L2572 [UTC]
WIDEBAND PLL FM DEMODULATOR; 宽带锁相环调频解调器型号: | L2572 |
厂家: | Unisonic Technologies |
描述: | WIDEBAND PLL FM DEMODULATOR |
文件: | 总14页 (文件大小:251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
L2572
LINEAR INTEGRATED CIRCUIT
WIDEBAND PLL FM
DEMODULATOR
DESCRIPTION
As a wideband PLL FM demodulator, the UTC L2572 is
intended for application in satellite tuners primarily.
The device includes all the necessary elements, with
external oscillator sustaining network and the exception of
loop feedback components, to form a PLL system operating
at frequencies up to 800MHz completely.
SOP-16
An AFC with window adjust (whose output signal can be
used to correct for any frequency drift at the head end local
oscillator) is provided.
*Pb-free plating product number: L2572L
FEATURES
* Constant voltage and constant current control
* Single chip PLL system for wideband FM demodulation
* Simple low component count application
* Allows for application of threshold extension
* Fully balanced low radiation design
* High operating input sensivity
* Improved VCO stability with variations in supply or
temperature
* AGC detect and bias adjust
* 75Ω video output drive with low distortion levels
* Dynamic self biasing analog AFC
* Full ESD Protection
ORDERING INFORMATION
Ordering Number
Package
Packing
Normal
Lead Free Plating
L2572-S16-R
L2572-S16-T
L2572L-S16-R
L2572L-S16-T
SOP-16
SOP-16
Tape Reel
Tube
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Copyright © 2007 Unisonic Technologies Co., Ltd
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PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
PIN NAME
AFC PUMP
I/O
DESCRIPTION
Current pump, integrating the signal pulses into a DC voltage
Set the AFC deadband voltages corresponding the frequency
GND
1
2
I
I
AFC WINDOW ADJUST
VEE
3
4
OSCILLATOR+
OSCILLATOR-
AGC BIAS
I
I
Oscillator positive signal
Oscillator negative signal
Set the AGC bias
5
6
I
7
AGC OUTPUT
RF INPUT
O
I
Output AGC DC voltage
Input signal
8
9
RF INPUT
I
Input signal
10
11
12
13
14
15
16
VIDEO OUTPUT
VIDEO FEEDBACK-
VIDEO+
O
I
Output video signal
Feedback the video negative signal
Video positive signal
O
O
I
VIDEO-
Video negative signal
VIDEO FEEDBACK+
VCC
Feedback the video positive signal
Input VCC
AFC OUTPUT
O
Output AFC DC voltage
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L2572
LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
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L2572
LINEAR INTEGRATED CIRCUIT
TEST CONFIGURATION
BASE BAND VIDEO 1V p–p
VIDEO GENERATOR
TV SAT TEST TX
ROHDE &
ROHDE &
SCHWARZ SGPF
SCHWARZ SFZ
RF CARRIER FREQ 479.5MHz
FM MODULATION 13.5MHz P–P
PRE–EMPHASISED VIDEO
TEST APPLICATION BOARD
See Fig. 1 for details
MONTFORD TEST OVEN
PRE EMPHASISED BASE BAND VIDEO
VIDEO AMPLIFIER/
DE EMPHASISED NETWORK
DE EMPHASISED BASE BAND VIDEO 1V p–p
VIDEO ANALYSER
ROHDE & SCHWARZ UAF
Using the above test configuration the video drive characteristics measurements were made. In the Electrical
Characteristics Table the maximum figures recorded coincide with extremes of supply voltage and high temperatures.
There’s no adjustment to the recorded figures has been made to compensate for the effects of temperature on the
external components of the application test board, in the varactor diodes particularly. Attention to temperature
compensation of the external circuitry will result in performance figures closer to the stated typical figures if operation
of the device at high ambient temperatures is envisaged.
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LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS (VEE=0V)
PARAMETER
SYMBOL
VCC
RATINGS
-0.3~7
UNIT
V
Supply Voltage
RF Input Voltage
RF Input DC Offset
Oscillator ± DC Offset
Video ± DC Offset
VIN(RF)
2.5
VP-P
V
VIN_RF(OFF)
VOSC(OFF)
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
-0.3~VCC+0.3
250
V
V
VVDO(OFF)
Video Feedback ± DC Offset
Video Output DC Offset
AFC Pump DC Offset
V
V
V
VAFC(OFF)
AFC Disable DC Offset
AFC Deadband DC Offset
AGC Bias DC Offset
V
V
V
VAGC(OFF)
PD
AGC Output DC Offset
Power Dissipation (at 5.5V)
ESD Protection - Pin 1 to 15
ESD Protection - Pin 16
Junction Temperature
Storage Temperature
V
mW
kV
kV
°C
°C
2
ESD
1.7
TJ
150
TSTG
-55~125
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
THERMAL DATA
Parameter
SYMBOL
ΘJA
RATINGS
111
Unit
°C/W
°C/W
Junction to Ambient
Junction to Case
ΘJC
41
ELECTRICAL CHARACTERISTICS
(Ta = -20°C~+80°C, VCC = +4.5V ~ +5.5V. Either design or production test guarantee the electrical characteristics.
Unless otherwise stated they apply within the specified ambient temperature and supply voltage.)
PARAMETER
Supply Current
SYMBOL
VCC
CONDITIONS
MIN TYP MAX UNIT
36
40
mA
Operating Frequency
Input Sensitivity
FOPR
300
800
MHz
dBm
dBm
Preamp limiting
-40
Input Overload
0
VCO Sensitivity (dF/dV)
Refer to Fig. 1
25
32
25
39 MHz/V
Refer to Fig. 1 with13.5MHz p-p
deviation
VCO linearity
%
VCO Supply Stability
See note 5
2.0
20
MHz/V
KHz/°C
VCO Temperature Stability
See note 5
Differential loop filter
Single ended loop filter
0.5
0.25
Phase Detector Gain
V/rad
Loop Amplifier Input Impedance
Loop Amplifier Output Impedance
Loop Amplifier Open Loop Gain
Loop Amplifier Gain Bandwidth Product
Loop Amplifier Output Swing
RIN
450 570 700
Ω
Ω
ROUT(LOOP)
25
38
dB
BW
240
1.2
MHz
Vp-p
Ω
Video Drive Output Impedance
ROUT(VIDEO)
55
75
95
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LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNIT
VIDEO DRIVE
Luminance Nonlinearity
Differential Gain
1KΩ load, See note 3 and 4
75KΩ load, See note 3 and 4
75KΩ load, See note 3 and 4
See notes 1, 3 and 4
1KΩ load, See note 2 and 4
1KΩ load, See note 3 and 4
1KΩ load, See note 3 and 4
Maximum load voltage drop 2V
1.9
0.5
1.0
5
2.5
3
%
%
Degree
dB
dB
%
Differential Phase
Intermodulation
Signal/noise
Tilt
-40
66
72
0.3
0.4
3
2
Baseline Distortion
%
AGC Output Current
IOUT
IBIAS
10
0
400
250
400
µA
AGC Bias Current
µA
400µA gives 1.5V deadband
window
0
µA
AFC Window Current
AFC Charge Pump Current
AFC Leakage Current
50
µA
µA
V
ILEAK
With charge pump disabled
10
AFC Output Saturation Voltage
VO(SAT) AFC output enabled
0.4
Note 1. Input modulation’s product f 1 at 4.43MHz, 13.5MHz p–p deviation and f 2 at 6MHz p–p deviation, (PAL
chroma and sound subcarriers).
2. To output rms noise in 6MHz bandwidth with no input modulation, ratio of output video signal with input
modulation at 1MHz, 13.5MHz p–p deviation.
3. Output voltage is 600mV pk–pk and input test signal pre–emphasised video 13.5MHz p–p deviation.
4. See page 4
5. Assuming ambient temperature of +20°C and operating frequency of 479.5MHz set with VCC @ 5.0V. Only
applies to application shown in Fig. 1 also refer to Fig. 4.
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L2572
LINEAR INTEGRATED CIRCUIT
APPLICATION CIRCUIT
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
The UTC L2572 as optimized for application in satellite receiver systems and requiring a minimum external
component count is a wideband PLL FM demodulator. It includes all the elements required to construct a phase
locked loop circuit, with the exception of an AFC detector circuit for generation of error signal to correct for any
frequency drift in the outdoor unit local oscillator, and tuning components for the local oscillator contains a block
diagram and Fig. 1 contains the typical application.
Fig. 2-1 contains the internal pin connections
In applications the second satellite IF frequency of typically 479.5 or 402MHz is fed to the RF preamplifier normally,
which depending on application and layout has a working sensitivity of typically -40 dBm. An RF level detect circuit,
which generates an AGC signal that can be used for controlling the gain of the IF amplifier stages is contained in the
preamplifier, so it can be maintaining a fixed level to the RF input of the UTC L2572, for optimum threshold
performance. The AGC circuit’s bias point can be adjusted to cater for device input power and variation in AGC line
voltage requirement. Fig. 5 shows the typical AGC curves are shown in. That the device is recommended that be
operated with an input signal between -30 and -35dBm. That can ensure optimum linearity and threshold
performance, and when over the typical sensitivity of -40dBm can give a good safety margin.
The preamplifier’s output is fed to the mixer section which is of balanced design for low radiation. In this stage the
RF signal is mixed with which is generated by an on–board oscillator, the local oscillator frequency. The oscillator
block is optimized for high linearity over the normal deviation range and uses an external varactor tuned sustaining
network. Fig. 3 contains a typical frequency versus voltage characteristic for the oscillator. Fig.4 shows the typical
stability that he loop output is designed to compensate for first order temperature variation effects.
The mixer’s output is then fed to the loop amplifier around which feedback is applied to effect loop transfer
characteristic. Feedback could be applied either in single ended or differential mode; both modes should give the
same loop response if the appropriate phase detector gains are assumed in calculating loop filters.
The loop amplifier drives a 75Ω output impedance buffer amplifier, which could be connected to a 75Ω load and
used to drive a high input impedance stage giving greater linearity and approximately 6dB higher demodulated signal
output level too.
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L2572
LINEAR INTEGRATED CIRCUIT
INTERNAL CIRCUITS
VCC
AGC Bias
VREF:2.7V
VREF:2V
AGC Output
Fig. 2-1 AGC Output
Fig. 2-2 AGC Bias Adjust
AFC WINDOW
VREF:36V
2X1500
RF Input
VREF:1.6V
Fig. 2-4 AFC Window Adjust
Fig. 2-3 RF Input
VCC
AFC Pump
Video +
Video -
10K
AFC OUTPUT
330
330
2mA
2mA
Fig. 2-5 AFC Output Stage
Fig. 2-6 Video Amp Output
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L2572
LINEAR INTEGRATED CIRCUIT
INTERNAL CIRCUITS(Cont.)
From Phase Detector
2x570
VREF:1.2V
2X5K
VIDEO
FEEDBACK +
OSCILLATOR +
OSCILLATOR -
VIDEO
FEEDBACK -
Fig. 2-7 Local Oscillator
Fig. 2-8 Video amp feedback inputs
VCC
68
Output
Video
105
4mA
Fig. 2-9 Video Output Drive
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LINEAR INTEGRATED CIRCUIT
2.0
1.5
1.0
AGC Bias Resistor 5.1K
AGC Bias Current 297 A
AGC Load Resistor 3.9K
AGC Bias Resistor 10.5K
AGC Bias Current 150 A
AGC Load Resistor 4.7K
0.5
AGC Bias Resistor 32K
AGC Bias Current 52 A
AGC Load Resistor 10K
-70 -60 -50 -40 -30 -20 -10
RF Input Level (dBm) Unmodulated
0
VCC = 5.0 V
Fig.5 AGC Output Voltage for Differing Values of AGC Bias Resistor
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L2572
LINEAR INTEGRATED CIRCUIT
DESIGN OF PLL LOOP PARAMETERS
The UTC L2572 is normally used as a type 1 second order loop and can be represented by the above diagram.
For such a system the following parameters apply;
τ1 = C1.R1
τ2 = C1.R2
and
K0 KD
τ1 =
ωn2
2ζ
τ 2 =
ωn
where:
K0 is the VCO gain in radian seconds per volt
KD is the phase detector gain in volts per radian
ωn is the natural loop bandwidth
ξ is the loop damping factor
R1 is loop amplifier input impedance
Note: K0 is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
From these factors the loop 3dB bandwidth can be determined from the following expression;
ω32dB = ωn2 (2ζ 2 +1) ± ωn2 (2ζ 2 +1)2 +1
1
Which approximates to ω3dB = 2ωn when ζ =
2
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L2572
LINEAR INTEGRATED CIRCUIT
AFC FACILITY
An analog frequency error detect circuit, which generates DC voltage proportional to the integral of frequency error
is contained in UTC L2572.As the incident RF is high then the AFC voltage increases, as low then the voltage
decreases. ADC converts the AFC voltage can then be an to be read by the micro controller for frequency fine
tuning.
Around the aligned frequency the AFC detect circuit contains a deadband centre. From zero window to
approximately 25MHz width assuming an oscillator dF/dV of 15MHz/V the deadband can be adjusted. The AFC
voltage does not integrate if the incident RF is within this window, except by component leakage.
With reference to Fig. 6; the demodulated video is fed to a dual comparator which can be compared with two
reference voltages in normal operation, corresponding to the extremes of the deadband, or window. These voltages
are variable and the window adjust input can set it.
Two digital outputs corresponding to voltages above or below the voltage window, or frequency above or below
deadband can be produced by the comparators. These digital control signals can control a complimentary current
source pump. The current signals are then fed to an amplifier’s input. it is arranged as an integrator, so integrating
the pulses into a DC voltage.
Both the current source and sink are disabled if the frequency is correctly aligned, therefore the DC output voltage
can be constant. Due to component leakage there will be a small drift; the maximum drift can be calculated from
here:
dV
dt
I
Vcc
=
where
I =
,
C = CEXT
2500.C
REXT
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L2572
LINEAR INTEGRATED CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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