L8400 [UTC]
Analog Circuit, PDSO16;
| 型号： | L8400 |
| 厂家： | 
Unisonic Technologies |
| 描述： | Analog Circuit, PDSO16 光电二极管 |
| 文件： | 总7页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTCL8400
LINEAR INTEGRATED CIRCUIT
FET BIAS CONTROLLER
DESCRIPTION
The UTC L8400 is designed to meet the bias requirements
of GaAs and HEMT FETs commonly used in satellite receiver
LNBs, PMR, cellular telephones etc. with a minimum of
external components.
With the addition of two capacitors and resistors the
devices provide drain voltage and current control for a
number of external grounded source FETs, generating the
regulated negative rail required for FET gate biasing whilst
operating from a single supply. This negative bias, at –3
volts, can also be used to supply other external circuits.
The UTC L8400 contains four bias stages respectively. In
setting drain current the L8400 two resistors allows individual
FET pair control to different levels. This allows the operating
current of input FETs to be adjusted to minimize noise, whilst
the following FET stages can separately be adjusted for
maximum gain. The UTC L8400 gives 2.2 volts drain whilst .
These devices are unconditionally stable over the full
working temperature with the FETs in place, subject to the
inclusion of the recommended gate and drain capacitors.
These ensure RF stability and minimal injected noise.
It is possible to use less than the devices full complement
of FET bias controls, unused drain and gate connections can
be left open circuit without affecting operation of the
remaining bias circuits.
SSOP-16(150mil)
FEATURES
* Provides bias for GaAs and HEMT FETs
* Drives up to four or six FETs
* Dynamic FET protection
* Drain current set by external resistor
* Regulated negative rail generator requires only
2 external capacitors
* Choice in drain voltage
* Wide supply voltage range
In order to protect the external FETs the circuits have been
designed to ensure that, under any conditions including
power up/down transients, the gate drive from the bias
circuits cannot exceed the range –3.5V to 0.7V.Furthermore if
the negative rail experiences a fault conditions, such as
overload or short circuit, the drain supply to the FETs will shut
down avoiding excessive current flow.
APPLICATIONS
* Satellite receiver LNBs
* Private mobile radio(PMR)
* Cellular telephones
1
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
G1
D2
G2
GND
N/C
VCC
D3
G3
D4
G4
RCAL2
RCAL1
CSUB
CNB1
CNB2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Vcc
VALUE
-0.6~15
100
0~15
100
UNIT
V
mA
mA
mA
Supply Voltage
Supply Current
Drain Current (per FET) (set by RCAL1 and RCAL2 )
Output Current
ICC
Io
Power Dissipation (Ta=25°C)
500
PD
mW
Operating Temperature
Storage Temperature
Topr
TStg
-40~70
-50~85
°C
°C
ELECTRICAL CHARACTERISTICS(Unless otherwise specified)
(Ta = 25 °C,Vcc=5V,ID=10mA( RCAL1=33kΩ;RCAL2=33kΩ)
PARAMETER
Supply Voltage
SYMBOL
Vcc
TEST CONDITIONS
MIN
5
TYP
-3
MAX
UNIT
V
12
ID1to ID4=0
10
50
-2
mA
mA
V
Supply Current
Substrate Voltage
ICC
ID1 to ID4=10mA
VSUB
(Internally
generated)
-3.5
ISUB =0
I
-2
V
SUB = -200µA
Output Noise
Drain Voltage
Gate Voltage
Oscillator Freq.
END
ENG
fO
CG=4.7nF,CD=10nF
CG=4.7nF,CD=10nF
0.02
0.005
800
Vpkpk
Vpkpk
kHz
200
350
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UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
DRAIN CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
8
TYP
10
MAX
12
UNIT
mA
Current
ID
Current Change
With Vcc
ΔIDV
ΔIDT
VD
Vcc=5 to12V
Tj= -40 to +70°C
0.02
0.05
2.2
%/V
%/V
v
With Tj
Voltage
2
2.4
Voltage Change
ΔVDV
ΔVDT
With Vcc
Vcc=5 to12V
Tj= -40 to +70°C
0.5
50
%/V
ppm
With Tj
GATE CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
-30
TYP
MAX
2000
UNIT
μA
Outpt Current Range
IGO
Output Voltage
Output Low
VoL
ID1 to ID4=12mA
IG1 to IG4=0
-3.5
-3.5
0
-2
-2
1
V
V
V
ID1 to ID4=12mA
IG1 to IG4= -10μA
ID1 to ID4=8mA
IG1 to IG4=0
Output High
NOTES:
VOH
1.
The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors,
CNB and CsuB of 47nFare required for this purpose.
2.
The characteristics are measured using two external reference resistors RCAL1 and RCAL2 of value 33kΩ wired
from pins RCAL1/2 to ground. For the L8400, resistor RCAL1 sets the drain current of FETs 1and 2,resistor RCAL2
sets the drain current of FETs 3 and 4.
3.
4.
Noise voltage is not measured in production.
Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs.
CG, 4.7nF ,are connected between gate outputs and ground,CD,10nF,are connected between drain outputs and
ground.
3
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS
16
Note :Operation with loads>200
is not guranteed.
μA
Vcc =5V
14
-0.0
12
10
8
-0.5
-1.0
-1.5
Vcc =5V
Vcc =6V
6
4
-2.0
-2.5
2
0
-3.0
Vcc =8V
0.6
Vcc =10V
0.8 1.0
0
20
40
60
80
100
0
0.2
0.4
Rcal (k)
External Vsub Load (mA)
JFET Drain Current vRcal
Vsub v External Load
2.4
2.3
2.2
Vcc =5V
Vcc =6V
Vcc =8V
Vcc =10V
12
2.1
2.0
2
4
6
8
10
14
16
Drain Current (mA)
JFET Drain Voltage v Drain Current
4
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DIAGRAM
-
Vcc
+
+
-
ID
Sense
DN
VD
Set
ON
+
-
RCAL
ID
Set
GN
+
-
RCAL
A
20µ
SetS ID
CSUB
Negative
Supply
Gen.
GND
CSUB
CNB1
CNB2
CNB
FUNCTIONAL DESCRIPTION
The L8400 devices provide all the bias requirements for external FETs, including the generation of the negative
supply required for gate biasing, from the single supply voltage.
The diagram above shows a single stage from the L8400. It contains 4 such stages. The negative rail generator is
common to all devices.
The drain voltage of the external FET QN is set by the L8400 device to its normal operating voltage. This is
determined by the on board VD Set reference, this is nominally 2.2 volts .
The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate
of the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an
external resistor RCAL. The L8400 device has the facility to program different drain currents into selected FETs.
Two RcAL inputs are provided. For the L8400, resistor RcAL1 sets the drain current of FETs 1 and 2,resistor RCAL2
sets the drain current of FETs 3 and 4.
Since the FET is a depletion mode transistor, it is usually necessary to drive its gate negative with respect to ground
to obtain the required drain current. To provide this capability powered from a single positive supply, the device
includes a low current negative supply generator. This generator uses an internal oscillator and two external
capacitors, CNB and CSUB.
5
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
*L1
CD
*C2
10nF
L8400
Q1
*L2
Vcc
GN
DN
*C3
CG
4.7nF
RCAL2
RCAL1
CSUB
GND
CNB1
*Stripline Elements
CNB2
CNB
47nF
CSUB
47nF
RCAL2
33K
RCAL1
33K
APPLICATIONS INFORMATION
The device is a partial application circuit for the L8400 showing all external components required for appropriate
biasing. The bias circuits are unconditionally stable over the full temperature range with the associated FETs and
gate and drain capacitors in circuit.
Capacitors CD and CG ensure that residual power supply and substrate generator noise is not allowed to affect other
external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF
feedthrough between stages via the L8400 device. These capacitors are required for all stages used. Values of 10nF
and 4.7nFrespectively are recommended however this is design dependent and any value between 1nFand
100nFcould be used.
The capacitors CNB and CSUB are an integral part of the L8400 negative supply generator. The negative bias voltage
is generated on-chip using an internal oscillator. The required value of capacitors CNB and CsuB is 47nFThis
generator produces a low current supply of approximately –3 volts. Although this generator is intended purely to bias
the external FETs, it can be used to power other external circuits via the CsUB pin.
Resistors RcAL1/2 sets the drain current at which all external FETs are operated. The L8400 device has the facility
to program different drain currents into selected FETs. Two RcAL inputs are provided. For the L8400, resistor RcAL
sets the drain current of FETs 1 and 2,resistor RCAL2 sets the drain current of FETs 3 and 4.If the same drain current
is required for all FETs on either device then pins RCAL1 and RCAL2 can be wired together and shunted to ground by
a single calibration resistor of half normal value.
If any bias control circuit is not required, its related drain and gate connections may be left open circuit without
affecting the operation of the remaining bias circuits. If all FETs associated with a current setting resistor are omitted,
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UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
UTCL8400
LINEAR INTEGRATED CIRCUIT
the particular RCAL should still be included. The supply current can be reduced, if required, by using a high value
RCAL resistor(e.g.470K)
The L8400 has been designed to protect the external FETs from adverse operating conditions. With a JFET
connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range –3.5V to
0.7V,under any conditions including power up and powerdown transients. Should the negative bias generator be
shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to
FETs is shut down to avoid damage to the FETs by excessive drain current..
The following diagrams show the L8400 in typical LNB applications. Within each FET gain stage the numbering
system indicates how the bias stages relate to the application circuits. This is important when RCAL values are used
to set differing drain currents.
Dual standard or enhanced LNB block diagram
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R123-001,A
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