LR1802 [UTC]

1.0A LOW DROPOUT LINEAR REGULATOR WITH OUTPUT;


型号：	LR1802
厂家：	Unisonic Technologies
描述：	1.0A LOW DROPOUT LINEAR REGULATOR WITH OUTPUT 输出元件
文件：	总5页 (文件大小：203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO., LTD

LR1802

Preliminary

LINEAR INTEGRATED CIRCUIT

1.0A LOW DROPOUT LINEAR

REGULATOR WITH OUTPUT

VOLTAGE SETTING OPTIONS



DESCRIPTION

The UTC LR1802 is a typical LDO that features output voltage

HSOP-8

setting options, very low dropout voltage as low as 0.3V at output

current 1.0A, an enable input and the soft-start reduces inrush

current of the load capacitors and minimizes stress on the input

power source during start-up. An enable pin to further reduce

power dissipation while shutdown..

The UTC LR1802 is stable with any type of output capacitor of

10µF or more. A precision reference and feedback control deliver

3% accuracy.



FEATURES

* Low V_INand wide V_INrange: 1.0V~5.5V

* Bias voltage (V_PP) range: 3.0V~5.5V

* Low V_OUTrange: 0.8V~3.3V

* 300mV dropout @1.0A, V_PP=5V

* 3% output Voltage

* output voltage setting options

* Programmable soft-start provides linear voltage startup

* Stable with output capacitor≥10µF



ORDERING INFORMATION

Ordering Number

Lead Free

Package

HSOP-8

Packing

Tape Reel

Halogen Free

LR1802G-SH2-R

LR1802L-SH2-R

LR1802G-SH2-R

(1) R: Tape Reel

(2) SH2: HSOP-8

(3) G: Halogen Free and Lead Free, L: Lead Free

(1)Packing Type

(2)Package Type

(3)Green Package



MARKING

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LR1802

Preliminary

LINEAR INTEGRATED CIRCUIT



PIN CONFIGURATION

V_IN

V_OUT

ADJ

SSC

V_PP

GND

SET1 3

SET2 4

5 EN



PIN DESCRIPTION

PIN NO.

PIN NAME

V_IN

DESCRIPTION

Input voltage. Large bulk capacitance should be placed closely to this pin, A 10uF

ceramic capacitor is recommended at this pin

V_PP

Input voltage for controlling circuit

SET1

SET2

Output voltage setting pin. Pull-high: 1, Pull-Low; 0

Enable input. Pulling this pin below 0.4V turns the regulator off, reducing the quiescent

current to a fraction of its operating value. The device will be disabled if this pin is left

open

SSC

ADJ

Inrush current limit pin

Resistor ratio of external feedback for output voltage by VO=0.8*(R1+R2)/R2 Volts

The power output of the device. A pull low resistance exists when device deactivated by

EN pin

V_OUT



BLOCK DIAGRAM

V_OUT

V_IN

Gate

Driver

Thermal

Shutdown

V_PP

SSC

0.8V

ADJ

GND

SET1

SET2

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LR1802

Preliminary

LINEAR INTEGRATED CIRCUIT



ABSOLUTE MAXIMUM RATING

PARAMETER

SYMBOL

V_IN

RATINGS

UNIT

Input Voltage

(V_PP, V_IN, EN, ADJ, V_OUT, SSC, SET1, SET2)

Power Dissipation

P_D

T_J

Internally limited

150

°C

Junction Temperature

Storage Temperature Range

Operation Conditions

T_STG

-65≤T_J≤+150

V_INVoltage

V_IN

V_PP

1.0~5.5

3~5.5

V_PPVoltage

(V_PP≥V_INfor normal operation) Temperature Range

T_OPR

-40 ≤ T_A≤ +85

°C

Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.

Absolute maximum ratings are stress ratings only and functional device operation is not implied.



THERMAL CHARACTERISTICS

PARAMETER

SYMBOL

RATINGS

143

UNIT

°C/W

Junction To Ambient

θ_JA



ELECTRICAL CHARACTERISTICS

V_PP=5V, V_IN=3.3V, V_EN=V_PP, I_OUT=10mA, C_IN=10µF, C_OUT=10µF, T_A=T_J=25°C

The device is not guaranteed to function outside its operating conditions. Parameters with MIN and/ of MAX limits

are 100% tested at +25°C unless otherwise specified.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

1.0

TYP

MAX UNIT

V_IN

Input Voltage Range

V_IN

V_IN>V_O

5.5

V_PP

V_PPVoltage Range

V_PP

V_PP>V_O+1V and V_PP>3V

V_OUT

Externally set voltage

V_IN=V_O+0.5V

Output Voltage

V_O

V_O(S)-3% V_O(S)V_O(S)+3%

V_O(S): V_OVoltage setting

V_IN=( V_O+0.5V)~5V, I_OUT=100mA

(△V_OUT/△V_IN*V_OUT

f=1kHz

Line Regulation

0.8

%/v

Ripple ejection

0.6

300

500

Load Regulation

Dropout Voltage

Short Circuit Current

V_OUTPull Low Resistance

V_OUT

10mA≤I_O≤1A

V_D

I_O=1A, V_O=1.8V

Ω

V_EN=0V

C_SS: Capacitor on SSC pin

V_IN=V_O+1V, I_OUT=1A, C_SS=3nF

Time period when V_SSCrises from

0~0.8V

0.6

Soft Start Time

T_SS

C_SS: Capacitor on SSC pin

V_IN=V_O+1V, I_OUT=1A, C_SS=0nF

Time period when V_SSCrises from

0~0.8V

0.06

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LR1802

Preliminary

LINEAR INTEGRATED CIRCUIT



ELECTRICAL CHARACTERISTICS (Cont.)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

0.8

MAX UNIT

ADJ

Reference Voltage

Adjust Pin Current

V_REF

I_ADJ

V_ADJ= V_O

0.784

0.816

100

EN Pin Voltage High

EN Pin Voltage Low

EN Pin Down Resistor

SET1, SET2

V_ENH

V_ENL

R_EN

1.6

0.4

2.0

MΩ

V_SET1H

V_SET2H

SET1, SET2 Pin Voltage High

SET1, SET2 Pin Voltage Low

V_PP-0.5

V_SET1L

0.5

V_SET2L

Over Temperature Protection

Over Temperature

T_OT

150

°C

Over Temperature Hysteresis

T_OTHY



OUTPUT VOLTAGE SETTING OPTION

Internal V_Osetting table:

SET1

SET2

V_OUT

0.9

1.05

1.2

1.5

ADJ mode

1.5

1.8

2.5

3.3

* 0: pin voltage low, 1: pin voltage high, F: pin floating

External V_Osetting:

V_O={(R1+R2)/R2}*V_ADJ

* If ADJ pin is connected to gnd, V_Ofollows internal V_Osetting

* ADJ pin has the priority than set1 pin and set2 pin

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LR1802

Preliminary

LINEAR INTEGRATED CIRCUIT



TYPICAL APPLICATION CIRCUIT

0.8(R1R2)

R2<120KΩ is recommended

V^OUT

Volts

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products specifications of any and all UTC products described or contained herein.

UTC products are not designed for use in life support appliances, devices or systems where malfunction

of these products can be reasonably expected to result in personal injury. Reproduction in whole or in

part is prohibited without the prior written consent of the copyright owner. UTC reserves the right to

make changes to information published in this document, including without limitation specifications and

product descriptions, at any time and without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

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