LS3718-S28-R [UTC]

20-BIT SERIAL TO PARALLEL CONVERTER; 20位串行到并行转换


型号：	LS3718-S28-R
厂家：	Unisonic Technologies
描述：	20-BIT SERIAL TO PARALLEL CONVERTER 20位串行到并行转换
文件：	总8页 (文件大小：86K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO., LTD

LS3718

CMOS IC

20-BIT SERIAL TO PARALLEL

CONVERTER

DESCRIPTION

The UTC LS3718 is a 20-bit serial to parallel converter utilizing

CMOS Technology. It is incorporates control circuit, shift register,

latch and driver into a single ship. It is suitable for MCU interface.

The effective interface assignment of MPU is available as the

connection between UTC LS3718 and MPU is required only 4

lines.

The device is designed to operate up to 5MHz. When the serial

data input to the DATA terminal and the data is output from parallel

output buffer through serial in parallel out shift register and parallel

data latches.

The data can through the shift register serial output to the SO

terminal. Therefore the UTC LS3718 can cascade connection to

expand the output data number.

*Pb-free plating product number: LS3718L

The hysteresis input circuit realizes wide noise margin and the

high drive-ability output buffer (25mA) can drive LED directly.

FEATURES

* 20-Bit serial in parallel out

* Cascade connection

* Operating voltage

* Hysteresis input

* Output current

5V±10%

0.5V typ

25mA

* Operating frequency

5MHz or more

ORDERING INFORMATION

Ordering Number

Package

Packing

Normal

Lead Free Plating

LS3718-S28-R

LS3718-S28-T

LS3718L-S28-R

LS3718L-S28-T

SOP-28

Tape Reel

Tube

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LS3718

CMOS IC

PIN CONFIGURATION

P10

P11

V_DD

P12

P13

P14

V_SS

P15

P16

P17

V_SS

P18

P19

P20

CLR

STB

CLK

DATA

PIN DESCRIPTION

PIN NO PIN NAME

I/O

DESCRIPTION

P10

P11

P12

P13

P14

V_SS

P15

P16

P17

P18

P19

P20

Parallel Data Output Pin 9

Parallel Data Output Pin 10

Parallel Data Output Pin 11

Parallel Data Output Pin 12

Parallel Data Output Pin 13

Parallel Data Output Pin 14

GND

Parallel Data Output Pin 15

Parallel Data Output Pin 16

Parallel Data Output Pin 17

Parallel Data Output Pin 18

Parallel Data Output Pin 19

Parallel Data Output Pin 20

Serial Data Output Pin

Serial Data Input Pin

DATA

CLK

STB

CLR

Clock Signal Input Pin

Data Strobe, Low Actived

Data Reset, Low Actived

Parallel Data Output Pin 1

Parallel Data Output Pin 2

GND

V_SS

Parallel Data Output Pin 3

Parallel Data Output Pin 4

Parallel Data Output Pin 5

Parallel Data Output Pin 6

Parallel Data Output Pin 7

Parallel Data Output Pin 8

Power Supply

V_DD

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LS3718

CMOS IC

BLOCK DIAGRAM

P1~P20

driver

STB

CLR

control

latch

CLK

shift register

DATA

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LS3718

CMOS IC

ABSOLUTE MAXIMUM RATINGS (Ta=25℃)

PARAMETER

SYMBOL

V_DD

RATINGS

-0.5~+7.0

V_SS-0.5~V_DD+0.5

±25

UNIT

Supply Voltage

Input Voltage

V_IN

Output Voltage

V_OUT

I_OUT

Output Current

℃

Power Dissipation

Junction Temperature

Operating Temperature

Storage Temperature

P_D

500

T_J

+125

T_OPR

T_STG

-25 ~ +85

-40 ~ +150

℃

Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.

Absolute maximum ratings are stress ratings only and functional device operation is not implied.

ELECTRICAL CHARACTERISTICS (V_DD=4.5~5.5V, V_SS=0V, Ta=25℃)

PARAMETER

SYMBOL

V_DD

TEST CONDITIONS

MIN

4.5

TYP

MAX

5.5

UNIT

Operating Voltage

Operating Current

Input Leakage Current

I_S

V_IH=V_DD, V_IL=V_SS

0.1

µA

I_I(LEAK)

V_IH

V_IN=0~V_DD

-10

0.7V_DD

V_SS

High-Level

V_DD

Input Voltage

Low-Level

High-Level

Low-Level

V_IL

0.3 V_DD

V_DD

V_OH

I_OH=-0.4mA

I_OL=+3.2mA

I_OH=-25mA

I_OH=-15mA

I_OH=-10mA

I_OL=+25mA

I_OL=+15mA

I_OL=+10mA

4.0

4.97

0.11

Output Voltage

SO Terminal

V_OL

V_SS

0.4

V_DD-1.5 V_DD-0.5 V_DD

V_DD-1.0 V_DD-0.3 V_DD

V_DD-0.5 V_DD-0.2 V_DD

High-Level

Low-Level

V_OHP

P1~P20

Terminals (Note)

Output Voltage

V_SS

0.5

0.3

0.2

1.5

0.8

0.4

V_OLP

Note: Specified value represent output current per pin. When use, total current consideration and less than power

dissipation rating operation should be required.

SWITCHING CHARACTERISTICS (V_DD=4.5~5.5V, V_SS=0V, Ta=-20~75℃)

PARAMETER

SYMBOL

t_SD

TEST CONDITIONS

DATA-CLK

MIN

TYP

MAX

UNIT

Data Set-up Time

Data Hold Time

Set-up Time

t_HD

CLK-DATA

STB-CLK

CLK-STB

CLK-SO

t_SSTB

t_HSTB

t_PD

Hold Time

100

t_PDPCK CLK-P1~P20

t_PDPSTB STB-P1~P2

Output Delay Time

_PDPCLR CLR-P1~P20

f_MAX

Max. Operating Frequency

Note: C_OUT=50pF

MHz

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LS3718

CMOS IC

SWITCHING CHARACTERISTICS TEST WAVEFORM

f_MAX

CLK

t_SD

DATA

STB

t_HD

t_HSTB

t_SSTB

CLK

t_PD

CLK

t_PDpck

STB

P1~P 20

CLK

STB

t_PDSTB

P1~P 20

CLR

DATA

t_PDPCLR

P1~P 20

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LS3718

CMOS IC

FUNCTION DESCRIPTION

RESET

When the CLR terminal is "L" level, all latches are reset and all of parallel output are "L" level.

Normally, the CLR terminal should be "H" level.

DATA TRANSMISSION

When the STB terminal is "H" level and input the clock signal to the CLK terminal, the serial data input the DATA

terminal and shift in the shift register by synchronizing at rising edge of the clock signal.

When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latch.

Even if the STB terminal is "L" level, the input clock signal shift the data in the shift register, therefore, the clock

signal controlled is needed.

CASCADE CONNECTION

The serial data input from DATA terminal and output from the SO terminal through internal shift register

unrelated to the CLR and STB status.

Furthermore, the 4 input terminals have a hysteresis characteristic by using the schmitt trigger structure to

decrease the noise.

CLK

STB

CLR

DESCRIPTION

All latch are reset (the data in the shift register is not change). All of

parallel outputs are "L".

The serial data input from DATA terminal to the shift register (the data in

the latch is not change).

The data in the shift register transfer to the latch. And the data in the

latch output from the parallel output.

The CLK input in the STB="L" and CLR="H" state, the data shift in the

shift register and latched data also change in accordance with the shift

Note: X: Don’t care

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LS3718

CMOS IC

TIMING CHART

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LS3718

CMOS IC

TYPICAL APPLICATION CIRCUIT

Cascade Connection

P1~P20

UTC

LS3718

STB

DATA CLK

CLR

STB

DATA CLK

CLR

MPU

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or

other parameters) listed in products specifications of any and all UTC products described or contained

herein. UTC products are not designed for use in life support appliances, devices or systems where

malfunction of these products can be reasonably expected to result in personal injury. Reproduction in

whole or in part is prohibited without the prior written consent of the copyright owner. The information

presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice.

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