MC14511_18 [UTC]
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER;
| 型号： | MC14511_18 |
| 厂家： | 
Unisonic Technologies |
| 描述： | BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER 驱动 CD |
| 文件： | 总8页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
MC14511
CMOS IC
BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
DESCRIPTION
The UTC MC14511 BCD–to–seven segment latch/decoder/driver
DIP-16
is constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic
structure. The circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output drive capability.
Lamp test (LT ), blanking (BI ), and latch enable (LE) inputs are used
to test the display, to turn-off or pulse modulate the brightness of the
display, and to store a BCD code, respectively. It can be used with
seven-segment light-emitting diodes (LED), incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
SOP-16
FEATURES
* Low Logic Circuit Power Dissipation
* High–Current Sourcing Outputs (Up to 25 mA)
* Latch Storage of Code
* Blanking Input
* Lamp Test Provision
* Readout Blanking on all Illegal Input Combinations
* Lamp Intensity Modulation Capability
* Time Share (Multiplexing) Facility
* Supply Voltage Range = 3.0V ~ 18V
ORDERING INFORMATION
Ordering Number
Lead Free
Package
Packing
Halogen Free
MC14511L-D16-T
MC14511G-D16-T
MC14511G-S16-R
DIP-16
Tube
MC14511L-S16-R
SOP-16
Tape Reel
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Copyright © 2018 Unisonic Technologies Co., Ltd
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MC14511
CMOS IC
MARKING
DIP-16
SOP-16
PIN CONFIGURATION
B
1
2
3
4
5
6
16
15
14
13
12
11
VDD
f
C
LT
BI
a
g
g
f
b
a
e
c
LE
D
b
c
d
7
8
d
e
10
9
A
Vss
DISPLAY
0
1
2
3
4
5
6
7
8
9
TRUTH TABLE
Inputs
Outputs
e
LE
BI
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LT
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
C
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
A
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
a
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
b
c
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
d
f
g
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
Display
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
*
1
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
8
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
*
X=Don’t Care
*Depends upon the BCD code previously applied when LE=0
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MC14511
CMOS IC
BLOCK DIAGRAM
BI
4
13
a
A
B
7
1
12
11
10
9 e
15
b
c
d
f
C
2
14
g
LT
3
D
6
5
VDD=PIN 16
VSS=PIN 8
LE
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MC14511
CMOS IC
ABSOLUTE MAXIMUM RATINGS (Note 3)
PARAMETER
SYMBOL
RATINGS
-0.5 ~ +18.0
-0.5 ~ VDD+0.5
10
UNIT
V
DC Supply Voltage Range
VDD
VIN
I
Input Voltage Range, All Inputs
DC Current Drain per Input Pin
Power Dissipation, per Package
Maximum Output Drive Current
(Source) per Output
V
mA
mW
PD
500
IOHMAX
25
50
mA
mA
Maximum Continuous Output
Power (Source) per Output (Note 2)
Operating Temperature Range
Storage Temperature Range
POHMAX
TA
-55 ~ +125
-65 ~ +150
C
C
TSTG
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. POHMAX = IOH (VDD – VOH
)
3.This device contains protection circuitry to protect the inputs against damage due to high static voltages or
electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit. A destructive high current mode may
occur if VIN and VOUT are not constrained to the range:
VSS ≤ (VIN or VOUT) ≤ VDD
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the
outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified)
VDD
VDC
5.0
10
TYP
(Note 1)
0
PARAMETER
SYMBOL
VOL
TEST CONDITIONS
MIN
MAX
UNIT
V
0.05
0.05
0.05
“0” Level
“1” Level
“0” Level
“1” Level
VIN=VDD or 0
0
0
15
Output Voltage
5.0
10
15
4.1
9.1
14.1
4.57
9.58
14.59
2.25
4.50
6.75
2.75
5.50
8.25
4.57
4.24
4.12
3.94
3.70
3.54
9.58
9.26
9.17
9.04
8.90
8.70
VOH
VIN=0 or VDD
V
V
V
5.0
10
15
VO=3.8 or 0.5 V
VO=8.8 or 1.0 V
VO=13.8 or 1.5V
VO=0.5 or 3.8 V
VO=1.0 or 8.8 V
VO=1.5 or 13.8 V
1.5
3.0
4.0
VIL
Input Voltage
(Note 1)
5.0
10
15
3.5
7.0
11
VIH
I
OH=0mA
4.1
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
3.9
3.4
9.1
9.0
8.6
5.0
10
V
V
Output Drive Voltage
(Source)
VOH
I
OH=0mA
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
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MC14511
CMOS IC
ELECTRICAL CHARACTERISTICS (Cont.) (TA=25°C, unless otherwise specified)
VDD
VDC
PARAMETER
SYMBOL
TEST CONDITIONS
OH=0mA
MIN
14.1
TYP
MAX
UNIT
V
I
14.59
14.27
14.18
14.07
13.95
13.70
0.88
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
VOL=0.4V
VOL=0.5V
VOL=1.5V
Output Drive Voltage
(Source)
14
VOH
15
13.6
5.0
10
15
15
0.51
1.3
3.4
Output Drive Current
(Sink)
IOL
2.25
8.8
mA
Input Current
Input Capacitance
IIN
CIN
±0.1
7.5
5.0
10
μA
pF
±0.00001
5.0
5.0
10
15
(Per Package) VIN =0 or VDD
IOUT=0μA
,
0.005
0.010
0.015
Quiescent Current
IDD
μA
μA
20
(Dynamic plus Quiescent, Per
Package)
(CL=50pF on all outputs, all
buffers switching)
5.0
10
15
IT=(1.9μA/kHz) f+IDD
IT=(3.8μA/kHz) f+IDD
IT=(5.7μA/kHz) f+IDD
Total Supply Current
(Notes 2 & 3)
IT
Notes: 1. Noise immunity specified for worst–case input combination..
Noise Margin for both “1” and “0” level =
1.0 V min @ VDD = 5.0 V
2.0 V min @ VDD = 10 V
2.5 V min @ VDD = 15 V
2. The formulas given are for the typical characteristics only at 25C.
3. To calculate total supply current at loads other than 50 pF:
IT (CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf.
Where: IT is inμA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency
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MC14511
CMOS IC
SWITCHING CHARACTERISTICS (Note 1) (CL=50pF, TA=25C)
VDD
VDC
5.0
10
PARAMETER
SYMBOL
tTLH
TEST CONDITIONS
Min
TYP
MAX
UNIT
ns
t
TLH=(0.40 ns/pF) CL+20 ns
tTLH=(0.25 ns/pF) CL+17.5 ns
tTLH=(0.20 ns/pF) CL+15 ns
40
30
25
80
60
50
Output Rise Time
Output Fall Time
15
5.0
10
15
t
THL=(1.5 ns/pF) CL+50 ns
tTHL=(0.75 ns/pF) CL+37.5 ns
tTHL=(0.55 ns/pF) CL+37.5 ns
125
75
65
250
150
130
1280
500
350
1440
580
400
750
300
220
970
400
320
625
250
180
625
250
180
tTHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tsu
ns
ns
5.0
10
15
t
PLH=(0.40 ns/pF) CL+620 ns
tPLH=(0.25 ns/pF) CL+237.5 ns
tPLH=(0.20 ns/pF) CL+165 ns
640
250
175
720
290
200
600
200
150
485
200
160
313
125
90
Data Propagation
Delay Time
5.0
10
15
tPHL=(1.3 ns/pF) CL+655 ns
tPHL=(0.60 ns/pF) CL+260 ns
tPHL=(0.35 ns/pF) CL+182.5 ns
5.0
10
15
tPLH=(0.30 ns/pF) CL+585 ns
tPLH=(0.25 ns/pF) CL+187.5 ns
tPLH=(0.15 ns/pF) CL+142.5 ns
Blank Propagation
Delay Time
ns
ns
5.0
10
15
tPHL=(0.85 ns/pF) CL+442.5 ns
tPHL=(0.45 ns/pF) CL+177.5 ns
tPHL=(0.35 ns/pF) CL+142.5 ns
5.0
10
15
tPLH=(0.45 ns/pF) CL+290.5 ns
tPLH=(0.25 ns/pF) CL+112.5 ns
tPLH=(0.20 ns/pF) CL+80 ns
tPHL=(1.3 ns/pF) CL+248 ns
tPHL=(0.45 ns/pF) CL+102.5 ns
tPHL=(0.35 ns/pF) CL+72.5 ns
Lamp Test
Propagation Delay
Time
5.0
10
15
313
125
90
5.0
10
15
100
40
30
Setup Time
Hold Time
ns
ns
ns
5.0
10
15
60
40
30
th
5.0
10
15
520
220
130
260
110
65
Latch Enable Pulse
Width
tWL
Note 1: The formulas given are for the typical characteristics only.
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MC14511
CMOS IC
SWITCHING TIME WAVEFORMS
20 ns
20 ns
VDD
90%
50%
A, B, AND C
1
2f
10%
Vss
VOH
50% DUTY CYCLE
ANY OUTPUT
50%
VOL
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C L loads.
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
VDD
90%
50%
LE
20 ns
20 ns
VDD
10%
Vss
VDD
90%
50%
th
tsu
INPUT C
10%
INPUT C
50%
Vss
VOH
tPLH
tPHL
Vss
VOH
90%
10%
OUTPUT g
50%
VOL
OUTPUT g
tTLH
tTHL
VOL
(b) Input D low, Inputs A, B, BI and LT high
(a) Inputs D and LE low, and Inputs A, B, BI and LT high
20 ns
20 ns
90%
VDD
50%
LE
10%
Vss
tWL
(c) Data DCBA strobed into Iatches.
Figure 2. Dynamic Signal Waveforms
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MC14511
CMOS IC
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
～1.7V
～
～
～ 1.7V
～
Vss
Vss
INCANDESCENT READOUT
FLUORESCENT READOUT
VDD
VDD
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
Vss
Vss
Vss OR APPROPRIATE
VOLTAGE BELOW Vss.
(CAUTION: Maximum working voltage=18.0V)
GAS DISCHARGE READOUT
LIQUID CRYSTAL(LCD) READOUT
APPROPRIATE
VOLTAGE
EXCITATION
(SQUARE WAVE, Vss TO VDD)
VDD
VDD
1/4 OF MC14070B
Vss
Vss
,
** A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
Direct dc drive of LCD s not recommended for life of
LCD readouts.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all UTC products described or contained herein.
UTC products are not designed for use in life support appliances, devices or systems where malfunction
of these products can be reasonably expected to result in personal injury. Reproduction in whole or in
part is prohibited without the prior written consent of the copyright owner. UTC reserves the right to
make changes to information published in this document, including without limitation specifications and
product descriptions, at any time and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
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