MJE13002L-A-T60-T [UTC]
Power Bipolar Transistor;
| 型号： | MJE13002L-A-T60-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | Power Bipolar Transistor |
| 文件： | 总9页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
HIGH VOLTAGE
FAST-SWITCHING NPN
POWER TRANSISTOR
DESCRIPTION
The UTC MJE13002 designed for use in high–volatge,
high speed,power switching in inductive circuit, It is particularly
suited for 115 and 220V switchmode applications such as
switching regulator’s,inverters, DC-DC converter, Motor
control, Solenoid/Relay drivers and deflection circuits.
FEATURES
*Collector-Emitter Sustaining Voltage:
CEO (sus)=300V.
*Collector-Emitter Saturation Voltage:
CE(sat)=1.0V(Max.) @Ic=1.0A, IB =0.25A
V
V
*Switch Time- tf =0.7μs(Max.) @Ic=1.0A.
ORDERING INFORMATION
Ordering Number
Pin Assignment
Package
Packing
Lead Free
Halogen Free
1
2
C
C
C
C
3
MJE13002L-x-T92-B
MJE13002L-x-T92-K
MJE13002L-x-T92-R
MJE13002L-x-T60-T
MJE13002G-x-T92-B
MJE13002G-x-T92-K
MJE13002G-x-T92-R
MJE13002G-x-T60-T
TO-92
TO-92
TO-92
TO-126
B
B
B
B
E
E
E
E
Tape Box
Bulk
Tape Reel
Tube
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Copyright © 2012 Unisonic Technologies Co., Ltd
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
300
UNIT
Collector-Emitter Voltage
Collector-Emitter Voltage
Emitter Base Voltage
VCEO(SUS)
VCEV
VEBO
IC
V
V
V
600
9
Continuous
Peak (1)
1.5
Collector Current
Base Current
A
A
A
ICM
3
Continuous
Peak (1)
IB
0.75
1.5
IBM
Continuous
Peak (1)
IE
2.25
4.5
Emitter Current
IEM
TA=25°C
1.4
Watts
MW/°C
Watts
MW/°C
°C
Derate above 25°C
TC=25°C
11.2
40
Total Power Dissipation
PD
Derate above 25°C
320
Junction Temperature
Storage Temperature
TJ
150
TSTG
-65 to +150
°C
THERMAL CHARACTERISTICS
PARAMETER
TO-92
SYMBOL
RATINGS
25
UNIT
°C/W
Junction to Case
θJC
TO-126
TO-92
3.12
122
Junction to Ambient
θJA
°C/W
°C
TO-126
89
Maximum Load Temperature for Soldering Purposes:
1/8” from Case for 5 Seconds
TL
275
Note: 1. Pulse Test : Pulse Width=5ms,Duty Cycle≤10%
2. Designer 's Data for “Worst Case” Conditions – The Designer 's Data Sheet permits the design of most
circuits entirely from the information presented. SOA Limit curves – representing boundaries on device
characteristics – are given to facilitate “Worst case” design.
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
ELECTRICAL CHARACTERISTICS (TC=25°C, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS
MIN TYP MAX UNIT
OFF CHARACTERISTICS (1)
Collector-Emitter Sustaining Voltage
VCEO(SUS) IC=10 mA , IB=0
VCEV=Rated Value, VBE(off)=1.5 V
300
1
Collector Cutoff Current
ICEV
V
CEV=Rated Value,
5
VBE(off)=1.5V,Tc=100°C
SECOND BREAKDOWN
Second Breakdown Collector Current with
bass forward biased (See Figure 5)
Clamped Inductive SOA with base reverse
biased (See Figure 6)
IS/IB
RBSOA
hFE1
hFE2
IC=0.5 A, VCE=2 V
IC=1 A, VCE=2 V
8
5
40
25
0.5
1
DC Current Gain
IC=0.5A, IB=0.1A
IC=1A, IB=0.25A
Collector-Emitter Saturation Voltage
VCE(SAT)
V
V
IC=1.5A, IB=0.5A
3
IC=1A, IB=0.25A,TC=100°C
IC=0.5A, IB=0.1A
1
1
Base-Emitter Saturation Voltage
V BE(SAT)
IC=1A, IB=0.25 A
1.2
1.1
IC=1A, IB=0.25A,TC=100°C
DYNAMIC CHARACTERISTICS
Current-Gain-Bandwidth Product
Output Capacitance
fT
IC=100mA, VCE=10 V, f=1MHz
VCB=10V, IE=0, f=0.1MHz
4
10
21
MHz
pF
Cob
SWITCHING CHARACTERISTICS (TABLE 1)
Delay Time
Rise Time
Storage Time
Fall Time
td
tr
0.05 0.1 μs
V
CC=125V, IC=1A,
0.5
2
1
4
μs
μs
IB1=IB2=0.2A, tP=25μs,
Duty Cycle≤1%
ts
tf
0.4 0.7 μs
INDUCTIVE LOAD, CLAMPED (TABLE 1, FIGURE 7)
Storage Time
Crossover Time
Fall Time
tsv
tc
1.7
0.29 0.75 μs
0.15 μs
4
μs
IC=1A,Vclamp=300V,
IB1=0.2A,VBE(off)=5V,TC=100°C
tfi
CLASSIFICATION OF hFE1
RANK
A
B
C
D
E
F
RANGE
8 ~ 16
15 ~ 21
20 ~ 26
25 ~ 31
30 ~ 36
35 ~ 40
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
APPLICATION INFORMATION
Table 1.Test Conditions for Dynamic Performance
Resistive
Switching
Reverse Bias Safe Operating Area and Inductive Switching
+5V
VCC
33
1N4933
MJE210
L
MR826*
+125V
0.001µF
33
1N4933
pw
5V
Rc
Vclamp
IC
2N2222
RB
TUT
SCOPE
1K
RB
DUTY CYCLE? 10%
t,tf? 10ns
68
*SELECTED FOR? 1KV
VCE
r
1K
+5V
IB
5.1K
51
D1
-4.0V
1N4933
270
1K
T.U.T.
2N2905
47
MJE200
-VBE(off)
0.02µF
NOTE
100
1/2W
PWand Vcc Adjusted for Desired Ic
RB Adjusted for Desired IB1
Coil Data :
CC=20V
Ferroxcube core #6656
Vclamp=300V
GAP for 30 mH/2 A
Lcoil=50mH
VCC=125V
V
RC=125Ω
D1=1N5820 or
Equiv.
Full Bobbin ( ~ 200 Turns) #20
RB=47Ω
Output Waveforms
OUTPUT WAVEFORMS
+10.3V
0
25μS
tf CLAMPED
IC
IC(pk)
t1 Adjusted to
Obtain Ic
t
t1
tf
-8.5V
Test Equipment
Scope-Tektronics
475 or Equivalent
Lcoil(Icpk)
Vcc
tr,tf<10ns
Duty Cycly=1.0%
RB and Rc adjusted
for desired IB and Ic
t1=
VCE
VCE or
Lcoil(Icpk)
Vclamp
Vclamp
t2=
t
TIME
t2
Table 2. Typical Inductive Switching Performance
IC
TC
TSV
TRV
TFI
TTI
TC
(AMP)
(°C)
(μs)
(μs)
(μs)
(μs)
(μs)
25
100
1.3
1.6
0.23
0.26
0.30
0.30
0.35
0.40
0.30
0.36
0.5
1
25
100
1.5
1.7
0.10
0.13
0.14
0.26
0.05
0.06
0.16
0.29
25
100
1.8
3
0.07
0.08
0.10
0.22
0.05
0.08
0.16
0.28
1.5
Note: All Data Recorded in the inductive Switching Circuit Table 1
Fig 1. Inductive Switching Measurements
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage
waveforms since they are in phase, However, for inductive loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements
must be made on each wave form to determine the total switching time, For this reason, the following new terms have
been defined.
t
t
SV=Voltage Storage Time, 90% IB1 to 10% Vclamp
RV=Voltage Rise Time, 10-90% Vclamp
tFI=Current Fall Time, 90-10% IC
tTI=Current Tail, 10-2% IC
tC=Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the inductive switching waveforms is shown in Figure 1 to aid in the visual identity of
these terms.
For the designer, there is minimal switching loss during storage time and the predominant switching power losses
occur during the crossover interval and can be obtained using the standard equation from AN-222:
PSWT=1/2 VccIc (tc)f
In general, trv + tfi≒tc. However, at lower test currents this relationship may not be valid.
As is common with most switching transistor, resistive switching is specified at 25°C and has become a
benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications
which make this a “SWITCHMODE” transistor are the inductive switching speeds (tc and tsv) which are guaranteed at
100°C.
RESISTIVE SWITCHING PERFORMANCE
Collector Current, IC (A)
Collector Current, IC (A)
10
7
2
Vcc=125V
Ic/IB=5
TJ=25°C
tS
Vcc=125V
Ic/IB=5
5
1
0.7
tR
3
2
TJ=25°C
0.5
0.3
0.2
1
0.7
td @ VBE(off)=5V
0.5
0.1
0.07
0.3
0.2
tR
0.05
0.03
0.02
0.1
0.02
1
0
0.02
20
0.05 0.07 0.1
0.2 0.3
0.5
0.05 0.07 0.1
0.2 0.3
0.5
2
0.7
1
0.03
0.7
0.03
Fig 2. Turn-On Time
Fig 3. Turn-Off Time
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SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of a transistor: average junction temperature and second
break-down. Safe operating area curves indicate Ic – VCE limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 5 is based on Tc=25°C; TJ(pk) is variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated when Tc≧25°C. Second breakdown limitations do not
derate the same as thermal limitations. Allowable current at the voltages shown on Figure 5 may be found at any case
tem-perature by using the appropriate curve on Figure 7.
TJ(pk) may be calculated from the data in Figure 5. At high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn–off, in most cases,
with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe
level at or below a specific value of collector current. This can be accomplished by several means such as active
clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe
Operating Area and represents the voltage–current conditions during re-verse biased turn–off. This rating is verified
under clamped conditions so that the device is never subjected to an ava-lanche mode. Figure 6 gives RBSOA
characteristics.
VCEV,COLLECTOR-EMITTER LAMP VOLTAGE(VOLTS)
VCE,COLLECTOR-EMITTERVOLTAGE (VOLTS)
10
1.6
5
2
10µS
100µS
1.2
1
5.0ms
VBE(off)=9V
1.0ms
dc
0.5
Tj? 100?
IB1=1A
0.8
Tc=25?
0.2
0.1
THERMAL LIMIT (SINGLE PULSE)
BONDING WIRE LIMIT
SECOND BREAKDOWN LIMIT
5V
0.4
0.05
CURVES APPLY BELOW RATED VCEO
3V
0.02
0.01
1.5V
400
0
30
0
0
800
200
500
100
600
700
100
500
5
10
20
50
200 300
Fig 6. Reverse Bias Safe Operating Area
Fig 5. Active Region Safe Operating Area
IC, CASE TEMPERATURE (? )
1
SECOND BREAKDOWN
DERATING
0.8
0.
6
THERMAL
DERATING
0.4
0.2
0
20
160
40
60
80
100
120
140
Fig 7. Forward Bias Power Derating
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
TYPICAL CHARACTERISTICS
IB, BASE CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
80
60
40
30
2
Tj=25?
Tj=150?
25?
1.6
1.2
1.5A
1A
0.5A
Ic=0.1A 0.3A
20
0.8
-55?
10
8
0.4
0
VCE=2V
- - - - - -VCE=5V
6
4
0.02
0.02
1
2
0.01 0.02
0.05 0.1 0.2
0.5
0.05
2
0.03
0.07 0.1
0.2 0.3 0.5 0.7
1
0.05
DC Current Gain
Collector Saturation Region
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
1.4
0.35
0.3
VBE(sat)@IC/IB=3
- - - - - - VBE(on)@VCE=2V
1.2
1
0.25
0.2
IC/IB=3
Tj=-55°C
Tj=-55°C
25°C
25°C
0.15
0.1
0.8
25°C
0.6
0.4
0.05
150°C
150°C
0
0.02
2
0.05 0.07 0.1
0.2 0.3
0.5
0.7 1
0.02
2
0.03
0.07 0.1
0.2 0.3 0.5
0.7 1
0.05
0.03
Collector-Emitter Saturation Region
Base-Emitter Voltage
VBE,BASE-EMITTER VOLTAGE (VOLTS)
VR,REVERSE VOLTAGE (VOLTS)
Cib
4
10
500
300
200
VCE=250V
3
10
Tj=150°C
2
10
125°C
100
70
100°C
50
1
10
75°C
50°C
30
20
0
10
Cob
10
25°C
7
5
0.1
REVERSE
-0.2
-1
FORWARD
+0.2
10
+0.
6
-0.4
0
+0.4
200
50
100
500 1000
0.5 1
2
5
10 20
0.2
Capacitance
Collector Cutoff Region
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
UNISONIC TECHNOLOGIES CO., LTD
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MJE13002
NPN EPITAXIAL SILICON TRANSISTOR
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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