S3515L-S14-R [UTC]
PC POWER SUPPLY SUPERVISORS; PC电源监控
| 型号： | S3515L-S14-R |
| 厂家： | 
Unisonic Technologies |
| 描述： | PC POWER SUPPLY SUPERVISORS |
| 文件： | 总8页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
S3515
CMOS IC
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC S3515 is specially designed for switching power supply
system. It provides over-voltage protection, over-current protection,
under-voltage protection, on/off control and power good signal generating.
OVP/UVP (Over/Under-Voltage Protection) monitors 3.3V, 5V and
double 12V to protect our power supply and PC, FPO goes to high when
one of these supply voltages exceeds their normal operation voltage
range.
DIP-14
OCP (Over Current Protection) monitors IS33, IS5, IS12 input
current. The voltage difference across external current shunt is used for
OCP functions. An external resistor which is connected between the RI
pin and the GND pin can be used to adjust protection threshold. To
achieve better immunity for lighting surge glitch and to prevent
accidental power shut down during dynamic loading condition, the
de-bounce time for UVP/OCP is 73us respectively. The deglitch time for
OVP is 73uS for better noise immunity.
SOP-14
The power supply is turned on after 38mS de-bounce time when
PSON signal is set from high to low. To turn off power supply, PSON
signal is set from low to high and the de-bounce time is 115mS. When
PGI input voltage level is lower than the internal 1.15V reference
voltage, after 73uS de-bounce time, the PGO signal is pulled low.
FEATURES
* Over/Under-Voltage Protection for 3.3V, 5V, and Two 12V
* Over-Current Protection for 3.3V, 5V, and Two 12V
* PGO and FPO pins with Open Drain Output Stage
* 300mS Power Good Delay from PGI to PGO
* 75mS Delay for 3.3V, 5V and 12V Power Turn on
* 2.8mS Delay for PSON Control to FPO Turn off
* 38mS / 115mS PSON on/off De-Bounce Time
* 73uS width Noise Deglitches
* 73uS De-Bounce Time for UVP and OCP
* Wide Supply Voltage Range
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free Plating
S3515L-D14-T
S3515L-S14-R
S3515L-S14-T
Halogen Free
S3515G-D14-T
S3515G-S14-R
S3515G-S14-T
DIP-14
SOP-14
SOP-14
Tube
Tape Reel
Tube
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S3515
CMOS IC
PIN CONFIGURATION
PGI
PGO
VDD
14
13
12
11
10
9
1
2
3
4
5
6
7
GND
FPO
VS5
VS33
VS12
IS33
IS5
PSON
IS12
RI
VS12B
8
PIN DESCRIPTION
PIN NO
PIN NAME
PGI
TYPE
input
DESCRIPTION
1
3
Power good input.
FPO
output
Fault protection output, open drain output stage.
Power on/off control signal sends from CPU or main-board. The power
supply will be turned on/off after 38mS/115mS respectively.
5V over current protection.
4
PSON
input
8
9
IS5
input
input
IS33
3.3V over current protection.
12V over current protection. Regarding typical application, this pin is
connected to the positive end of a current shunt through one resistor.
When the voltage on IS12 is higher than that of VS12 by 5mV, OCP
will be enabled. One current sink, 8 x IREF, is used to determine the
voltage drop between the positive end of the current shunt and VS12.
Adjusting the value of the external resistor can adjust the threshold for
OCP accordingly. The operation for IS5 or IS33 is the same.
Current sense setting. An external resistor Ri is connected between RI
pin and GND pin will adjust a reference current, IREF = 1.15/Ri, for OCP
function.
5
6
IS12
input
RI
input
12
7
VS5
VS12B
VS12
VS33
VDD
input
input
input
input
power
5V over/under-voltage protection.
Second 12V over/under-voltage protection.
10
11
13
12V over/under-voltage protection.
3.3V over/under-voltage protection.
Supply voltage. 4V ~ 15V.
Power good logic output, open drain output stage. The power good
delay is 300mS from PGI to PGO.
14
2
PGO
GND
output
power
Ground.
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S3515
CMOS IC
BLOCK DIAGRAM
Power On Reset
2.4ms
PWR
PWR
38ms /115ms
debounce
PSON
Clr
delay
Bandgap
Reference
RST
75ms
delay
VREF=1.15V
Clr
-
UN
+
VS
33
-
OV
+
-
UN
+
VS 5
-
OV
+
-
UN
+
VS12A
-
OV
+
RST
73µs
-
FPO
PGO
UN
+
R
VS12B
S Q
-
debounce
OV
+
RST
300ms
V
REF
-
73µs
debounce
clr
UN
delay
PGI
+
V12A
-
+
IS33
IREF×8
V12A
-
VREF=1.15 V
+
-
IS5
IREF=VREF/R
+
I
IREF×8
RI
V12A
-
IS12
+
V12A
-
+
IREF×8
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S3515
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
DC Supply Voltage
SYMBOL
VDD
RATINGS
-0.3 ~ 16
-0.3 ~ 8
UNIT
V
Input Voltage (PSON, VS33, VS5, PGI)
VIN
V
-0.3 ~ 16
-0.3 ~ 8
Output Voltage (FPO)
VOUT
V
Power Dissipation (PGO)
Operating Temperature
Storage Temperature
PD
400
mW
°C
TOPR
TSTG
-40 ~ +85
-55 ~ +150
°C
Note 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. Stresses above those listed may cause permanent damage to the device.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD
RATINGS
UNIT
V
DC Supply Voltage
4 ~ 15
Input Voltage (PSON, VS33, VS5, IS33, IS5, PGI)
7
VIN
V
V
Input Voltage (VS12,VS12B, IS12
)
15
FPO
PGO
FPO
PGO
15
Output Voltage
VOUT
7
20
Output Sink Current
IO(SINK)
mA
10
1
Supply Voltage Rising Time (Note)
Output Current RI
tR
mS
µA
IRI
12.5 ~ 62.5
Note VDD rising and falling slew rate must be less than 14V/mS.
ELECTRICAL CHARACTERISTICS (VDD=12V, TA=25°C)
PARAMETER
SYMBOL TEST CONDITIONS
VPGI
VUVp
MIN
TYP
MAX UNIT
UNDER-VOLTAGE AND PGI, PGO
Input Threshold Voltage PGI
Under-voltage protect VS33
1.1
2.6
4.0
9.4
1.15
2.8
4.2
9.9
1.2
3.0
4.4
10.4
0.7
5
V
V
Under-voltage protect VS5
Under-voltage protect VS12, VS12B
Low Level Output Voltage (PGO)
Leakage Current (PGO)
VOL
VDD = 12V ISINK =10mA
PGO = 5V
V
ILEAK
μA
mS
mS
μS
μS
Under-voltage Enable Delay Time
49
75
300
250
73
114
450
350
Timing PG Delay
PGI to PGO
PGI to PGO
tPG
200
150
Noise Deglitch Time
Timing UVP to Protection (FPO)
TUVP
VS33,VS5, VS12,VS12B
OVER-VOLTAGE AND OVER-CURRENT PROTECTION
Over-Voltage Protection
Over-Voltage Protection
Over-Voltage Protection
VS33
3.7
5.7
3.9
6.1
4.1
6.5
VOVP
V
VS5
VS12, VS12B
13.2
13.8
14.4
Ratio of Current Sense Sink Current to Current
Sense Setting Pin (RI) Source Current
Current Source Reference Voltage
OCP Comparator Input Offset Voltage
Low Level Output Voltage (FPO)
Leakage Current (FPO)
RI = 30 ΚΩ,
0.1% Resistor
IREF
7.6
8
8.4
VREF
VI(OFF)
VOL
1.1
-5
1.15
1.2
5
V
mV
V
ISINK =20mA
V(FPO) = 5V
0.7
5
ILEAK
TOVP
TOCP
µA
μS
μS
Timing OVP to Protection
73
73
Timing OCP to Protection
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S3515
CMOS IC
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
1.9
TYP
MAX
UNIT
PSON CONTROL
High-Level Input Voltage
Low-Level Input Voltage
Timing PGO Low to FPO High
VIH
VIL
V
0.98
4.0
57
V
TPSOFF
1.6
24
24
2.8
38
mS
mS
mS
μA
ON
Timing PSON to On/Off
TPSON
OFF
38
57
Input Pull-up Current
TOTAL DEVICE
IPSON PSON = 0V
120
Supply Current
IDD
PSON = 5V, VDD = 5V
1.0
1.8
4.0
mA
V
VDD Start Threshold Voltage
VTHD
VMIN
VDD Min. Operation Voltage After Start-up
3.65
V
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S3515
CMOS IC
TYPICAL APPLICATION CIRCUIT
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S3515
CMOS IC
TIMING DIAGRAM
PSON On/Off and 3.3V, 5V,12V OVP Function
VDD
PSON
TPSON(OFF)
TPSON(ON)
FPO
TOVP
PGI
TPSOFF
TPG
PGO
3.3V,5V,12V
3.3V,5 V,12V OVP UVP and OCP Function
VDD
PSON
FPO
PGI
TOVP
TUVP
PGO
12V
OCP
TOCP
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S3515
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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