UC2843B [UTC]
HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS; 高性能的电流模式PWM控制器
| 型号： | UC2843B |
| 厂家： | 
Unisonic Technologies |
| 描述： | HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS |
| 文件： | 总9页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
HIGH-PERFORMANCE
CURRENT-MODE PWM
CONTROLLERS
DESCRIPTION
The UTC UC2843B provides off-line or DC-DC fixed-frequency
current-mode control design with minimum external components.
Internally-implemented circuits include an under-voltage lockout
(UVLO) and a precision reference with accuracy at the error amplifier
input. The UTC UC2843B also contain internal circuits which include
a pulse width modulation (PWM) comparator providing current-limit
control, logic ensuring latched operation, and a totem-pole output
stage designed to source or sink high-peak current. The output
stage is low when it is in off-state condition and suitable for
N-channel MOSFETs driving.
The UTC UC2843B also has following advantages: the start-up
current lower than 0.5mA while the oscillator discharge current is
specified to 8.3mA (Typ.). In UVLO conditions, the output has a
maximum saturation voltage of 1.2V when sinking 10mA@VCC = 5V.
The typical UVLO threshold of the UTC UC2843B is 8.4V (on)
and 7.6V (off) and can operate to duty cycles approximately 100%.
FEATURES
*
*
*
*
*
*
*
*
*
Current mode operation:500 kHz
Low start-up current value<0.5mA
Latching PWM for cycle-by-cycle current limiting
Trimmed oscillator discharge current
Automatic feed-forward compensation
Internally trimmed reference with UVLO
High-current totem-pole output UVLO with hysteresis
Double-pulse suppression
Halogen free
ORDERING INFORMATION
Ordering Number
UC2843BG-S08-R
Package
SOP-8
Packing
Tape Reel
www.unisonic.com.tw
Copyright © 2009 Unisonic Technologies Co., Ltd
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
COMP 1
VREF
8
7 VCC
VFB
ISENSE
RT/CT
2
3
4
OUTPUT
6
5
GND
PIN DESCRIPTION
PIN NO.
PIN NAME
COMP
DESCRIPTION
1
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the
switching power supply output through a resistor divider.
2
VFB
A voltage proportional to inductor current is connected to this input. The PWM uses
this information to terminate the output switch conduction.
The Oscillator frequency and maximum Output duty cycle are programmed by
connecting resistor RT to VREF and capacitor CT to ground. Operation to 500 kHz is
possible.
3
4
ISENSE
RT/CT
5
6
7
8
GND
OUTPUT
VCC
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A
are sourced and sunk by this pin.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through
resistor RT.
VREF
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING(Ta=25°C, unless otherwise specified)
PARAMETER
Supply Voltage (Low impedance source)
SYMBOL
VCC
RATINGS
30
UNIT
V
Analog Input Voltage (VFB and ISENSE
Supply Current
)
VIN
-0.3~+6.3
30
V
ICC
mA
A
Output Current
IOUT
IO(SINK)
PD
±1
10
Error Amplifier Output Sink Current
Power Dissipation
mA
mW
μJ
702
Output Energy (Capacitive load)
Junction Temperature
W
5
TJ
150
°C
°C
°C
Operating Temperature
Storage Temperature
TOPR
TSTG
-40~+85
-65~+150
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. All voltages are concerning the device GND terminal.
THERMAL DATA
PARAMETER
Junction to Ambient
SYMBOL
MIN
TYP
TYP
MAX
178
UNIT
°C/W
θJA
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VCC
MIN
MAX
30
UNIT
V
Supply Voltage
RT/CT
VFB and ISENSE
0
0
0
5.5
5.5
30
V
Input Voltage
VIN
V
Output Voltage (OUTPUT)
VOUT
ICC
V
Supply Current, Externally Limited
Output Current
25
mA
mA
mA
kHz
°C
IOUT
IO(REF)
fOSC
Ta
200
-20
500
+85
Reference Output Current
Oscillator Frequency
100
Operating Temperature
-40
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
(VCC = 15 V, RT = 10kΩ, CT = 3.3nF, TJ=25°C, unless otherwise specified)
PARAMETER
REFERENCE SECTION
Reference Output Voltage
Line Regulation
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
VREF
IOUT =1mA, TJ =25°C
4.95
5
6
6
5.05
20
V
ΔVOUT
ΔVOUT
VCC = 12V~25V
mV
mV
Load Regulation
IOUT = 1mA~20mA
25
Average Temperature Coefficient Of
Output Voltage
TS
0.2
0.4 mV/°C
Total Output Variation
Output Noise Voltage
Long Term Stability
VREF
eN
VCC =12V~25V, IOUT =1mA~20mA 4.9
f = 10Hz~10kHz, TJ =25°C
TJ=25°C FOR 1000 hours
-30
5.1
V
50
5
μV
mV
mA
25
Output Short Circuit Current
OSCILLATOR SECTION
ISC
-100 -180
TJ =25°C,
RT =62kΩ, CT =1nF,
Min =225 kHz, Max =275 kHz
TJ = Full range
49
48
52
55
kHz
Frequency
fOSC
56
1
kHz
%
ΔfOSC
ΔV
Frequency Change with Voltage
VCC = 12V ~ 25V
TJ = Full range
0.2
5
ΔfOSC
ΔT
Frequency Change with
Temperature
%
Oscillator Voltage Swing
VOSC
Peak to peak
1.7
8.3
V
TJ =25°C, RT/CT =2V
RT/CT =2V
7.8
7.5
8.8
8.8
mA
mA
Discharge Current
IDISC
ERROR-AMPLIFIER SECTION
Voltage Feedback Input
Input Bias Current
VFB
II(BIAS)
GVO
COMP =2.5V
VOUT =2V~4V
2.45
2.5
-0.3
90
1
2.55
-1
V
μA
dB
MHz
dB
mA
mA
V
Open Loop Voltage Gain
Unity Gain Bandwidth
65
0.7
60
2
GBW
Power Supply Rejection Ratio
Output Sink Current
PSRR
ISINK
VCC =12V~25V
70
6
VFB =2.7V, COMP=1.1V
VFB =2.3V, COMP =5V
VFB =2.3V, RL =15kΩ to GND
VFB =2.7V, RL =15kΩ to GND
Output Source Current
ISOURCE
VOH
-0.5
5
-0.8
6
Output Voltage Swing High State
VOL
0.7
1.1
V
CURRENT-SENSE SECTION
Current Sense Input Voltage Gain
Maximum Current Sense Input
Threshold
GV
(Note 2,3)
2.85
0.9
3
1
3.15
1.1
V/V
V
VTH
COMP =5V (Note 2)
VCC =12V~25V (Note 2)
Power Supply Rejection Ratio
Input Bias Current
PSRR
II(BIAS)
tD
70
-2
dB
μA
ns
-10
Propagation Delay
VFB =0V~2V
150
300
OUTPUT SECTION
IOH =-20mA
IOH =-200mA
IOL =20mA
13
12
13.5
13.5
0.1
V
V
V
V
High-Level Output Voltage
Low-Level Output Voltage
VOH
VOL
0.4
2.2
IOL =200mA
1.5
Under-Voltage Lockout
Output Voltage
VUVLO
VCC =5V, IOL=1mA
0.7
1.2
V
Output Voltage Rise Time
Output Voltage Fall Time
tR
tF
CL =1nF, TJ = 25°C
CL =1nF, TJ = 25°C
50
50
150
150
ns
ns
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
UNDERVOLTAGE-LOCKOUT SECTION
Startup Threshold
VTH
7.8
7
8.4
7.6
9
V
V
Minimum Operating Voltage
After Start-Up
VCC(MIN)
8.2
PULSE-WIDTH MODULATOR SECTION
Maximum Duty Cycle
DC(MAX)
DC(MIN)
94
96
100
0
%
%
Minimum Duty Cycle
SUPPLY VOLTAGE
Power Startup Supply Current
Power Operating Supply Current
Power Supply Zener Voltage
ICC+IC
ICC+IC
VZ
0.3
11
34
0.5
17
mA
mA
V
VFB and ISENSE at 0V
ICC =25mA
30
Notes: 1. Adjust VCC above the start threshold before setting it to 15V.
2. Measured at the trip point of the latch, with VFB at 0V.
3. Measured between ISENSE and COMP, with the input changing from 0V ~ 0.8V.
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION
Error amplifier (EA) configuration circuit:
0.5mA
2.5V
EA
VFB
COMP
Error
Amplifier
Z1
Z2
Note: Error amplifier can source or sink up to 0.5mA.
Current-sense circuit:
Notes: 1. Peak current (IS) is determined by the formula: IS(max) = 1 V/RS
2. A small RC filter formed by resistor Rf and capacitor Cf may be required to suppress switch transients.
The oscillator frequency is set using the circuit:
VREF
RT
RT/CT
CT
GND
The frequency is calculated as followed:
f = 1 / RTCT
For RT > 5kΩ:
f = 1.72 / RTCT
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Open-Loop Laboratory Test Fixture
In the open-loop laboratory test fixture, high peak currents and loads need grounding techniques. The transistor
and 5-kΩ potentiometer sample the oscillator waveform, applying an adjustable ramp to the ISENSE terminal. Timing
and bypass capacitors should be connected closely to the GND terminal in a single-point ground.
Shutdown Technique
The PWM controller can be shut down through two methods: the one is raising voltage (above 1 V) at ISENSE, the
other is pulling the COMP terminal below a voltage two diode drops above ground. Either method can leave the
output of the PWM comparator high (refer to block diagram). To reset the PWM latch is dominant so the output can
stay low in the case of the next clock cycle is coming and the COMP or ISENSE terminal is removed beyond this
shutdown condition. For example, an externally-latched shutdown can be accomplished by adding an SCR reset by
cycling VCC below the lower UVLO threshold. So the reference turns off then allows the SCR to reset at this
condition.
1kΩ
VREF
COMP
Shutdown
330Ω
ISENSE
500Ω
To Current-Sense
Resistor
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UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Shutdown Technique (cont.)
A fraction of the triangular-wave oscillator can be summed resistively with the current-sense signal providing
slope compensation for converters, which requiring duty cycles over 50%. Please note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
VREF
0.1µF
RT
RT/CT
CT
R1
ISENSE
R2
ISENSE
C
RSENSE
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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