UTC571_技术文档

UTC571

LINEAR INTEGRATED CIRCUIT

COMPANDER

DESCRIPTION

The UTC571 is a versatile low cost dual gain control

circuit in which either channel may be used as a dynamic

range compressor or expandor. Each channel has a full-

wave rectifier to detect the average value of the signal, a

linerarized temperature-compensated variable gain cell,

and an operational amplifier.

The UTC571 is well suited for use in cellular radio and

radio communications systems, modems, telephone, and

satellite broadcast/receive audio systems.

FEATURES

DIP-16

• Complete compressor and expandor in one IChip

•Temperature compensated

ꢀ

APPLICATIONS

•Greater than 110dB dynamic range

• Operates down to 6VDC

•

ꢀ

• System levels adjustable with external components

• Distortion may be trimmed out

• Dynamic noise reduction systems

• Voltage-controlled amplifier

ꢀ

•

ꢀ

PIN CONFIGURATION

RECT CAP 1

RECT IN 1

1

2

3

4

5

6

7

8

16 RECT CAP 2

15

RECT IN 2

AG CELL IN 1

AG CELL IN 2

14

VCC

GND

13

INV.IN 1

12 INV.IN 2

RES.R

3

1

RES.R 3 2

11

10

9

OUTPUT 1

OUTPUT 2

THD TRIM 1

THD TRIM 2

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UTC571

LINEAR INTEGRATED CIRCUIT

BLOCK DIAGRAM

THD TRIM

R3 INVERTER IN

R3 20K

R2 20K

R1 10K

VARIABLE

GAIN

G IN

OUTPUT

VREF

1.8V

R4 20K

RECTIFIER

RECT CAP

RECT IN

ꢀ

ABSOLUTE MAXIMUM RATINGS

(Ta=25°C )

Characteristic

Maximum Operating Voltage

Operating Temperature

Power dissipation

Symbol

Value

18

Unit

V

V_CC

T_A

0~70

400

°C

P_D

mW

AC ELECTRICAL CHARACTERISTICS

(Ta=25°C, Vcc=+6V,unless otherwise stated)

Characteristic

Supply Voltage

Symbol

V_CC

Test Condition

Min

Typ.

Max

18

Unit

6

v

Supply Current

I_CC

No signal

3.2

4.8

mA

V/µs

Output Current capability

Output Slew Rate

I_OUT

SR

±20

±.5

0.5

0.1

±5

Untrimmed

Trimmed

Gsin Cell Distortion

2.0

%

Resister Tolerance

±15

2.0

%

V

Internal Reference Voltage

Output DC Shift

1.7

1.85

±30

20

Untrimmed

±150

60

mV

µV

Expandor Output Noise

Unity Gain Level

No signal, 15Hz-20kHz

1kHz

-1.5

0

+1.5

dBm

dB

Gain Change

±0.1

Reference Drift

+2,-25 +20,-50 mV

Resistor Drift

+8,-0

%

Tracking Error(measured relative

to value at unity gain) Equals [VO-

VO(unity gain)]dB-V2dBm

Rectifier input,

V2=+6dBm,V1=0dB

V2=-30dBm, V1=0dB

+0.2

-1,+1.5

dB

Channel Separation

60

Note: 1. Input to V 1 and V 2 grounded.

2. Measured at 0dBm, 1kHz.

3. Expandor AC input change from no signal to 0dBm.

4. Relative to value at T A = 2ꢀꢀC.

5. Electrical characteristics for the UTC571 only are specified over -40 to +8 °C temperature range.

6. 0dBm = 775mV RMS .

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UTC571

LINEAR INTEGRATED CIRCUIT

FUNCTION DESCRIPTION

CIRCUIT DESCRIPTION

The UTC571 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable

gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a

circuit which can perform well with few external components, yet can be adapted to many diverse applications.

The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing

node which is biased at V REF . The rectified current is averaged on an external filter capacitor tied to the CRECT

terminal, and the average value of the input current controls the gain of the variable gain cell. The gain will thus

be proportional to the average value of the input signal for capacitively-coupled voltage inputs as shown in the

following equation. Note that for capacitively-coupled inputs there is no offset voltage capable of producing a

gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than

0.1µA.

| VIN − VREF | avg

G

or

R1

| VIN | avg

R1

The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter

capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on

the gain control signal will modulate the signal passing through the variable gain cell. In an expander or

compressor application, this would lead to third harmonic distortion, so there is a trade-off to be made between

fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown

by this equation.

G(t)=(Ginitial-Gfinal)e-t/τ+Gfinal; τ=10k × CRECT

The variable gain cell is a current-in, current-out device with the ratio IOUT /IIN controlled by the rectifier. IIN is

the current which flows from the DG input to an internal summing node biased at VREF . The following equation

applies for capacitively-coupled inputs. The output current, IOUT , is fed to the summing node of the op amp.

VIN − VREF

VIN

R2

IIN =

=

R2

A compensation scheme built into the DG cell compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset

voltages. The THD trim terminal provides a means for nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally compensated) has the non-inverting input tied to V REF , and the

inverting input connected to the DG cell output as well as brought out externally. A resistor, R 3 , is brought out

from the summing node and allows compressor or expander gain to be determined only by internal components.

The output stage is capable of ±20mA output current. This allows a +13dBm (3.5V RMS ) output into a 300W

load which, with a series resistor and proper transformer, can result in +13dBm with a 600Ω output impedance.

A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the

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UTC571

LINEAR INTEGRATED CIRCUIT

rectifier and DG cell, and a bias current for the DG cell. The low tempco of this type of reference provides very

stable biasing over a wide temperature range.

The typical performance characteristics illustration shows the basic input-output transfer curve for basic

compressor or expander circuits.

+20

+10

0

-10

-20

-30

-40

-50

-60

-70

-80

-40 -30 -20 -10

0

+10

COMPRESSOR OUTPUT LEVEL OR

EXPANDOR INPUT LEVEL(dBm)

Basic Input-Output Transfer Curve

TYPICAL TEST CIRCUIT

Vcc=15V

0.1

F

10F

6.11

20k

2.2

F

20k

V1

V2

G

V0

3.14

7.10

VREF

2.2

F

10k

30k

2.15

4

1.16

2.2

5.12

8.2k

8.9

200pF

F

Typical Test Circuit

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LINEAR INTEGRATED CIRCUIT

INTRODUCTION

Much interest has been expressed in high performance electronic gain control circuits. For non-critical

applications, an integrated circuit operational transconductance amplifier can be used, but when high-performance

is required, one has to resort to complex discrete circuitry with many expensive, well-matched components.

This paper describes an inexpensive integrated circuit, the UTC571 Compandor, which offers a pair of high

performance gain control circuits featuring low distortion (<0.1%), high signal-to-noise ratio (90dB), and wide

dynamic range (110dB).

CIRCUIT BACKGROUND

The UTC571 Compandor was originally designed to satisfy the requirements of the telephone system. When

several telephone channels are multiplexed onto a common line, the resulting signal-to-noise ratio is poor and

companding is used to allow a wider dynamic range to be passed through the channel. Figure 1 graphically shows

what a compandor can do for the signal-to-noise ratio of a restricted dynamic range channel. The input level range

of +20 to -80dB is shown undergoing a 2-to-1 compression where a 2dB input level change is compressed into a

1dB output level change by the compressor. The original 100dB of dynamic range is thus compressed to a 50dB

range for transmission through a restricted dynamic range channel. A complementary expansion on the receiving

end restores the original signal levels and reduces the channel noise by as much as 45dB.

INPUT

LEVEL

+20

OUTPUT

LEVEL

+20

0d

B

0dB

-40

-80

-40

-80

NOISE

Figure 1. Restricted Dynamic Range Channel

The significant circuits in a compressor or expander are the rectifier and the gain control element. The phone

system requires a simple full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines

the (input) output level tracking accuracy. The gain cell determines the distortion and noise characteristics, and the

phone system specifications here are very loose. These specs could have been met with a simple operational

transconductance multiplier, or OTA, but the gain of an OTA is proportional to temperature and this is very

undesirable. Therefore, a linearized Tran conductance multiplier was designed which is insensitive to temperature

and offers low noise and low distortion performance. These features make the circuit useful in audio and data

systems as well as in telecommunications systems.

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LINEAR INTEGRATED CIRCUIT

BASIC CIRCUIT HOOK-UP AND OPERATION

THD TRIM

R3

INVIN

5.12

8.9

6.11

R3

20K

R2

20K

G

IN

G

VREE

1.8V

3.14

OUTPUT

7.10

R4

30K

IG

R1

10K

VCC PIN 13

RECTIN

GND PIN 4

2.15

1.16

CRECT

Figure 2. Chip Block Diagram

Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-

wave averaging rectifier provides a gain control current, IG , for the variable gain (∆G) cell. The output of the DG

cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V

reference denoted VREF . The non-inverting input of the op amp is tied to VREF , and the summing nodes of the

rectifier and ∆G cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the VREF

potential.

R3

CIN1

R2

G

V

OUT

VIN

R4

V

REF

C

IN2

R1

2R3VIN (avg)

R1R2IB

NOTE: GAIN=

C

RECT

I

B

=140A

Figure 3. Basic Expander

Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, VIN is applied to the inputs

of both the rectifier and the ∆G cell. When the input signal drops by 6dB, the gain control current will drop by a

factor of 2, and so the gain will drop 6dB. The output level at VOUT will thus drop 12dB, giving us the desired 2 to 1

expansion.

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LINEAR INTEGRATED CIRCUIT

R1

20K

G

R1

10K

C

REC

T

CF

R

D

C

RDC

R3

20K

CIN

VIN

V

OUT

R4

30K

V

REF

Figure 4. Basic Components

Figure 4 shows the hook-up for a compressor. This is essentially an expandor placed in the feedback loop of the

op amp . the ∆G cell is setup to provide AC feedback only, so a separate DC feedback loop is provide by the two

RDC and CDC. The values of RDC will determine the DC bias at the output of the amp. The output will bias to:

RDC1 + RDC2

VOUT DC = 1 +

R4

RDCTOT

VREF = (1+

)1.8V

30K

The output of the expander will bias up to:

R3

VOUT DC = 1 +

VREF

R4

20K

VREF = (1 +

)1.8V = 3.0V

30K

The output will bias to 3.0V when the internal resistor are used. External resistor may be placed in series with r3,

(which will affect the gain ), or in parallel with r4 to raise the DC bias to any desired value.

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LINEAR INTEGRATED CIRCUIT

CIRCUIT DETAILS—RECTIFIER

V+

I=VIN/R1

R1

VIN

I

G

RS

10K

C

R

Figure 5. Rectifier Concept

Figure 5 shows the concept behind the full-wave averaging rectifier. The input current to the summing node of

the op amp, V IN R 1 , is supplied by the output of the op amp. If we can mirror the op amp output current into a

unipolar current, we will have an ideal rectifier. The output current is averaged by R5 , CR, which set the averaging

time constant, and then mirrored with a gain of 2 to become IG , the gain control current.

Q3

Q7

Q4

Q5

R1

10K

VIN

Q1 Q2

R

10K

S

D1

Q6

Q9

Q8

I

1

I2

CR

Figure 6. Simplified Rectifier Schematic

Figure 6 shows the rectifier circuit in more detail. The op amp is a one-stage op amp, biased so that only one

output device is on at a time. The non-inverting input, (the base of Q 1 ), which is shown grounded, is actually tied

to the internal 1.8V V REF . The inverting input is tied to the op amp output, (the emitters of Q 5 and Q 6 ), and the

input summing resistor R 1 . The single diode between the bases of Q 5 and Q 6 assures that only one device is on

at a time. To detect the output current of the op amp, we simply use the collector currents of the output devices Q

5 and Q 6 . Q 6 will conduct when the input swings positive and Q 5 conducts when the input swings negative. The

collector currents will be in error by the a of Q 5 or Q 6 on negative or positive signal swings, respectively. ICs such

as this have typical NPN bs of 200 and PNP bs of 40. The a’s of 0.995 and 0.975 will produce errors of 0.5% on

negative swings and 2.5% on positive swings. The 1.5% average of these errors yields a mere 0.13dB gain error.

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LINEAR INTEGRATED CIRCUIT

At very low input signal levels the bias current of Q 2 , (typically 50nA), will become significant as it must be

supplied by Q 5 . Another low level error can be caused by DC coupling into the rectifier. If an offset voltage exists

between the V IN input pin and the base of Q 2 , an error current of V OS /R 1 will be generated. A mere 1mV of

offset will cause an input current of 100nA which will produce twice the error of the input bias current. For highest

accuracy, the rectifier should be coupled into capacitively. At high input levels the β of the PNP Q 6 will begin to

suffer, and there will be an increasing error until the circuit saturates. Saturation can be avoided by limiting the

current into the rectifier input to 250mA. If necessary, an external resistor may be placed in series with R 1 to limit

the current to this value. Figure 7 shows the rectifier accuracy vs input level at a frequency of 1kHz.

+1

0

-1

-40

-20

0

RECTIFIER INPUT dBm

Figure 7. Rectifier Accuracy

At very high frequencies, the response of the rectifier will fall off. The roll-off will be more pronounced at lower

input levels due to the increasing amount of gain required to switch between Q 5 or Q 6 conducting. The rectifier

frequency response for input levels of 0dBm, -20dBm, and -40dBm is shown in Figure 8. The response at all three

levels is flat to well above the audio range.

INPUT=0dBm

0

-20dBm

-40dBm

3

10K

1MEG

FREQUENCY(Hz)

Figure 8. Simplified ∆G Cell Schematic

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LINEAR INTEGRATED CIRCUIT

VARIABLE GAIN CELL

V+

I1

140

A

R2

20K

Q1 Q2

I2(=2I1)

Q3 Q4

VIN

IIN

IG

280

A

V-

LG

IGVIN

Note: LOUT =

IIN =

L1

I2R2

Figure 9. Simplified ∆G Cell Schematic

Figure 9 is a diagram of the variable gain cell. This is a linearized two-quadrant transconductance multiplier. Q 1 ,

Q 2 and the op amp provide a predistorted drive signal for the gain control pair, Q 3 and Q 4 . The gain is

controlled by I G and a current mirror provides the output current.

The op amp maintains the base and collector of Q 1 at ground potential (V REF ) by controlling the base of Q 2 .

The input current I IN (=V IN /R 2 ) is thus forced to flow through Q 1 along with the current I 1 , so I C1 =I 1 +I IN .

Since I 2 has been set at twice the value of I 1 , the current through Q 2 is:

I2 - (I1 +IIN ) = I1 - IIN = IC2.

The op amp has thus forced a linear current swing between Q 1 and Q 2 by providing the proper drive to the

base of Q 2 . This drive signal will be linear for small signals, but very non-linear for large signals, since it is

compensating for the non-linearity of the differential pair, Q 1 and Q 2 , under large signal conditions.

The key to the circuit is that same predistorted drive signal is applied to the gain control pair, Q3 and Q4. When

two differential pairs of transistors have the same signal applied, their collector current ratios will be identical

regardless of the magnitude of the currents. This gives us :

IC1

IC2

IC4

IC3

I1 + IIN

I1 − IIN

=

plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3 will yield the multiplier transfer function,

IG

I1

VINIG

R2I1

IOUT =

IIN =

This equation is liner and temperature-insenstive, but it assumes ideal transistor.

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LINEAR INTEGRATED CIRCUIT

4

3

VOS=5mV

4mV

2

3mV

2mV

1

1mV

0.34

-6

0

+6

INPUT LEVEL(dBm)

Figure 10. ∆G Cell Distortion vs Offset Voltage

If the transistors are not perfectly matched, a parabolic, non-linearity is generated, which results in second

harmonic distortion. Figure 10 gives an indication of the magnitude of the distortion caused by a given input level

and offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level.

Saturation of the gain cell occurs at a +8dBm level. At a nominal operating level of 0dBm, a 1mV offset will yield

0.34% of second harmonic distortion. Most circuits are somewhat better than this, which means our overall offsets

are typically about mV. The distortion is not affected by the magnitude of the gain control current, and it does not

increase as the gain is changed. This second harmonic distortion could be eliminated by making perfect transistors,

but since that would be difficult, we have had to resort to other methods. A trim pin has been provided to allow

trimming of the internal offsets to zero, which effectively eliminated second harmonic distortion. Figure 11 shows

the simple trim network required.

VCC

R

3.6V

20K

6.2K

TO THD

TRIM

200PF

Figure 11. THD Trim Network

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LINEAR INTEGRATED CIRCUIT

+20

0

MAXIMUM

SIGNAL LEVEL

-20

-40

-60

-80

-100

90dB

110dB

NOISE IN

20kHz BW

-40

-20

0

VCA GAIN (0dB)

Figure 12. Dynamic Range of UTC571

Figure 12 shows the noise performance of the DG cell. The maximum output level before clipping occurs in the

gain cell is plotted along with the output noise in a 20kHz bandwidth. Note that the noise drops as the gain is

reduced for the first 20dB of gain reduction. At high gains, the signal to noise ratio is 90dB, and the total dynamic

range from maximum signal to minimum noise is 110dB.

Control signal feedthrough is generated in the gain cell by imperfect device matching and mismatches in the

current sources, I 1 and I 2 . When no input signal is present, changing I G will cause a small output signal. The

distortion trim is effective in nulling out any control signal feedthrough, but in general, the null for minimum

feedthrough will be different than the null in distortion. The control signal feedthrough can be trimmed

independently of distortion by tying a current source to the DG input pin. This effectively trims I . Figure 17 shows

such a trim network.

Vcc

R-SELECT FOR

3.6V

470k

100k

TO PIN 3 OR 14

Figure 13. control Signal Feedthrough

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LINEAR INTEGRATED CIRCUIT

OPERATIONAL AMPLIFIER

The main op amp shown in the chip block diagram is equivalent to a 741 with a 1MHz bandwidth. Figure 18

shows the basic circuit. Split collectors are used in the input pair to reduce g M , so that a small compensation

capacitor of just 10pF may be used. The output stage, although capable of output currents in excess of 20mA, is

biased for a low quiescent current to conserve power. When driving heavy loads, this leads to a small amount of

crossover distortion.

I1

I2

Q6

Q7

D1

D2

OUT

Q1

Q2

-IN

+IN

Q5

Q4

Q3

Figure 14. Operational Amplifier

RESISTORS

Inspection of the gain equations in Figures 3 and 4 will show that the basic compressor and expander circuit

gains may be set entirely by resistor ratios and the internal voltage reference. Thus, any form of resistors that

match well would suffice for these simple hook-ups, and absolute accuracy and temperature coefficient would be of

no importance. However, as one starts to modify the gain equation with external resistors, the internal resistor

accuracy and tempco become very significant. Figure 15 shows the effects of temperature on the diffused resistors

which are normally used in integrated circuits, and the ion-implanted resistors which are used in this circuit. Over

the critical 0°C to +70°C temperature range, there is a 10-to-1 improvement in drift from a 5% change for the

diffused resistors, to a 0.5% change for the implemented resistors. The implanted resistors have another

advantage in that they can be made the size of the diffused resistors due to the higher resistivity. This saves a

significant amount of chip area.

1.15

140

¡/

DIFFUSED

RESISTOR

1.10

1.05

1.00

0.95

1k

¡/

LOW TC IMPLANTED

RESISTOR

1% ERROR BAND

-40

0

40

80

120

TEMPERATURE

Figure 15. Resistance vs temperature

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LINEAR INTEGRATED CIRCUIT

PACKAGE OUTLINE

16-DIP-P-300

UNIT: mm

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型号：	UTC571
厂家：	Unisonic Technologies
描述：	COMPANDER Complete compressor and expandor in one IChip COMPANDER完整的压缩机和扩张器于一体的Internet控制
文件：	总14页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UTC571 [UTC]

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