VL-PS-PDA320240D-02 [VARITRONIX]
SPECIFICATION OF LCD MODULE TYPE; 规格液晶显示模组式
| 型号： | VL-PS-PDA320240D-02 |
| 厂家： | 
VARITRONIX INTERNATIONAL LIMITED |
| 描述： | SPECIFICATION OF LCD MODULE TYPE |
| 文件： | 总16页 (文件大小：1280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 2 OF 16
DOCUMENT REVISION HISTORY
DOCUMENT
REVISION
DATE
DESCRIPTION
CHANGED
BY
CHECKED
BY
FROM
TO
A
2005.06.24 First Release.
Based on
ZHANG
YAN FANG
LIU ZHI
QIANG
a.) Test Specification:
VL-TS-PDA320240D-02 REV. A
2005.06.10
b.) VL-QUA-012B, REV. W,
2004.03.20
According to VL-QUA-012B, LCD
size is middle because Unit Per
Laminate=6 which is in the range of
2pcs/Laminate to 6pcs /Laminate.
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 3 OF 16
CONTENTS
Page No.
1.
2.
3.
GENERAL DESCRIPTION
4
4
MECHANICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
7
7
7
3.1. ELECTRICAL MAXIMUM RATINGS – FOR IC ONLY
3.2. ENVIRONMENTAL CONDITIONS
4.
ELECTRICAL SPECIFICATIONS
8
8
4.1. INTERFACE SIGNALS
4.2. TYPICAL ELECTRICAL CHARACTERISTICS
4.3. TIMING SPECIFICATIONS
4.4. PRECAUTION WHEN CONNECTING AND DISCONNECTING THE POWER
9
10
14
5.
6.
REMARK
15
16
LCD COSMETIC CONDITIONS
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 4 OF 16
VARITRONIX LIMITED
Preliminary Specification
of
LCD Module Type
PDA320240D-02
1. General Description
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
320 X 240 dots.
FSTN Positive Black & White Transflective LCD Graphic Module.
Viewing Angle: 6 O’clock direction.
Driving scheme: 1/240 Duty, 1/13 bias.
‘NOVATEK’ NT7701 (TCP form) 160 Output LCD Segment/Common Drivers or equivalent.
‘NOVATEK’ NT7702 (TCP form) 240 Output LCD Segment/Common Drivers or equivalent.
DC/DC Converters.
White LED05 backlight.
FFC connection.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1(a) and summarized in Table 1 below.
Table 1
Parameter
Outline dimensions
Specifications
95.4(W) x 128.88(H) x 7.8 (D)
(Include FFC & backlight terminals, exclude TAB)
79.78(W) x 60.58(H)
76.785(W) x 57.585(H)
320 (H) dots x 240 (V) dots
0.225(W) x 0.225(H)
0.015(W) x 0.015(H)
0.24(W) x 0.24(H)
TBD
Unit
mm
Viewing area
Active area
Display format
Dot size
Dot spacing
Dot pitch
mm
mm
-
mm
mm
mm
gram
Overall Weight
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 5 OF 16
Figure 1(a): Module specification
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 6 OF 16
C1
.
.
.
.
.
.
.
PDA320240D
COM1
.
.
.
240
LCD GRAPHIC DISPLAY
LCD COMMON
DRIVER
COM240
320 X 240 DOTS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EIO2
'NOVATEK' NT7702
(TCP)
C240
S1
S320
LP
FR
DISPOFF
. . . . .
SEG1
SEG160
SEG161. . . . .
SEG320
LCD SEGMENT DRIVER
LCD SEGMENT DRIVER
'NOVATEK' NT7701
(TCP)
'NOVATEK' NT7701
(TCP)
LP
FR DISPOFFD0~3
XCK
DISPOFF
XCK
FR
LP
D0~3
VSS
3
V0,V1,V4
VDD
3
3
V0,V2,V3
DC/DC Conveters and
bias voltage circuit
3
FLM
CL1
CL2
M
D-OFF
DB0~DB3
4
A
K
WHITE LED05 BACKLIGHT
Figure 1(b): Block Diagram of the module.
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 7 OF 16
3. Absolute Maximum Ratings
3.1 Electrical Maximum Ratings – for IC Only
Table 2
Parameter
Supply voltage range (Logic)
Supply voltage (LCD)
Input voltage range
Symbol
VDD - VSS
V0
Min.
-0.3
-0.3
-0.3
Max.
+7.0
+30.0
Unit
V
V
VIN
VDD+0.3
V
Note: 1.) The module may be destroyed if they are used beyond the absolute maximum ratings.
2.) All voltage values are referenced to VSS= 0V.
3.2 Environmental Conditions
Table 3
Operating
Temperature
(Topr)
Storage
Temperature
(Tstg)
Item
Remark
(Note1)
Min.
0°C
Max.
+50°C
Min.
-20°C
Max.
+70°C
Ambient Temperature
(Except Touch Panel)
Humidity
Vibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
Half-sine pulse shape
Dry
No condensation
3 directions
90% max. RH for Ta ≤ 40°C
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration: 11 ms
3 directions
Peak acceleration: 981 m/s2 = 100 g
Number of shocks: 3 shocks in 3
mutually perpendicular axes.
Note 1: Product cannot sustain in extreme storage conditions for a long time.
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 8 OF 16
4. Electrical Specifications
4.1 Interface signals
Table 4: Pin description (LCD Driver)
Pin No.
Symbol
FLM
M
Description
1
2
Input/output for chip select or data of the shift register.
AC signal input for LCD driving waveform
-The input signal is level-shifted from logic voltage level to the LCD
driver voltage level, and it controls the LCD driver circuit
-Normally, inputs a frame inversion signal.
The LCD driver output pin’s output voltage level can be set using the
shift register output signal and the FR signal.
3
4
5
CL1
Latch pulse input/shift clock input for the shift register.
Display data shift clock input for segment mode.
Control input for deselect output level.
CL2
____________
D-OFF
DB0
DB1
DB2
DB3
VDD
VSS
VEE *
VSS
NC
A
K
TP_R
TP_D
TP_L
TP_U
6
7
8
9
Input pin for display data.
10
11
12
13
14
15
16
17
18
19
20
Power supply for logic.
Ground (0V)
Positive power supply for LCD driving voltage. *
Ground (0V)
No connection
Anode of backlight
Cathode of backlight.
RIGHT Input Position
BOTTOM Input Position
LEFT Input Position
TOP Input Position
* This pin should be NC (No Connection) when Built-in DC/DC converter is used
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 9 OF 16
4.2
Typical Electrical Characteristics
At Ta = 25 °C, VDD = 3.0V±5%, VSS = 0V. Ta=25°C
Table 5
Parameter
Symbol
Conditions
VDD=3.0V,
Ta=25°C, Note 1
“High” level,
Note 2
Min.
2.85
16.3
Typ.
3.0
16.5
Max.
3.15
16.7
Unit
V
V
Supply voltage (Logic) VDD-VSS
Supply voltage (LCD) VLCD
(Build-in)
Input signal voltage
VIH
VIL
IDD
0.8 VDD
-
-
-
V
V
“Low” level,
Note 2
-
-
0.2 VDD
30
Supply Current
(Logic & LCD)
Character mode,
VDD = 3.0V.
Ta=25°C, Note (1)
Checker board mode,
VDD = 3.0V.
Ta=25°C, Note (1)
Forward current
=20mA
20
mA
-
30
3.2
100
45
3.4
-
mA
V
Supply voltage of
White LED05
backlight
Luminance (on the
backlight surface)
VLED
3.0
70
cd/m2
Number of LED
chips=1x4=4
Note 1: There is tolerance in optimum LCD driving voltage during production and it will be
within the specified range.
Note 2: Apply to pins DB0~DB3 (or D0~D3), FLM (or EIO2), CL1 (or LP), CL2 (or XCK), DISPOFF
____________
_________________
M (or FR), and D-OFF (or DISPOFF).
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 10 OF 16
4.3
Timing Specifications
Refer to Fig. 2, Segment mode characteristics (NT7701)
At Ta = 0 °C to +50 °C, VDD = 3.0V±5%, VSS = 0V.
Table 6
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 11 OF 16
DB0~3
Figure 2: Timing waveform of the segment mode (NT7701)
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 12 OF 16
Refer to Fig. 3, Common mode characteristics (NT7702).
At Ta = 0 °C to +50 °C, VDD = 3.0V±5%, VSS = 0V.
Table 7
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 13 OF 16
Figure 3: Timing waveform of the common mode (NT7702)
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 14 OF 16
4.4 Precaution when Connecting and Disconnecting the Power
Be careful when connecting or disconnecting the power.
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current,
which may occur, if a voltage is supplied to the LCD driver power supply while the logic system
power supply is floating.
The details are as follows:
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When connecting the power supply, connect the LCD driver power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system power
after disconnecting the LCD driver power.
We recommend that you connect a serial resistor (50-100 Ω) or fuse to the LCD driver power V0
of the system as a current limiting device. Also, set a suitable value of the resistor in
consideration of LCD display grade.
In addition, when connecting the logic power supply, the logic condition of this LSI inside is
insecure. Therefore connect the LCD driver power supply after resetting the logic condition of
this LSI inside on /DOFF function. After that, the /DOFF cancel the function after the LCD
driver power supply has become stable. Furthermore, when disconnecting the power, set the
LCD driver output pins to level VSS on the /DOFF function. After that, disconnect the logic
system power after disconnecting the LCD driver power.
When connecting the power supply, follow the recommended sequence shown.
Figure 4: Power sequence
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 15 OF 16
5. Remark
VL-PS-PDA320240D-02 REV. A
(PDA320240D-02)
JUN/2005
PAGE 16 OF 16
6. LCD Cosmetic Conditions
a.) Reference document follow VL-QUA-012B.
b.) LCD size of the product is middle.
“Varitronix Limited reserves the right to change this specification.”
FAX:(852) 2343-9555.
URL:http://www.varitronix.com
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