CRCW06030000ZOEA_技术文档

SiC414, SiC424

Vishay Siliconix

6 A, microBUCK^®SiC414, SiC424

Integrated Buck Regulator with 5 V LDO

DESCRIPTION

FEATURES

•

High efficiency > 95 %

The Vishay Siliconix SiC414 and SiC424 are an advanced

stand-alone synchronous buck regulator featuring integrated

power MOSFETs, bootstrap switch, and an internal 5 V_LDO

in a space-saving PowerPAK MLP44-28L package.

6 A continuous output current capability

Integrated bootstrap switch

Integrated 5 V/200 mA LDO with bypass logic

Temperature compensated current limit

The SiC414 and SiC424 are capable of operating with all

ceramic solutions and switching frequencies up to 1 MHz.

The programmable frequency, synchronous operation and

selectable power-save allow operation at high efficiency

across the full range of load current. The internal LDO may

be used to supply 5 V for the gate drive circuits or it may be

bypassed with an external 5 V for optimum efficiency and

used to drive external n-channel MOSFETs or other loads.

Additional features include cycle-by-cycle current limit,

voltage soft-start, under-voltage protection, programmable

over-current protection, soft shutdown and selectable

power-save. The Vishay Siliconix SiC414 and SiC424 also

provides an enable input and a power good output.

Pseudo fixed-frequency adaptive on-time

control

•

All ceramic solution enabled

Programmable input UVLO threshold

Independent enable pin for switcher and LDO

Selectable ultrasonic power-save mode (SiC414)

Selectable power-save mode (SiC424)

Internal soft-start and soft-shutdown

1 % internal reference voltage

Power good output and over voltage protection

Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

PRODUCT SUMMARY

Input Voltage Range

Output Voltage Range

Operating Frequency

Continuous Output Current

Peak Efficiency

3 V to 28 V

0.75 V to 5.5 V

200 kHz to 1 MHz

6 A

APPLICATIONS

•

Notebook, desktop, and server computers

Digital HDTV and digital consumer applications

Networking and telecommunication equipment

Printers, DSL, and STB applications

Embedded applications

95 %

Package

PowerPAK MLP44-28L

Point of load power supplies

TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTION

LDO_EN

EN/PSV (Tri-State)

3.3 V

V_OUT

P_GOOD

28 27 26 25 24 23 22

V_OUT

FB

21

1

2

LX

V5V

A_GND

V_OUT

V_IN

20

19

18

17

PAD1

A_GND

3

4

5

6

7

P_GND

PAD3

LX

V_IN

PAD2

V_IN

P_GND

P

V_LDO

BST

_GND16

15

LX

10 11 12 13 14

8

9

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

This document is subject to change without notice.

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SiC414, SiC424

Vishay Siliconix

PIN CONFIGURATION (top view)

28 27 26 25 24 23 22

21

20

19

18

17

16

FB

1

2

3

4

5

6

7

PAD1

LX

V5V

A

GND

A

PAD3

LX

P

GND

V

P

OUT

PAD2

V

IN

V

P

GND

LDO

V

IN

15 LX

BST

PIN DESCRIPTION

Pin Number

Symbol

Description

Feedback input for switching regulator used to program the output voltage - connect to an external resistor

divider from V_OUTto A_GND

Bias input for internal analog circuits and gate drives - connect to external 3 V or 5 V supply or bias

connection to V_LDO

Analog ground.

1

FB

.

2

V5V

.

3, 26, PAD 1

A_GND

V_OUT

V_IN

4

Switcher output voltage sense pin, and also the input to the internal switch-over between V_OUTand V_LDO.

5, 8 to 11, PAD 2

6

Input supply voltage.

5 V LDO output.

V_LDO

Bootstrap pin - connect a capacitor from BST to LXBST to develop the floating supply for the high-side gate

drive.

7

BST

12

LXBST

LX

LX Boost - connect to the BST capacitor.

Switching (Phase) node.

Power ground.

15, 20, 21, PAD 3

13, 14, 16 to 19

P_GND

Open-drain power good indicator. High impedance indicates power is good. An external pull-up resistor is

required.

22

P_GOOD

23

24

I_LIM

Current limit sense pin - used to program the current limit by connecting a resistor from I_LIMto LXS.

LX sense - connect to R_ILIMresistor.

LXS

Enable/power save input for the switching regulator - connect to A_GNDto disable the switching regulator.

Float to operate in forced continuous mode (power save disabled).

For SiC414, connect to V5V to operate with ultrasonic power save mode enabled.

For SiC424, connect to V5V to operate with power save mode enabled with no minimum frequency.

25

EN/PSV

27

28

t_ON

On-time programming input - set the on-time by connecting through a resistor to A_GND

Enable input for the LDO - connect ENL to A_GNDto disable the LDO. Drive with logic to + 3 V for logic

control, or program the V_INUVLO with a resistor divider between V_IN, ENL, and A_GND

.

ENL

.

ORDERING INFORMATION

Part Number

Package

SiC414CD-T1-GE3

PowerPAK MLP44-28

SiC424CD-T1-GE3

SiC414DB

PowerPAK MLP44-28

Reference board

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This document is subject to change without notice.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

FUNCTIONAL BLOCK DIAGRAM

5, 8 to 11, PAD2

2

22

GOOD

25

EN/PSV

P

V5V

V

IN

V

IN

V5V

A

GND

V5V

BST

7

Reference

Soft Start

Control and Status

3, 26, PAD1

DL

LX

12, 15, 20, 21,

24 PAD3

+

-

On-Time

Generator

Gate Drive

Control

FB

1

V5V

FB Comparator

TON

P

GND

27

13, 14, 16 to 19

Zero Cross

Detector

V

OUT

4

I

LIM

Valley1-Limit

Bypass Comparator

23

V

IN

V

LDO

A

B

MUX

6

Y

LDO

ENL

28

ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)

A

Electrical Parameter

Conditions

to P_GND

to GND

to P_GND

to LX

Limits

Unit

V_IN

- 0.3 to + 30

- 2 to + 30

LX

LX (transient < 100 ns)

EN/PSV, P_GOOD, I_LIM

- 0.3 to + (V5V + 0.3)

- 0.3 to + 6

V_OUT, V_LDO, FB

V5V

t_ON

V

- 0.3 to + (V5V - 1.5)

- 0.3 to + 6

BST

to P_GND

- 0.3 to + 35

ENL

- 0.3 to V_IN

A_GNDto P_GND

- 0.3 to + 0.3

Temperature

Maximum Junction Temperature

Storage Temperature

Power Dissipation

150

°C

- 65 to 150

b

Junction to Ambient Thermal Impedance (R_thJA

)

IC Section

43

3.4

1.3

°C/W

W

Ambient Temperature = 25 °C

Ambient Temperature = 100 °C

Maximum Power Dissipation

ESD Protection

HBM

2

kV

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is

not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

This document is subject to change without notice.

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)

Parameter

Min.

Typ.

Max.

28

Unit

V_IN

3

V5V to P_GND

3

5.5

V

V_OUTto P_GND

0.75

5.5

Temperature

°C

Recommended Ambient Temperature

- 40 to 85

Note:

For proper operation, the device should be used within the recommended conditions.

ELECTRICAL SPECIFICATIONS

Test Conditions Unless Specified

V

_IN= 12 V, V5V = 5 V, T_A= + 25 °C for typ.,

- 40 °C to + 85 °C for min. and max.,

T_J= < 125 °C

Parameter

Symbol

Min.

Typ.

Max.

Unit

Input Supplies

V_INUVLO Threshold Voltage^a

(not available for V5V < 4.5 V)

Sensed at ENL pin, rising edge

Sensed at ENL pin, falling edge

2.4

2.6

2.4

0.2

2.9

2.7

0.2

8.5

2.95

2.57

V_UVLO

V_{UVLO_HYS}

V_UVLO

2.23

V_INUVLO Hysteresis

V

Measured at V_DDpin, rising edge

Measured at V_DDpin, falling edge

2.5

2.4

3.0

2.9

V5V UVLO Threshold Voltage

V_DDUVLO Hysteresis

V_{UVLO_HYS}

EN/PSV, ENL = 0 V, V_IN= 28 V

20

7

V_INSupply Current

I_IN

Standby mode:

ENL = V5V, EN/PSV = 0 V

130

µA

EN/PSV, ENL = 0 V, V5V = 5 V

EN/PSV, ENL = 0 V, V5V = 3 V

3

2

SiC414, EN/PSV = V5V, no load,

(f_sw= 25 kHz), V_FB> 0.75 V^b

1

SiC424, EN/PSV = V5V, no load,

V5V Supply Current

I_DD

0.4

4

V

_FB> 0.75 V^b

mA

V5V = 5 V, f_sw= 250 kHz,

EN/PSV = floating, no load^b

V5V = 5 V, f_sw= 250 kHz,

EN/PSV = floating, no load^b

2.5

Controller

Static V_INand load, - 40 °C to + 85 °C,

V5V = 3 V or 5 V

FB Comparator Threshold

V_FB

0.7425 0.750 0.7575

V

Continuous mode

200

1000

Frequency Range^b

f_sw

kHz

Minimum f_SW, (SiC414 only),

EN/PSV= V5V, no load

25

10

Bootstrap Switch Resistance



Timing

Continuous mode operation V_IN= 15 V,

On-Time

t_ON

1350

1500

1650

V_OUT= 3 V, f_SW= 300 kHz, R_ton= 133 k

Minimum On-Time^b

Minimum Off-Time^b

t_{ON, min.}

t_{OFF, min.}

80

ns

V5V = 5 V

V5V = 3 V

320

390

Soft Start

Soft Start Time^b

t_SS

1.7

500

0

ms

k

mV

Analog Inputs/Outputs

V_OUTInput Resistance

Current Sense

R_O-IN

Zero-Crossing Detector Threshold Voltage

V_Sense-th

LX-P_GND

- 3

+ 3

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This document is subject to change without notice.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

ELECTRICAL SPECIFICATIONS

Test Conditions Unless Specified

_IN= 12 V, V5V = 5 V, T_A= + 25 °C for typ.,

- 40 °C to + 85 °C for min. and max.,

T_J= < 125 °C

V

Parameter

Symbol

Min.

Typ.

Max.

Unit

Power Good

Upper limit, V > internal reference 750 mV

+ 20

- 10

4

FB

PG_V_{TH_UPPER}

PG_T_d

Power Good Threshold Voltage

%

Lower limit, V < internal reference 750 mV

FB

V5V = 5 V

V5V = 3 V

Start-Up Delay Time

(between PWM enable and P_GOODhigh)

ms

2

Fault (noise-immunity) Delay Time^b

Power Good Leakage Current

Power Good On-Resistance

Fault Protection

PG_I_CC

PG_I_LK

5

µs

µA



1

PG_R_DS-ON

10

Valley Current Limit

V5V = 5 V, R_ILIM= 5 k

3

4

8

0

5

A

I_LIMSource Current

I_LIM

µA

mV

I_LIMComparator Offset Voltage

V_ILM-LK

With respect to A_GND

- 8

+ 8

V_FBwith respect to Internal 750 mV

reference, 8 consecutive clocks

Output Under-Voltage Fault

V_{OUV_Fault}

P_{SAVE_VTH}

- 25

+ 10

+ 20

Smart Power-Save Protection

Threshold Voltage^b

V_FBwith respect to internal 750 mV

reference

%

V

_FBwith respect to internal 750 mV

reference

Over-Voltage Protection Threshold

Over-Voltage Fault Delay^b

Over Temperature Shutdown^b

Logic Inputs/Outputs

t_OV-Delay

T_Shut

5

µs

°C

10 °C hysteresis

ENL

150

Logic Input High Voltage

Logic Input Low Voltage

V_IH

V_IL

1

V

0.4

EN/PSV

45

1V

100

Input for PSAVE Operation^b

% of V5V

%

EN/PSV

42

Input for Forced Continuous Operation^b

EN/PSV Input for Disabling Switcher

EN/PSV Input Bias Current

ENL Input Bias Current

FB Input Bias Current

0

0.4

+ 10

18

V

I_EN

EN/PSV = V5V or A_GND

V_IN= 28 V

- 10

11

µA

FBL_I_LK

FB = V5V or A_GND

- 1

+ 1

Linear Dropout Regulator

V_LDOAccuracy

V_{LDO_ACC}

LDO_I_LIM

V_LDOload = 10 mA

4.9

5

5.1

V

Start-up and foldback, V_IN= 12 V

Operating current limit, V_IN= 12 V

115

200

LDO Current Limit

mA

135

- 140

- 450

V_LDOto V_OUTSwitch-Over Threshold^c

V_LDOto V_OUTNon-Switch-Over Threshold^c

V_LDOto V_OUTSwitch-Over Resistance

V_LDO-BPS

V_LDO-NBPS

R_LDO

+ 140

+ 450

mV



V_OUT= 5 V

2

From V_INto V_VLDO, V_VLDO= 5 V,

LDO Drop Out Voltage^d

1.2

V

I

_VLDO= 100 mA

Notes:

a. V_{IN UVLO}is programmable using a resistor divider from V_INto ENL to A_GND. The ENL voltage is compared to an internal reference.

b. Guaranteed by design.

c. The switch-over threshold is the maximum voltage differential between the V_LDOand V_OUTpins which ensures that V_LDOwill internally

switch-over to V_OUT. The non-switch-over threshold is the minimum voltage differential between the V_LDOand V_OUTpins which ensures that

V

_LDOwill not switch-over to V_OUT

.

d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

This document is subject to change without notice.

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

90

80

90

80

70

60

50

40

30

V

IN

= 12 V, V

= 1 V, FSW = 500 kHz

OUT

70

60

50

40

30

20

10

0

V

IN

= 12 V, V

= 1 V, FSW = 500 kHz (at 6 A)

OUT

0

3

1

2

3

I

4

5

6

7

0

3

1

2

3

4

5

6

7

(A)

I

(A)

OUT

Efficiency vs. I_OUT

(in Continuous Conduction Mode)

Efficiency vs. I_OUT

(in Power-Save-Mode)

1.05

1.04

1.03

1.02

1.01

1

1.05

1.04

1.03

1.02

1.01

1

V

IN

= 12 V, V

= 1 V, FSW = 500 kHz (at 6 A)

OUT

V

IN

= 12 V, V

= 1 V, FSW = 500 kHz

OUT

0.99

0.98

0.97

0.96

0.95

0.99

0.98

0.97

0.96

0.95

1

2

3

I

4

5

6

7

1

2

3

4

5

6

7

I

(A)

OUT

V_OUTvs. I_OUT

(in Continuous Conduction Mode)

V_OUTvs. I_OUT

(in Power-Save-Mode)

1.05

1.04

1.03

1.02

1.01

1

1.05

1.04

1.03

1.02

1.01

1

V

OUT

= 1 V, I

= 0 A

OUT

V

= 1 V, I

= 6 A

OUT

0.99

0.98

0.97

0.96

0.95

0.99

0.98

0.97

0.96

0.95

6

9

12

15

(V)

18

21

24

6

9

12

V

15

(V)

18

21

24

V

IN

V

_OUTvs. V_INat I_OUT= 0 A

V

_OUTvs. V_INat I_OUT= 6 A

(in Continuous Conduction Mode, FSW = 500 kHz)

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Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

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This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

1.05

1.04

1.03

50

45

40

35

30

25

20

15

10

5

V

= 1 V, I

= 0 A

OUT

1.02

1.01

1

V

OUT

= 1 V, I

= 6 A, FSW = 500 kHz

OUT

0.99

0.98

0.97

0.96

0.95

0

3

6

9

12

15

(V)

18

21

24

0

5

10

15

20

25

V

IN

(V)

V

IN

V_OUTvs. V_IN

(I_OUT= 0 A in Power-Save-Mode)

V_OUTRipple vs. V_IN

(I_OUT= 6 A in Continuous Conduction Mode)

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

V

OUT

= 1 V, I

= 0 A, FSW = 500 kHz

V

OUT

= 1 V, I

= 0 A, PSV Mode

OUT

0

5

10

15

20

25

0

5

10

15

20

25

V

IN

(V)

V

IN

(V)

V_OUTRipple vs. V_IN

(I_OUT= 0 A in Continuous Conduction Mode)

V_OUTRipple vs. V_IN

(I_OUT= 0 A in Power-Save-Mode)

550

525

500

475

450

425

400

375

350

520

470

420

370

320

270

220

170

120

70

V

1

= 12 V, V

= 1 V, FSW = 500 kHz (at 6 A)

IN

OUT

V

= 12 V, V

= 1 V, FSW = 500 kHz (at 6 A)

IN

OUT

20

0

2

3

4

5

6

7

0

1

2

3

4

5

6

7

I

(A)

I

(A)

OUT

FSW vs. I_OUT

(in Continuous Conduction Mode)

FSW vs. I_OUT

(in Power-Save-Mode)

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

This document is subject to change without notice.

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

LX Switching Node

2V/div.

2ms/div

Output Ripple Voltage

20 mV/div.

2 ms/div

V_OUTRipple in Continuous Conduction Mode (No Load)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

V_OUTRipple in Power Save Mode (No Load)

(V_IN= 12 V, V_OUT= 1 V)

Output Current

2 A/div.

Output Current

2 A/div.

5 µs/div.

Output Voltage

50 mV/div.

5 µs/div.

AC Coupling

Output Voltage

50 mV/div.

5 µs/div.

AC Coupling

Transient Response in Continuous Conduction Mode

(0.2 A - 6 A)

Transient Response in Continuous Conduction Mode

(6 A - 0.2 A)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

Output Current

2 A/div.

Output Current

2 A/div.

5 µs/div.

Output Voltage

50 mV/div.

5 µs/div.

AC Coupling

Output Voltage

50 mV/div.

5 µs/div.

AC Coupling

Transient Response in Power Save Mode

(0.2 A - 6 A)

Transient Response in Power Save Mode

(6 A - 0.2 A)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz at 6 A)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz at 6A)

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Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC414, SiC424

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

Start-up with V_INRamping up

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

Over-Current Protection

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

APPLICATIONS INFORMATION

Device Overview

t

ON

The SiC414 and SiC424 are a step down synchronous buck

DC/DC converter with integrated power FETs and

programmable LDO. The device is capable of 6 A operation

at very high efficiency in a tiny 4 mm x 4 mm - 28 pin

package. The programmable operating frequency range of

200 kHz to 1 MHz, enables the user to optimize the solution

for minimum board space and optimum efficiency.

The buck controller employs pseudo-fixed frequency

adaptive on-time control. This control scheme allows fast

transient response thereby lowering the size of the power

components used in the system.

V

IN

V

LX

C

IN

V

Q1

Q2

FB

FB threshold

V

LX

V

OUT

L

ESR

FB

+

C

OUT

The buck controller employs pseudo-fixed frequency

adaptive on-time control. This control scheme allows fast

transient response thereby lowering the size of the power

components used in the system.

Figure 1 - PWM Control Method, V_OUTRipple

Input Voltage Range

The SiC414 and SiC424 requires two input supplies for

normal operation: V_INand V5V. V_INoperates over the wide

range from 3 V to 28 V. V5V requires a 3.3 V or 5 V supply

input that can be an external source or the internal LDO

configured to supply 5 V.

The adaptive on-time control has significant advantages over

traditional control methods used in the controllers today.

• Reduced component count by eliminating DCR sense or

current sense resistor as no need of a sensing inductor

current.

• Reduced saves external components used for

compensation by eliminating the no error amplifier and

other components.

• Ultra fast transient response because of fast loop,

absence of error amplifier speeds up the transient

response.

Pseudo-Fixed Frequency Adaptive On-Time Control

The PWM control method used by the SiC414 and SiC424

is pseudo-fixed frequency, adaptive on-time, as shown in

figure 1. The ripple voltage generated at the output capacitor

ESR is used as a PWM ramp signal. This ripple is used to

trigger the on-time of the controller.

The adaptive on-time is determined by an internal one-shot

timer. When the one-shot is triggered by the output ripple, the

device sends a single on-time pulse to the high side

MOSFET. The pulse period is determined by V_OUTand V_IN;

the period is proportional to output voltage and inversely

proportional to input voltage. With this adaptive on-time

arrangement, the device automatically anticipates the

on-time needed to regulate V_OUTfor the present V_IN

condition and at the selected frequency.

• Predictable frequency spread because of constant on-time

architecture.

• Fast transient response enables operation with minimum

output capacitance Overall, superior performance

compared to fixed frequency architectures.

Overall, superior performance compared to fixed frequency

architectures.

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SiC414, SiC424

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t_ONlimitations and V5V Supply Voltage

For V5V below 4.5 V, the t_ONaccuracy may be limited by the

input voltage.

The original R_tONequation is accurate if V_INsatisfies the

below relation over the entire V_INrange:

On-Time One-Shot Generator (t_ON

Frequency

) and Operating

The figure 2 shows the on-chip implementation of on-time

generation. The FB Comparator output goes high when V_FB

is less than the internal 750 mV reference. This feeds into the

gate drive and turns on the high-side MOSFET, and also

starts the one-shot timer. The one-shot timer uses an internal

comparator and a capacitor. One comparator input is

connected to V_OUT, the other input is connected to the

capacitor. When the on-time begins, the internal capacitor

charges from zero volts through a current which is

proportional to V_IN. When the capacitor voltage reaches

V_IN< (V5V - 1.6 V) x 10

If V_INexceeds (V5V - 1.6 V) x 10, for all or part of the V_IN

range, the R_tONequation is not accurate. In all cases where

V_IN> (V5V - 1.6 V ) x 10, the R_tONequation must be modified

as follows.

V_OUT, the on-time is completed and the high-side MOSFET

(V5V - 1.6 V) x 10

V_OUT

1

turns off.

R_tON

=

- 400 Ω x

25 pF x f_sw

Gate

drives

V_IN

Note that when V_IN> (V5V - 1.6 V) x 10, the actual on-time

is fixed and does not vary with V_IN. When operating in this

condition, the switching frequency will vary inversely with V_IN

rather than approximating a fixed frequency.

FB comparator

FB

V_REF

-

+

Q1

V

DH

DL

V

L

OUT

LX

V

ESR

OUT

FB

One-shot

timer

Q2

V

+

IN

V_OUTVoltage Selection

C

The switcher output voltage is regulated by comparing V_OUT

as seen through a resistor divider at the FB pin to the internal

750 mV reference voltage, see figure 3.

R

On-time = K x R x (V

V )

OUT/ IN

ton

Figure 2 - On-Time Generation

To FB pin

V

OUT

R

1

This method automatically produces an on-time that is

proportional to V_OUTand inversely proportional to V_IN. Under

steady-state conditions, the switching frequency can be

determined from the on-time by the following equation.

R

2

V

OUT

f

=

SW

t

x V

IN

ON

Figure 3 - Output Voltage Selection

The SIC414 and SiC424 uses an external resistor to set the

ontime which indirectly sets the frequency. The on-time can

be programmed to provide operating frequency from

200 kHz to 1 MHz using a resistor between the t_ONpin and

ground. The resistor value is selected by the following

equation.

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage V_OUTis offset by the output ripple according to the

following equation.

V_OUT= 0.75 x (1 + R₁/R₂) + V_RIPPLE/2

V_IN

1

R_tON

=

- 400 Ω x

V_OUT

25 pF x f_sw

Enable and Power-Save Inputs

The EN/PSV and ENL inputs are used to enable or disable

the switching regulator and the LDO. When EN/PSV is low

(grounded), the switching regulator is off and in its lowest

power state. When off, the output of the switching regulator

soft-discharges the output into a 10  internal resistor via the

V_OUTpin. When EN/PSV is allowed to float, the pin voltage

will float to 33 % of the voltage at V5V. The switching

regulator turns on with power-save disabled and all switching

is in forced continuous mode. For V5V < 4.5 V, it is

recommended to force 33 % of the V5V voltage on the

EN/PSV pin to operate in forced continuous mode.

The maximum R_tONvalue allowed is shown by the following

equation.

V

IN_MIN

R

=

ton_MAX

15 µA

Immediately after the on-time, the DL (drive signal for the

low side FET) output drives high to turn on the low-side

MOSFET. DL has a minimum high time of ~ 320 ns, after

which DL continues to stay high until one of the following

occurs:

When EN/PSV is high (above 45 % of the voltage at V5V) for

SiC414, the switching regulator turns on with ultrasonic

• V_FBfalls below the 750 mV reference.

• The zero cross detector senses that the voltage on the LX

node is below ground. Power save is activated when a

zero crossing is detected.

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SiC414, SiC424

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power-save enabled. The SiC414 ultrasonic power-save

operation maintains a minimum switching frequency of

25 kHz, for applications with stringent audio requirements.

When EN/PSV is high (above 45 % of the voltage at V5V) for

SiC424, the switching regulator turns on with power-save

enabled. The SiC424 power-save operation is designed to

maximize efficiency at light loads with no minimum frequency

limits. This makes the SiC424 an excellent choice for

portable and battery-operated systems.

The ENL input is used to control the internal LDO. This input

provides a second function by acting as a V_INULVO sensor

for the switching regulator. When ENL is low (grounded), the

LDO is off. When ENL is a logic high but below the V_INUVLO

threshold (2.6 V typical), then the LDO is on and the switcher

is off. When ENL is above the V_INUVLO threshold, the LDO

is enabled and the switcher is also enabled if the EN/PSV pin

is not grounded.

high to turn the low-side MOSFET on. This draws current

from V_OUTthrough the inductor, forcing both V_OUTand V_FB

to fall. When V_FBdrops to the 750 mV threshold, the next DH

(the drive signal for the high side FET) on-time is triggered.

After the on-time is completed the high-side MOSFET is

turned off and the low-side MOSFET turns on. The low-side

MOSFET remains on until the inductor current ramps down

to zero, at which point the low-side MOSFET is turned off.

Because the on-times are forced to occur at intervals no

greater than 40 µs, the frequency will not fall far below

25 kHz. Figure 5 shows ultrasonic power-save operation.

Forced Continuous Mode Operation

The SiC414 and SiC424 operates the switcher in Forced

Continuous Mode (FCM) by floating the EN/PSV pin (see

figure 4). In this mode of operation, the MOSFETs are turned

on alternately to each other with a short dead time between

them to avoid cross conduction. This feature results in

uniform frequency across the full load range with the

trade-off being poor efficiency at light loads due to the

high-frequency switching of the MOSFETs.

For V5V < 4.5 V, it is recommended to force 33 % of the V5V

voltage on the EN/PSV pin to operate in forced continuous

mode.

After the 40 μs time-out, DL drives high if V_FBhas not reached the FB threshold

Figure 5 - Ultrasonic Power-Save Operation

FB ripple

voltage (VFB)

FB threshold

(750 mV)

Power-Save Mode Operation (SiC424)

The SiC424 provides power-save operation at light loads

with no minimum operating frequency. With power-save

enabled, the internal zero crossing comparator monitors the

inductor current via the voltage across the low-side MOSFET

during the off-time. If the inductor current falls to zero for 8

consecutive switching cycles, the controller enters

power-save operation. It will turn off the low-side MOSFET

on each subsequent cycle provided that the current crosses

zero. At this time both MOSFETs remain off until V_FBdrops

to the 750 mV threshold. Because the MOSFETs are off , the

load is supplied by the output capacitor. If the inductor

current does not reach zero on any switching cycle, the

controller immediately exits powersave and returns to forced

continuous mode. Figure 6 shows power-save mode

operation at light loads.

DC load current

Inductor

current

DH on-time is triggered when

On-time

(t

V

reaches the FB threshold

FB

)

ON

DH

DL

DL drives high when on-time is completed.

DL remains high until V falls to the FB threshold.

FB

Figure 4 - Forced Continuous Mode Operation

Ultrasonic Power-Save Operation (SiC414)

The SiC414 provides ultrasonic power-save operation at

light loads, with the minimum operating frequency fixed at

slightly under 25 kHz. This is accomplished by using an

internal timer that monitors the time between consecutive

high-side gate pulses. If the time exceeds 40 µs, DL drives

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SiC414, SiC424

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SmartDrive^TM

Dead time varies

according to load

For each DH pulse the DH driver initially turns on the high

side MOSFET at a lower speed, allowing a softer, smooth

turn-off of the low-side diode. Once the diode is off and the

LX voltage has risen 0.5 V above P_GND, the SmartDrive

circuit automatically drives the high-side MOSFET on at a

rapid rate. This technique reduces switching losses while

maintaining high efficiency and also avoids the need for

snubbers for the power MOSFETs.

FB Ripple

Voltage

FB threshold

(750 mV)

(V_FB

)

Inductor

Current

Zero (0 A)

Current Limit Protection

On-time (T_ON

)

The device features programmable current limiting, which is

accomplished by using the R_DS(ON)of the lower MOSFET for

current sensing. The current limit is set by RILIM resistor.

The R_ILIMresistor connects from the ILIM pin to the LXS pin

which is also the drain of the low-side MOSFET. When the

low-side MOSFET is on, an internal ~ 8 µA current flows from

the ILIM pin and through the R_ILIMresistor, creating a voltage

drop across the resistor. While the low-side MOSFET is on,

the inductor current flows through it and creates a voltage

across the R_DS(ON). The voltage across the MOSFET is neg-

ative with respect to ground. If this MOSFET voltage drop

exceeds the voltage across R_ILIM, the voltage at the ILIM pin

will be negative and current limit will activate. The current

limit then keeps the low-side MOSFET on and will not allow

another high-side on-time, until the current in the low-side

MOSFET reduces enough to bring the ILIM voltage back up

to zero. This method regulates the inductor valley current at

the level shown by ILIM in figure 8.

DH On-time is triggered when

V_FBreaches the FB Threshold

DH

DL

DL drives high when on-time is completed.

DL remains high until inductor current reaches zero.

Figure 6 - Power-Save Mode Operation

Smart Power-Save Protection

Active loads may leak current from a higher voltage into the

switcher output. Under light load conditions with power-save

mode enabled, this can force V_OUTto slowly rise and reach

the over-voltage threshold, resulting in a hard shutd-own.

Smart power-save prevents this condition.

When the FB voltage exceeds 10 % above nominal, the

device immediately disables power-save, and DL drives high

to turn on the low-side MOSFET. This draws current from

V_OUTthrough the inductor and causes V_OUTto fall. When

V_FBdrops back to the 750 mV trip point, a normal t_ON

switching cycle begins.

I

PEAK

I

LOAD

I

LIM

This method prevents a hard OVP shutdown and also cycles

energy from V_OUTback to V_IN. It also minimizes operating

power by avoiding forced conduction mode operation.

Figure 7 shows typical waveforms for the smart power-save

feature.

Time

Figure 8 - Valley Current Limit

Setting the valley current limit to 6 A results in a 6 A peak

inductor current plus peak ripple current. In this situation, the

average (load) current through the inductor is 6 A plus

one-half the peak-to-peak ripple current.

V

OUT

drifts up to due to leakage

current flowing into C

OUT

V

discharges via inductor

OUT

Smart power save

threshold (825 mV)

and low-side MOSFET

The internal

8

µA current source is temperature

Normal V ripple

compensated at 4100 ppm in order to provide tracking with

the R_DS(ON). The R_ILIMvalue is calculated by the following

equation.

OUT

FB

threshold

DH and DL off

R_ILIM= 1250 x I_LIMx [0.088 x (5 V - V5V) + 1]

High-side

drive (DH)

Single DH on-time pulse

after DL turn-off

When selecting a value for R_ILIMdo not exceed the absolute

maximum voltage value for the ILIM pin. Note that because

the low-side MOSFET with low R_DS(ON)is used for current

sensing, the PCB layout, solder connections, and PCB

connection to the LX node must be done carefully to obtain

good results. R_ILIMshould be connected directly to LXS

(pin 24).

Low-side

drive (DL)

DL turns on when smart

PSAVE threshold is reached

Normal DL pulse after DH

on-time pulse

DL turns off FB

threshold is reached

Figure 7 - Smart Power-Save

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SiC414, SiC424

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Soft-Start of PWM Regulator

LDO Regulator

Soft-start is achieved in the PWM regulator by using an

internal voltage ramp as the reference for the FB

comparator. The voltage ramp is generated using an internal

charge pump which drives the reference from zero to 750 mV

in ~ 1.8 mV increments, using an internal ~ 500 kHz

oscillator. When the ramp voltage reaches 750 mV, the ramp

is ignored and the FB comparator switches over to a fixed

750 mV threshold. During soft-start the output voltage tracks

the internal ramp, which limits the start-up inrush current and

provides a controlled soft-start profile for a wide range of

applications. Typical soft-start ramp time is 1.7 ms.

During soft-start the regulator turns off the low-side MOSFET

on any cycle if the inductor current falls to zero. This prevents

negative inductor current, allowing the device to start into a

pre-biased output. This soft start operation is implemented

even if FCM is selected. FCM operation is allowed only after

P_GOODis high.

The device features an integrated LDO regulator with a fixed

output voltage of 5 V. There is also an enable pin (ENL) for

the LDO that provides independent control. The LDO voltage

can also be used to provide the bias voltage for the switching

regulator.

A minimum capacitance of 1 µF referenced to A_GNDis

normally required at the output of the LDO for stability. If the

LDO is providing bias power to the device, then a minimum

0.1 µF capacitor referenced to A_GNDis required, along with

a minimum 1 µF capacitor referenced to P_GNDto filter the

gate drive pulses. Refer to the layout guide-lines section.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

1. ENL pin

2. V_LDOoutput

3. V_INinput voltage

Power Good Output

The power good (P_GOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage is

10 % below the nominal voltage, P_GOODis pulled low. It is

held low until the output voltage returns to the nominal

voltage. P_GOODis held low during start-up and will not be

allowed to transition high until soft-start is completed (when

V_FBreaches 750 mV) and typically 4 ms has passed.

P_GOODwill transition low if the V_FBpin exceeds + 20 % of

nominal, which is also the over-voltage shutdown threshold

(900 mV). P_GOODalso pulls low if the EN/PSV pin is low

when V5V is present.

When the ENL pin is high, the LDO will begin start-up, see

figure 9. During the initial phase, when the LDO output

voltage is near zero, the LDO initiates a current-limited

start-up (typically 85 mA) to charge the output capacitor.

When V_LDOhas reached 90 % of the final value, the LDO

current limit is increased to ~ 200 mA and the LDO output is

quickly driven to the nominal value by the internal LDO reg-

ulator.

V

final

VLDO

Voltage regulating with

~ 200 mA current limit

90 % of V

VLDO

Output Over-Voltage Protection

Over-Voltage Protection (OVP) becomes active as soon as

the device is enabled. The threshold is set at 750 mV + 20 %

(900 mV). When V_FBexceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN/PSV input is

toggled or V5V is cycled. There is a 5 µs delay built into the

OVP detector to prevent false transitions. P_GOODis also low

after an OVP event.

Constant current startup

Figure 9 - LDO Start-Up

LDO Switch-over Function

The SiC414 and SiC424 includes a switch-over function for

the LDO. The switch-over function is designed to increase

efficiency by using the more efficient DC/DC converter to

power the LDO output, avoiding the less efficient LDO

regulator when possible. The switch-over function connects

the V_LDOpin directly to the V_OUTpin using an internal switch.

When the switch-over is complete the LDO is turned off,

which results in a power savings and maximizes efficiency. If

the LDO output is used to bias the SiC414 and SiC424, then

after switch-over the device is self-powered from the

switching regulator with the LDO turned off.

Output Under-Voltage Protection

When V_FBfalls to 75 % of its nominal voltage (falls to

562.5 mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to turn off

the MOSFETs. The controller stays off until EN/PSV is

toggled or V5V is cycled.

V5V UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switching

and tri-states the DH/DL drivers until V5V rises above 2.9 V.

An internal Power-On Reset (POR) occurs when V5V

exceeds 2.9 V, which resets the fault latch and soft-start

counter to begin the soft-start cycle. The SiC414 and SiC424

then begins a soft-start cycle. The PWM will shut off if V5V

falls below 2.7 V.

The switch-over logic waits for 32 switching cycles before it

starts the switch-over. There are two methods that determine

the switch-over of V_LDOto V_OUT

.

In the first method, the LDO is already in regulation and the

DC/DC converter is later enabled. As soon as the P_GOOD

output goes high, the 32 cycle counter is started. The

voltages at the V_LDOand V_OUTpins are then compared; if the

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SiC414, SiC424

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two voltages are within 300 mV (typically) of each other,

within 32 cycles, the V_LDOpin connects to the V_OUTpin using

an internal switch, and the LDO is turned off.

In the second method, the DC/DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90 % of its final

value. At this time, the V_LDOand V_OUTpins are compared,

and if within 300 mV (typically) the switch-over occurs and

the LDO is turned off.

threshold and stays above 1 V, then the switcher will turn off

but the LDO remains on. The V_INUVLO function has a typical

threshold of 2.6 V on the V_INrising edge.The falling edge

threshold is 2.4 V.

Note that it is possible to operate the switcher with the LDO

disabled, but the ENL pin must be below the logic low

threshold (0.4 V maximum). The table below summarizes the

function of the ENL and EN pins, with respect to the rising

edge of ENL.

EN

ENL

LDO

Off

On

Switcher

Off

Switch-Over Limitations on V_OUTand V_LDO

Low

High

Low

High

Low

High

Low, < 0.4 V

High, < 2.6 V

High, > 2.6 V

Because the internal switch-over circuit always compares

the V_OUTand V_LDOpins at start-up, there are voltage

limitations on permissible combinations of these pins.

Consider the situation where V_OUTis programmed to 4.7 V.

After start-up, the device would connect V_OUTto V_LDOand

disable the LDO, since the two voltages are within the

300 mV switch-over window. To avoid unwanted switch-

over, the minimum difference between the voltages for V_OUT

and V_LDOshould be 500 mV.

On

Off

On

Figure 11 below shows the ENL voltage thresholds and their

effect on LDO and switcher operation.

Switch-Over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that are

inherent to its construction, as shown in figure 10.

Switchover

control

Switchover

MOSFET

V

OUT

V

LDO

Parastic diode

V5V

Figure 10 - Switch-Over MOSFET Parasitic Diodes

Figure 11 - ENL Thresholds

There are some important design rules that must be followed

to prevent forward bias of these diodes. The following two

conditions need to be satisfied in order for the parasitic

diodes to stay off.

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6 V, it is impossible to

determine if the LDO output is going to be used to power the

device or not. In self-powered operation where the LDO will

power the device, it is necessary during the LDO start-up to

hold the PWM switching off until the LDO has reached 90 %

of the final value. This prevents overloading the current-

limited LDO output during the LDO start-up. However, if the

switcher was previously operating (with EN/PSV high but

ENL at ground, and V5V supplied externally), then it is

undesirable to shut down the switcher. To prevent this, when

the ENL input is above 2.6 V (above the V_INUVLO

threshold), the internal logic checks the P_GOODsignal. If

P_GOODis high, then the switcher is already running and the

LDO will run through the start-up cycle without affecting the

switcher. If P_GOODis low, then the LDO will not allow any

PWM switching until the LDO output has reached 90 % of its

final value.

• V5V  V_LDO

• V5V  V_OUT

If either V_LDOor V_OUTis higher than V5V, then the respective

diode will turn on and the SiC414 and SiC424 operating

current will flow through this diode. This has the potential of

damaging the device.

ENL Pin and V_INUVLO

The ENL pin also acts as the switcher under-voltage lockout

for the V_INsupply. The V_INUVLO voltage is programmable

via a resistor divider at the V_IN, ENL, and A_GNDpins. ENL is

the enable/disable signal for the LDO. In order to implement

the V_INUVLO there is also a timing requirement that needs

to be satisfied. If the ENL pin transitions low within

2 switching cycles and is < 1 V, then the LDO will turn off, but

the switcher remains on. If ENL goes below the V_INUVLO

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V_IN

1

Using the On-chip LDO to Bias the SIC414/SIC424

The following steps must be followed when using the onchip

LDO to bias the device.

• Connect V5V to V_LDObefore enabling the LDO.

• Any external load on V_LDOshould not exceed 40 mA until

the LDO voltage has reached 90 % of final value.

• Do not connect the EN pin directly to the V5V or any other

supply voltage if V_OUTis greater than or equal to 4.5 V.

Many applications connect the EN pin to V5V and control the

on/off of the LDO and PWM simultaneously with the ENL pin.

This allows one signal to control both the bias and power

output of the SiC414 and SiC424. When V_OUT> 4.5 V this

configuration can cause problems due to the parasitic diodes

in the LDO switchover circuitry. After the V_OUT> 4.5 V PWM

output is up and running the switchover diodes can hold up

V5V > UVLO even if the ENL pin is grounded, turning off the

LDO. Operating in this way can potentially damage the part.

R_tON

=

- 400 Ω x

V_OUT

25 pF x f_sw

To select R_tON, use the maximum value for V_IN, and for t_ON

use the value associated with maximum V_IN.

V

OUT

t

=

ON

V

x f

SW

INMAX.

t_ON= 303 ns at 13.2 V_IN, 1 V_OUT, 250 kHz

Substituting for R_tONresults in the following solution

R_tON= 130.9 k, use R_tON= 130 k.

Inductor Selection

In order to determine the inductance, the ripple current must

first be defined. Low inductor values result in smaller size but

create higher ripple current which can reduce efficiency.

Higher inductor values will reduce the ripple current/voltage

and for a given DC resistance are more efficient. However,

larger inductance translates directly into larger packages and

higher cost. Cost, size, output ripple, and efficiency are all

used in the selection process.

The ripple current will also set the boundary for power-save

operation. The switching will typically enter power-save

mode when the load current decreases to 1/2 of the ripple

current. For example, if ripple current is 4 A then Power-save

operation will typically start for loads less than 2 A. If ripple

current is set at 40 % of maximum load current, then power-

save will start for loads less than 20 % of maximum current.

The inductor value is typically selected to provide a ripple

current that is between 25 % to 50 % of the maximum load

current. This provides an optimal trade-off between cost,

efficiency, and transient performance.

Design Procedure

When designing a switch mode power supply, the input

voltage range, load current, switching frequency, and

inductor ripple current must be specified.

The maximum input voltage (V_INMAX) is the highest specified

input voltage. The minimum input voltage (V_INMIN) is

determined by the lowest input voltage after evaluating the

voltage drops due to connectors, fuses, switches, and PCB

traces.

The following parameters define the design:

• Nominal output voltage (V_OUT

• Static or DC output tolerance

• Transient response

)

• Maximum load current (I_OUT

)

There are two values of load current to evaluate - continuous

load current and peak load current. Continuous load current

relates to thermal stresses which drive the selection of the

inductor and input capacitors. Peak load current determines

During the DH on-time, voltage across the inductor is

(V_IN- V_OUT). The equation for determining inductance is

shown next.

instantaneous

component

stresses

and

filtering

requirements such as inductor saturation, output capacitors,

and design of the current limit circuit.

The following values are used in this design:

• V_IN= 12 V 10 %

• V_OUT= 1.5 V 4 %

• f_SW= 250 kHz

(V - V

) x t

ON

IN

OUT

L =

I

RIPPLE

Example

In this example, the inductor ripple current is set equal to

50 % of the maximum load current. Therefore ripple current

will be 50 % x 6 A or 3 A. To find the minimum inductance

needed, use the V_INand t_ONvalues that correspond to

V_INMAX.

• Load = 6 A maximum

Frequency Selection

Selection of the switching frequency requires making a

trade-off between the size and cost of the external filter

components (inductor and output capacitor) and the power

conversion efficiency.

The desired switching frequency is 250 kHz which results

from using component selected for optimum size and cost.

A resistor (R_tON) is used to program the on-time (indirectly

setting the frequency) using the following equation.

(13.2 V - 1 V) x 318 ns

L =

= 1.26 µH

3 A

A slightly larger value of 1.5 µH is selected. This will

decrease the maximum I_RIPPLEto 2.53 A.

Note that the inductor must be rated for the maximum DC

load current plus 1/2 of the ripple current. The ripple current

under minimum V_INconditions is also checked using the

following equations.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

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15

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SiC414, SiC424

Vishay Siliconix

load dI/dt is not much faster than the - dI/dt in the inductor,

then the inductor current will tend to track the falling load

current. This will reduce the excess inductive energy that

must be absorbed by the output capacitor, therefore a

smaller capacitance can be used.

25 pF x R

x V

OUT

tON

+ 10 ns = 311 ns

t

=

ON_VINMIN

V

INMIN

(V - V

) x t

ON

IN

OUT

I

=

RIPPLE

L

(10.8 - 1 V) x 311 ns

1.5µH

The following can be used to calculate the needed

capacitance for a given dI_LOAD/dt:

I

=

= 2.03 A

RIPPLE_VINMIN

Peak inductor current is shown by the next equation.

Capacitor Selection

The output capacitors are chosen based on required ESR

and capacitance. The maximum ESR requirement is

controlled by the output ripple requirement and the DC

tolerance. The output voltage has a DC value that is equal to

the valley of the output ripple plus 1/2 of the peak-to-peak

ripple. Change in the output ripple voltage will lead to a

change in DC voltage at the output.

The design goal is for the output voltage regulation to be

4 % under static conditions. The internal 750 mV reference

tolerance is 1 %. Assuming a 1 % tolerance from the FB

resistor divider, this allows 2 % tolerance due to V_OUTripple.

Since this 2 % error comes from 1/2 of the ripple voltage, the

allowable ripple is 4 %, or 40 mV for a 1 V output.

I_LPK= I_MAX+ 1/2 x I_RIPPLEMAX

I_LPK= 10 + 1/2 x 2.53 = 7.26 A

Rate of change of load current = dI_LOAD/dt

I_MAX= maximum load release = 6 A

I

V

I

MAX

LPK

L x

-

x dt

dl

LOAD

OUT

C

OUT

= I

LPK

x

2 (V - V

)

PK

OUT

Example

dl

1.25 A

LOAD

dt

Load

=

The maximum ripple current of 2.53 A creates a ripple

voltage across the ESR. The maximum ESR value allowed

is shown by the following equations.

1 µs

This causes the output current to move from 6 A to 0 A in

4.8 µs, giving the minimum output capacitance requirement

shown in the following equation.

V

40 mV

RIPPLE

ESR

=

MAX

I

2.53 A

RIPPLEMAX

7.26 6 A

1 V 1.25 A

= 15.8 mΩ

1.5 µH x

-

x 1 µs

MAX

C

= 7.26 x

OUT

2 (1.05 V - 1 V)

The output capacitance is chosen to meet transient

requirements. A worst-case load release, from maximum

load to no load at the exact moment when inductor current is

at the peak, determines the required capacitance. If the load

release is instantaneous (load changes from maximum to

zero in < 1 µs), the output capacitor must absorb all the

inductor's stored energy. This will cause a peak voltage on

the capacitor according to the following equation.

= 443 µF

OUT

Note that C_OUTis much smaller in this example, 443 µF

compared to 772 µF based on a worst-case load release. To

meet the two design criteria of minimum 443 µF and

maximum 15 m ESR, select two capacitors rated at 220 µF

and 15 m ESR or less.

It is recommended that an additional small capacitor be

placed in parallel with C_OUTin order to filter high frequency

switching noise.

1

2

)

L (I

+

x I

2

OUT

RIPPLEMAX

C

=

OUT_MIN

2

(V

)

- (V

)

OUT

PEAK

Stability Considerations

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-pulsing or

ESR loop instability.

Assuming a peak voltage V_PEAKof 1.150 (100 mV rise

upon load release), and a 6 A load release, the required

capacitance is shown by the next equation.

Double-pulsing occurs due to switching noise seen at the FB

input or because the FB ripple voltage is too low. This causes

the FB comparator to trigger prematurely after the minimum

off-time has expired. In extreme cases the noise can cause

three or more successive on-times. Double-pulsing will result

in higher ripple voltage at the output, but in most applications

it will not affect operation. This form of instability can usually

be avoided by providing the FB pin with a smooth, clean

ripple signal that is at least 10 mV_p-p, which may dictate the

need to increase the ESR of the output capacitors. It is also

imperative to provide a proper PCB layout as discussed in

the Layout Guidelines section.

1

2

1.5 µH (6 A + x 2.53)

C

=

OUT_MIN

2

(1.05) - (1 V)

= 772 µF

OUT_MIN

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 750 mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately - V_OUT

This causes a down-slope or falling dI/dt in the inductor. If the

.

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SiC414, SiC424

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Another way to eliminate doubling-pulsing is to add a small

(~ 10 pF) capacitor across the upper feedback resistor, as

shown in figure 12. This capacitor should be left unpopulated

unless it can be confirmed that double-pulsing exists.

Adding the C_TOPcapacitor will couple more ripple into FB to

help eliminate the problem. An optional connection on the

PCB should be available for this capacitor.

voltage across CL, analogous to the ramp voltage generated

across the ESR of a standard capacitor. This ramp is then

capacitive coupled into the FB pin via capacitor C_C.

C

TOP

To FB pin

V

R

1

OUT

R

2

Figure 13 - Virtual ESR Ramp Circuit

Figure 12 - Capacitor Coupling to FB Pin

Dropout Performance

The output voltage adjustment range for continuous

conduction operation is limited by the fixed 250 ns (typical)

minimum off-time of the one-shot. When working with low

input voltages, the duty-factor limit must be calculated using

worst-case values for on and off times.

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking

stability is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and ringing.

Ringing for more than one cycle after the initial step is an

indication that the ESR should be increased.

The duty-factor limitation is shown by the next equation.

t

ON(MIN)

DUTY =

t

x t

ON(MIN)

OFF(MAX)

One simple way to solve this problem is to add trace

resistance in the high current output path. A side effect of

adding trace resistance is a decrease in load regulation.

The inductor resistance and MOSFET on-state voltage drops

must be included when performing worst-case dropout

duty-factor calculations.

ESR Requirements

System DC Accuracy (V_OUTController)

A minimum ESR is required for two reasons. One reason

is to generate enough output ripple voltage to provide

10 mV_p-pat the FB pin (after the resistor divider) to avoid

double-pulsing.

Three factors affect V_OUTaccuracy: the trip point of the FB

error comparator, the ripple voltage variation with line and

load, and the external resistor tolerance. The error

comparator off set is trimmed so that under static conditions

it trips when the feedback pin is 750 mV, 1 %.

The on-time pulse from the SiC414 and SiC424 in the design

example is calculated to give a pseudo-fixed frequency of

250 kHz. Some frequency variation with line and load is

expected. This variation changes the output ripple voltage.

Because constant on-time converters regulate to the valley

of the output ripple, 1/2 of the output ripple appears as a DC

regulation error. For example, if the output ripple is 50 mV

with V_IN= 6 V, then the measured DC output will be 25 mV

above the comparator trip point. If the ripple increases to

80 mV with V_IN= 25 V, then the measured DC output will be

40 mV above the comparator trip. The best way to minimize

this effect is to minimize the output ripple.

The second reason is to prevent instability due to insufficient

ESR. The on-time control regulates the valley of the output

ripple voltage. This ripple voltage is the sum of the two

voltages. One is the ripple generated by the ESR, the other

is the ripple due to capacitive charging and discharging

during the switching cycle. For most applications, the total

output ripple voltage is dominated by the output capacitors,

typically SP or POSCAP devices. For stability the ESR zero

of the output capacitor should be lower than approximately

one-third the switching frequency. The formula for minimum

ESR is shown by the following equation.

3

ESR

=

MIN

2 x π x C

x f

SW

OUT

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of trace

resistance between the inductor and output capacitor. This

trace resistance should be optimized so that at full load the

output droops to near the lower regulation limit. Passive

Using Ceramic Output Capacitors

When applications use ceramic output capacitors, the ESR

is normally too small to meet the previously stated ESR

criteria. In these applications it is necessary to add a small

virtual ESR network composed of two capacitors and one

resistor, as shown in figure 12. This network creates a ramp

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

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SiC414, SiC424

Vishay Siliconix

droop minimizes the required output capacitance because

the voltage excursions due to load steps are reduced as

seen at the load.

Switching Frequency Variations

The switching frequency will vary depending on line and load

conditions. The line variations are a result of fixed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

V_INincreases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net effect is that

frequency tends to falls slightly with increasing input voltage

inductor. An adaptive on-time converter must also

compensate for the same losses by increasing the effective

duty cycle (more time is spent drawing energy from V_INas

losses increase). The on-time is essentially constant for a

given V_OUT/V_INcombination, to offset the losses the off-time

will tend to reduce slightly as load increases. The net effect

is that switching frequency increases slightly with increasing

load.

The use of 1 % feedback resistors may result in up to an

additional 1 % error. If tighter DC accuracy is required,

resistors with lower tolerances should be used.

The output inductor value may change with current. This will

change the output ripple and therefore will have a minor

effect on the DC output voltage. The output ESR also affects

the output ripple and thus has a minor effect on the DC

output voltage.

BILL OF MATERIALS

Qty.

Ref. Designator

Description

Value Voltage

Footprint

Part Number

Manufacturer

SiC424 COT Buck

Converter

1

U1

MLPQ-28 4 x 4 mm

SiC424

Vishay

4

1

C16, C18, C17, C23

220 µF, 10 V D

220 µF

10 µF

1 µH

10 V

16 V

SM593D

SM1206

IHLP2525

SO-8

593D227X0010E2TE3

GRM31CR71C106KAC7L

IHLP2525EZER1R0M01

Si4812BDY

Vishay

Murata

Vishay

C15, C20, C21, C22 10 µF, 16 V, X7R.B, 1206

L1

1 µH

Q1

Si4812BDY-E3

C1, C2, C3, C4,

C29

5

CAP. 22 µF, 16 V, 1210

22 µF

16 V

SM1210

GRM32ER71C226ME18L

Murata

3

1

2

1

2

3

C8, C9, C10

C26

CAP. 10 µF, 25 V, 1210

4.7 µF, 10 V, 0805

10 µF

25 V

10 V

35 V

200 V

50 V

SM1210

SM0805

Radial

TMK325B7106MM-T

LMK212B7475KG-T

EU-FM1V151

Taiyo Yuden

Panasonic

Vishay

4.7 µF

C12

CAP. Radial 150 µF, 35 V 150 µF

R4

1 , 2512

Res. 0 

1 

0 

1K

SM2512

SM0603

SM0402

SM0603

CRCW25121R00FKEG

CRCW0603 0000ZOEA

CRCW04020000ZOED

CRCW04021K00FKED

CRCW0603 100K FKEA

CRCW060310KFKED

R7, R11

R39

Vishay

0R, 50 V, 0402

Res. 1K, 50 V, 0402

Res. 100K, 0603

Res. 10K, 50 V, 0603

Vishay

R3

Vishay

R5, R6

R8, R10, R15

100K

10K

Vishay

CAP. CER 1 µF, 35 V, X7R

0805

1

C6

1 µF

35 V

50 V

SM0805

SM0603

GMK212B7105KG-T

Murata

Vishay

Res. 16.5 k 1/10 W, 1%,

R23

16.5K

CRCW060316K5FKEA

0603 SMD

1

R13

C30

Res. 1K, 50 V, 0402

CAP. 180 pF, 0402

1K

50 V

SM0402

CRCW04021K00FKED

VJ0402A181JXACW1BC

Vishay

180 pF

Res. 78.7 k 1/10 W, 1 %,

1

R30

78.7k

50 V

SM0603

CRCW060378K7FKEA

Vishay

0603 SMD

4

1

4

1

C7, C11, C14, C28

CAP. 0.1 µF, 50 V, 0603

CAP. 0.1 µF, 10 V, 0402

Solder Banana

0.1 µF

50 V

10 V

SM0603

SM0402

VJ0603Y104KXACW1BC

VJ0402Y104MXQCW1BC

575-6

Vishay

C5

B1, B2, B3, B4

C13

Keystone

Vishay

CAP. 0.01 µF, 50 V, 0402 0.01 µF

50 V

SM0402

Terminal

VJ0402Y103KXACW1BC

P1, P2, P3, P4, P5,

P6, P7, P8, P9,

P10, P11, P12

12

4

Probe Hook

0

Keystone

M1, M2, M3, M4

Nylon on Stand off

8834

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This document is subject to change without notice.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

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SiC414, SiC424

Vishay Siliconix

PCB LAYOUT OF THE EVALUATION BOARD

Figure 14. Top Layer

Figure 15. Mid Layer1

Figure 16. Mid Layer2

Figure 17. Bottom Layer

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

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SiC414, SiC424

Vishay Siliconix

PACKAGE DIMENSIONS AND MARKING INFO

5

6

PIN 1 Dot by

2x

K1

Marking

0.10 C A

D

PIN 1 Identiﬁcation

A

D2-3

D2-1

2x

0.10 C B

1

2

3

e

E2-2

28L T/SLP

(4.0 mm x 4.0 mm)

E

(Ne-1)X e

Ref.

K2

E2-1

0.4000

b

E2-3

B

L

D2-2

Top View

Notes:

(Nd-1)X e

Ref.

1. Use millimeters as the primary measurement.

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.

3. N is the number of terminals.

Bottom View

Nd is the number of terminals in X-direction and

Ne is the number of terminals in Y-direction.

4. Dimensions b applies to plated terminal and is measured

between 0.15 mm and 0.30 mm from terminal tip.

5. The pin #1 identiﬁer must be existed on the top surface of the

package by using identiﬁcation mark or other feature of package body.

6. Exact shape and size of this feature is optional.

7. Package warpage max. 0.08 mm.

C

A

0.08

C

0.000-0.0500

0.2030 Ref.

Side View

8. Applied only for terminals.

Millimeters

Dimensions

Inches

Nom.

Min.

0.70

0.00

Nom.

0.75

Max.

Min.

0.027

0.000

Max.

A⁽⁸⁾

A1

0.80

0.05

0.029

0.031

0.002

-

A2

b⁽⁴⁾

0.20 Ref.

0.225

4.00 BSC

0.45 BSC

4.00 BSC

0.40

0.008 Ref.

0.009

0.175

0.275

0.50

0.007

0.011

0.020

D

0.157 BSC

0.018 BSC

0.157 BSC

0.016

e

E

L

0.30

0.012

N⁽³⁾

Nd⁽³⁾

Ne⁽³⁾

D2-1

D2-2

D2-3

E2-1

E2-2

E2-3

K1

28

7

0.912

0.908

2.43

1.062

1.058

2.58

1.162

1.158

2.68

0.036

0.096

0.051

0.023

0.042

0.046

0.105

0.061

0.033

0.042

0.102

1.30

1.45

1.55

0.057

0.58

0.73

0.83

0.029

0.46 BSC

0.40 BSC

0.018 BSC

0.016 BSC

K2

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For technical questions, contact: powerictechsupport@vishay.com

This document is subject to change without notice.

Document Number: 63388

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SiC414, SiC424

Vishay Siliconix

RECOMMENDED LAND PATTERN

Dimensions

Millimeters

(3.95)

3.20

1.29

C

G

H

K

X

2.58

H1

H2

K

0.73

1.45

1.29

H2

1.06

G

Y

(C)

Z

H

P

0.45

X

0.30

H1

Y

0.75

Z

4.70

P

K

2.58

Notes:

a. Controlling dimensions are in millimeters (angles in degrees).

b. This land pattern is for reference purposes only. Consult your manufacturing group to ensure your company’s manufacturing guidelines

are met.

c. Square package-dimensions apply in both X and Y directions.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?63388.

Document Number: 63388

S13-0248-Rev. B, 04-Feb-13

For technical questions, contact: powerictechsupport@vishay.com

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information

Vishay Siliconix

PowerPAK^®MLP44-28L CASE OUTLINE

5

6

PIN 1 Dot by

2x

K1

Marking

0.10 C A

PIN#1 Identiﬁcation

R0.20

D

A

D2-3

D2-1

2x

0.10 C B

1

2

e

E2-2

3

28L T/SLP

(4.0 mm x 4.0 mm)

E

(Ne-1)X e

Ref.

K2

E2-1

0.4000

b

E2-3

B

L

D2-2

Top View

Notes:

(Nd-1)X e

Ref.

1. Use millimeters as the primary measurement.

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.

3. N is the number of terminals.

Bottom View

Nd is the number of terminals in X-direction and

Ne is the number of terminals in Y-direction.

4. Dimensions b applies to plated terminal and is measured

between 0.15 mm and 0.30 mm from terminal tip.

5. The pin #1 identiﬁer must be existed on the top surface of the

package by using identiﬁcation mark or other feature of package body.

6. Exact shape and size of this feature is optional.

7. Package warpage max. 0.08 mm.

C

A

0.08 C

0.000-0.0500

0.2030 Ref.

Side View

8. Applied only for terminals.

MILLIMETERS

INCHES

NOM.

0.029

DIM.

A ⁽⁸⁾

A1

MIN.

0.70

0.00

NOM.

0.75

MAX.

0.80

MIN.

0.027

0.000

MAX.

0.031

0.002

-

0.05

-

A2

b ⁽⁴⁾

0.20 REF

0.225

4.00 BSC

0.45 BSC

4.00 BSC

0.40

0.008 REF

0.009

0.175

0.275

0.50

0.007

0.011

D

0.157 BSC

0.018 BSC

0.157 BSC

0.016

e

E

L

0.30

0.012

0.020

N ⁽³⁾

Nd ⁽³⁾

Ne ⁽³⁾

D2-1

D2-2

D2-3

E2-1

E2-2

E2-3

K1

28

7

0.908

0.912

2.43

1.058

1.062

2.58

1.158

1.162

2.68

0.036

0.096

0.051

0.023

0.042

0.046

0.105

0.061

0.033

0.042

0.102

1.30

1.45

1.55

0.057

0.58

0.73

0.83

0.029

0.46 BSC

0.40 BSC

0.018 BSC

0.016 BSC

K2

ECN: T10-0056-Rev. A, 22-Feb-10

DWG: 5996

Document Number: 65739

Revision: 22-Feb-10

www.vishay.com

1

PAD Pattern

Vishay Siliconix

PowerPAK^®MLP44-28L Land Pattern

Recommended Land Pattern

1.29

0.30

1.06

1

2

3

0.45

2.58

1.06

Recommended Land Pattern vs. Case Outline

0.30

0.06

1

2

3

Document Number: 70567

Revision: 17-May-10

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1

Legal Disclaimer Notice

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Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE

RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,

“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other

disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or

the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all

liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,

consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular

purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical

requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements

about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular

product with the properties described in the product specification is suitable for use in a particular application. Parameters

provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All

operating parameters, including typical parameters, must be validated for each customer application by the customer’s

technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,

including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining

applications or for any other application in which the failure of the Vishay product could result in personal injury or death.

Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please

contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by

any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the

definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council

of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment

(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that

all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free

requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference

to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21

conform to JEDEC JS709A standards.

Revision: 02-Oct-12

Document Number: 91000

1


型号：	CRCW06030000ZOEA
厂家：	VISHAY
描述：	6 A, microBUCK SiC414, SiC424 Integrated Buck Regulator with 5 V LDO 6 A， microBUCK SiC414 ， SiC424集成降压稳压器采用5 V LDO 稳压器
文件：	总24页 (文件大小：1226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CRCW06030000ZOEA [VISHAY]

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