IRFS11N50ATRLPA [VISHAY]

Power MOSFET;


型号：	IRFS11N50ATRLPA
厂家：	VISHAY
描述：	Power MOSFET
文件：	总10页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

Power MOSFET

FEATURES

• Low Gate Charge Q_gresults in Simple Drive

Requirement

• Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

PRODUCT SUMMARY

V_DS(V)

_DS(on)()

Q_g(Max.) (nC)

500

V_GS= 10 V

0.52

Available

_gs(nC)

_gd(nC)

• Fully

Characterized

Capacitance

and

Avalanche Voltage and Current

• Effective C_ossSpecified

Configuration

Single

• Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

Note

D²PAK (TO-263)

This datasheet provides information about parts that are

RoHS-compliant and/or parts that are non-RoHS-compliant. For

example, parts with lead (Pb) terminations are not RoHS-compliant.

Please see the information/tables in this datasheet for details.



APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

• High Speed Power Switching

N-Channel MOSFET

TYPICAL SMPS TOPOLOGIES

• Two Transistor Forward

• Half and Full Bridge

• Power Factor Correction Boost

ORDERING INFORMATION

Package

D²PAK (TO-263)

SiHFS11N50A-GE3

IRFS11N50APbF

D²PAK (TO-263)

SiHFS11N50ATRR-GE3^a

IRFS11N50ATRRP^a

D²PAK (TO-263)

SiHFS11N50ATRL-GE3^a

IRFS11N50ATRLP^a

Lead (Pb)-free and Halogen-free

Lead (Pb)-free

Note

a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (T_C= 25 °C, unless otherwise noted)

PARAMETER

SYMBOL

LIMIT

UNIT

500

Drain-Source Voltage

Gate-Source Voltage

V_DS

V_GS

_C= 25 °C

Continuous Drain Current

V_GSat 10 V

I_D

7.0

T_C= 100 °C

Pulsed Drain Current^a

I_DM

1.3

Linear Derating Factor

W/°C

Single Pulse Avalanche Energy^b

Repetitive Avalanche Current^a

Repetitive Avalanche Energy^a

E_AS

I_AR

275

170

E_AR

Maximum Power Dissipation

_C= 25 °C

P_D

Peak Diode Recovery dV/dt^c

dV/dt

T_J, T_stg

V/ns

6.9

- 55 to + 150

300

Operating Junction and Storage Temperature Range

Soldering Recommendations (Peak Temperature)^d

°C

for 10 s

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Starting T_J= 25 °C, L = 4.5 mH, R_g= 25 , I_AS= 11 A (see fig. 12).

c. I_SD 11 A, dI/dt  140 A/μs, V_DD V_DS, T_J 150 °C.

d. 1.6 mm from case.

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER

SYMBOL

TYP.

MAX.

0.75

UNIT

Maximum Junction-to-Case (Drain)

Case-to-Sink, Flat, Greased Surface

Maximum Junction-to-Ambient

R_thJC

R_thCS

R_thJA

0.50

°C/W

SPECIFICATIONS (T_J= 25 °C, unless otherwise noted)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX. UNIT

Static

Drain-Source Breakdown Voltage

V_DSTemperature Coefficient

Gate-Source Threshold Voltage

Gate-Source Leakage

V_DS

V_DS/T_J

V_GS(th)

I_GSS

V_GS= 0, I_D= 250 μA

Reference to 25 °C, I_D= 1 mA

V_DS= V_GS, I_D= 250 μA

500

V/°C

2.0

0.060

4.0

100

250

0.52

V_GS

V_DS= 500 V, V_GS= 0 V

V_DS= 400 V, V_GS= 0 V, T_J= 125 °C

V_GS= 10 V

I_D= 6.6 A^b

30 V

Zero Gate Voltage Drain Current

I_DSS

μA

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

R_DS(on)

g_fs



V_DS= 50 V, I_D= 6.6 A

6.1

Input Capacitance

C_iss

V_GS= 0 V,

V_DS= 25 V,

1423

208

Output Capacitance

C_oss

Reverse Transfer Capacitance

C_rss

8.1

f = 1.0 MHz, see fig. 5

V_DS= 1.0 V, f = 1.0 MHz

2000

Output Capacitance

C_oss

V_GS= 0 V

_DS= 400 V, f = 1.0 MHz

V_DS= 0 V to 400 V^c

Effective Output Capacitance

Total Gate Charge

_osseff.

Q_g

I_D= 11 A, V_DS= 400 V

see fig. 6 and 13^b

Gate-Source Charge

Gate-Drain Charge

Q_gs

Q_gd

V_GS= 10 V

Turn-On Delay Time

Rise Time

t_d(on)

t_r

t_d(off)

t_f

V_DD= 250 V, I_D= 11 A

R_g= 9.1 , R_D= 22

Turn-Off Delay Time

Fall Time

see fig. 10^b

Drain-Source Body Diode Characteristics

MOSFET symbol

Continuous Source-Drain Diode Current

I_S

showing the 

integral reverse

p - n junction diode

Pulsed Diode Forward Current^a

I_SM

Body Diode Voltage

V_SD

t_rr

T_J= 25 °C, I_S= 11 A, V_GS= 0 V^b

1.5

770

5.1

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

510

3.4

μC

T_J= 25 °C, I_F= 11 A, dI/dt = 100 A/μs^b

Q_rr

Forward Turn-On Time

t_on

Intrinsic turn-on time is negligible (turn-on is dominated by L_Sand L_D)

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width  300 μs; duty cycle  2 %.

c. C_osseff. is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising fom 0 % V_DSto 80 % V_DS

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 8 - Maximum Safe Operating Area

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

R_D

V_DS

V_GS

D.U.T.

R_g

10 V

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

V_DS

90 %

10 %

V_GS

t_d(on)t_r

t_d(off)t_f

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

V_DS

15 V

t_p

Driver

V_DS

R_g

D.U.T.

I_AS

20 V

0.01 Ω

t_p

Fig. 12b - Unclamped Inductive Waveforms

Fig. 12a - Unclamped Inductive Test Circuit

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Typical Drain-to-Source Voltage

vs. Avalanche Current

Current regulator

Same type as D.U.T.

50 kΩ

12 V

0.2 µF

Q_G

0.3 µF

V_GS

V_DS

Q_GS

Q_GD

D.U.T.

V_GS

V_G

3 mA

I_G

I_D

Charge

Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform

Fig. 13b - Gate Charge Test Circuit

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFS11N50A, SiHFS11N50A

www.vishay.com

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations

• Low stray inductance

• Ground plane

D.U.T.

• Low leakage inductance

current transformer

R_g

• dV/dt controlled by R_g

• Driver same type as D.U.T.

• I_SDcontrolled by duty factor “D”

• D.U.T. - device under test

V_DD

Driver gate drive

P.W.

D =

Period

_GS= 10 V^a

D.U.T. l_SDwaveform

D.U.T. V_DSwaveform

Reverse

recovery

current

Body diode forward

current

dI/dt

Diode recovery

dV/dt

V_DD

Re-applied

voltage

Body diode forward drop

Inductor current

I_SD

Ripple ≤ 5 %

Note

a. V_GS= 5 V for logic level devices

Fig. 14 - For N-Channel



Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91286.

S13-1927-Rev. E, 09-Sep-13

Document Number: 91286

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information

Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

(Datum A)

Gauge

plane

0° to 8°

Detail A

Seating plane

Detail “A”

Rotated 90° CW

scale 8:1

2 x b2

2 x b

0.010

0.004

2 x e

Base

metal

Plating

(c)

b1, b3

(b, b2)

Lead tip

Section B - B and C - C

Scale: none

View A - A

MILLIMETERS

INCHES

MILLIMETERS

INCHES

DIM.

MIN.

4.06

0.00

0.51

1.14

0.38

1.14

8.38

MAX.

4.83

0.25

0.99

0.89

1.78

1.73

0.74

0.58

1.65

9.65

MIN.

0.160

0.000

0.020

0.045

0.015

0.045

0.330

MAX.

0.190

0.010

0.039

0.035

0.070

0.068

0.029

0.023

0.065

0.380

DIM.

MIN.

6.86

MAX.

MIN.

MAX.

10.67

0.270

0.380

0.245

0.420

9.65

6.22

2.54 BSC

0.100 BSC

14.61

15.88

2.79

1.65

1.78

0.575

0.625

0.110

0.066

0.070

1.78

0.070

0.25 BSC

0.010 BSC

4.78

5.28

0.188

0.208

ECN: S-82110-Rev. A, 15-Sep-08

DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the

outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364

Revision: 15-Sep-08

www.vishay.com

AN826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR D PAK: 3-Lead

0.420

(10.668)

0.145

(3.683)

0.135

(3.429)

0.200

0.050

(5.080)

(1.257)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index

Document Number: 73397

11-Apr-05

www.vishay.com

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Revision: 01-Jan-2022

Document Number: 91000

IRFS11N50ATRLPA [VISHAY]

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