IRLD024 [VISHAY]

Power MOSFET; 功率MOSFET


型号：	IRLD024
厂家：	VISHAY
描述：	Power MOSFET 功率MOSFET
文件：	总8页 (文件大小：1593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRLD024, SiHLD024

Vishay Siliconix

Power MOSFET

FEATURES

• Dynamic dV/dt Rating

PRODUCT SUMMARY

V_DS(V)

Available

• For Automatic Insertion

• End Stackable

_DS(on)(Ω)

V_GS= 5.0 V

0.10

RoHS*

Q_g(Max.) (nC)

4.5

COMPLIANT

• Logic-Level Gate Drive

• R_DS(on)Specified at V_GS= 4 V and 5 V

• 175 °C Operating Temperature

• Fast Switching

_gs(nC)

_gd(nC)

Configuration

Single

• Lead (Pb)-free Available

HEXDIP

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effectiveness.

The 4 pin DIP package is a low cost machine-insertiable

case style which can be stacked in multiple combinations on

standard 0.1" pin centers. The dual drain servers as a

thermal link to the mounting surface for power dissipation

levels up to 1 W.

N-Channel MOSFET

ORDERING INFORMATION

Package

HEXDIP

IRLD024PbF

SiHLD024-E3

IRLD024

Lead (Pb)-free

SnPb

SiHLD024

ABSOLUTE MAXIMUM RATINGS T_C= 25 °C, unless otherwise noted

PARAMETER

SYMBOL

LIMIT

UNIT

Drain-Source Voltage

Gate-Source Voltage

V_DS

V_GS

T_C= 25 °C

T_C=100°C

2.5

Continuous Drain Current

V_GSat 5.0 V

I_D

1.8

Pulsed Drain Current^a

I_DM

Linear Derating Factor

0.0083

W/°C

Single Pulse Avalanche Energy^b

Maximum Power Dissipation

E_AS

P_D

_C= 25 °C

1.3

Peak Diode Recovery dV/dt^c

dV/dt

T_J, T_stg

4.5

V/ns

Operating Junction and Storage Temperature Range

Soldering Recommendations (Peak Temperature)

- 55 to + 175

300^d

°C

for 10 s

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. V_DD= 25 V, starting T_J= 25 °C, L = 16 mH, R_G= 25 Ω, I_AS= 2.5 A (see fig. 12).

c. I_SD≤ 17 A, dI/dt ≤ 140 A/µs, V_DD≤ V_DS, T_J≤ 175 °C.

d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

www.vishay.com

IRLD024, SiHLD024

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER

SYMBOL

TYP.

MAX.

UNIT

Maximum Junction-to-Ambient

R_thJA

120

°C/W

SPECIFICATIONS T_J= 25 °C, unless otherwise noted

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Static

Drain-Source Breakdown Voltage

V_DS

ΔV_DS/T_J

V_GS(th)

I_GSS

V_GS= 0 V, I_D= 250 µA

Reference to 25 °C, I_D= 1 mA

V_DS= V_GS, I_D= 250 µA

V/°C

_DSTemperature Coefficient

0.060

Gate-Source Threshold Voltage

Gate-Source Leakage

1.0

2.0

100

V_GS

V_DS= 60 V, V_GS= 0 V

_DS= 48 V, V_GS= 0 V, T_J= 150 °C

10 V

Zero Gate Voltage Drain Current

Drain-Source On-State Resistance

I_DSS

µA

250

0.10

0.14

V_GS= 5.0 V

V_GS= 4.0 V

I_D= 1.5A^b

I_D= 1.3 A^b

R_DS(on)

g_fs

Forward Transconductance

Dynamic

V_DS= 25 V, I_D= 1.5 A^b

3.7

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Turn-On Delay Time

Rise Time

C_iss

C_oss

C_rss

Q_g

870

360

V_GS= 0 V

_DS= 25 V

f = 1.0 MHz, see fig. 5

4.5

I_D= 17 A, V_DS= 48 V

see fig. 6 and 13^b

Q_gs

Q_gd

t_d(on)

t_r

_GS= 5.0 V

110

_DD= 30 V, I_D= 17 A

Turn-Off Delay Time

Fall Time

t_d(off)

t_f

_G= 9.0 Ω, R_D= 1.7 Ω, see fig. 10^b

Between lead,

Internal Drain Inductance

L_D

L_S

4.0

6.0

6 mm (0.25") from

package and center of

die contact

Internal Source Inductance

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

MOSFET symbol

showing the

integral reverse

p - n junction diode

I_S

2.5

Pulsed Diode Forward Current^a

I_SM

Body Diode Voltage

V_SD

t_rr

T_J= 25 °C, I_S= 2.5 A, V_GS= 0 V^b

1.5

260

1.5

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Forward Turn-On Time

110

0.49

µC

T_J= 25 °C, I_F= 17 A, dI/dt = 100 A/µs^b

Q_rr

t_on

Intrinsic turn-on time is negligible (turn-on is dominated by L_Sand L_D)

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.

www.vishay.com

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

IRLD024, SiHLD024

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Fig. 1 - Typical Output Characteristics, T_C= 25 °C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Fig. 2 - Typical Output Characteristics, T_C= 175 °C

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

www.vishay.com

IRLD024, SiHLD024

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

www.vishay.com

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

IRLD024, SiHLD024

Vishay Siliconix

R_D

V_DS

V_GS

D.U.T.

R_G

5.0 V

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

V_DS

90 %

10 %

V_GS

t_d(on)t_r

t_d(off)t_f

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

www.vishay.com

IRLD024, SiHLD024

Vishay Siliconix

V_DS

Vary t_pto obtain

required I_AS

t_p

V_DD

D.U.T.

I_AS

R_G

V_DD

V_DS

5.0 V

0.01 Ω

t_p

I_AS

Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator

Same type as D.U.T.

50 kΩ

Q_G

5.0 V

12 V

0.2 µF

0.3 µF

Q_GS

Q_GD

V_DS

D.U.T.

V_G

V_GS

3 mA

Charge

I_G

I_D

Current sampling resistors

Fig. 13b - Gate Charge Test Circuit

Fig. 13a - Basic Gate Charge Waveform

www.vishay.com

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

IRLD024, SiHLD024

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations

• Low stray inductance

• Ground plane

D.U.T.

• Low leakage inductance

current transformer

R_G

• dV/dt controlled by R_G

• I_SDcontrolled by duty factor "D"

• D.U.T. - device under test

V_DD

Driver gate drive

P.W.

Period

D =

= 10 V*

D.U.T. I waveform

Reverse

recovery

current

Body diode forward

current

dI/dt

D.U.T. V waveform

Diode recovery

dV/dt

Re-applied

voltage

Body diode

forward drop

Inductor current

Ripple ≤ 5 %

* V_GS= 5 V for logic level devices and 3 V drive devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see http://www.vishay.com/ppg?91308.

Document Number: 91308

S-81378-Rev. A, 07-Jul-08

www.vishay.com

Legal Disclaimer Notice

Vishay

Disclaimer

All product specifications and data are subject to change without notice.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf

(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein

or in any other disclosure relating to any product.

Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any

information provided herein to the maximum extent permitted by law. The product specifications do not expand or

otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed

therein, which apply to these products.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this

document or by any conduct of Vishay.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless

otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such

applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting

from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding

products designed for such applications.

Product names and markings noted herein may be trademarks of their respective owners.

Document Number: 91000

Revision: 18-Jul-08

www.vishay.com

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