SI3417DV-T1-GE3 [VISHAY]
Small Signal Field-Effect Transistor, 8A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, MO-193AA, HALOGEN FREE AND ROHS COMPLIANT, MO-193C, TSOP-6;
| 型号： | SI3417DV-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Small Signal Field-Effect Transistor, 8A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, MO-193AA, HALOGEN FREE AND ROHS COMPLIANT, MO-193C, TSOP-6 开关 光电二极管 晶体管 |
| 文件： | 总11页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3417DV
Vishay Siliconix
P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
•
•
TrenchFET® Power MOSFET
VDS (V)
RDS(on) () Max.
Qg (Typ.)
I
D (A)d,e
100 % Rg and UIS Tested
Material categorization:
0.0252 at VGS = - 10 V
0.0360 at VGS = - 4.5 V
- 8
- 8
- 30
15 nC
For definitions of compliance please see
www.vishay.com/doc?99912
Available
TSOP-6
Top View
APPLICATIONS
•
•
•
•
Load Switches
Adaptor Switch
DC/DC Converter
For Mobile Computing/Consumer
D
D
D
S
1
2
3
6
5
S
3 mm
D
G
G
4
Marking Code
BH XX
2.85 mm
Lot Traceability
and Date Code
D
Part # Code
Ordering Information:
Si3417DV-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)
A
Parameter
Symbol
VDS
Limit
- 30
Unit
Drain-Source Voltage
Gate-Source Voltage
V
VGS
20
- 8e
- 8e
- 7.3a, b
- 5.8a, b
- 50
T
C = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Continuous Drain Current (TJ = 150 °C)
ID
A
IDM
IS
Pulsed Drain Current (t = 100 µs)
T
C = 25 °C
A = 25 °C
- 3.5
- 1.7a, b
- 20
Continuous Source-Drain Diode Current
T
IAS
Avalanche Current
L = 0.1 mH
EAS
Single-Pulse Avalanche Energy
20
mJ
W
T
T
T
C = 25 °C
C = 70 °C
A = 25 °C
4.2
2.7
PD
Maximum Power Dissipation
2a, b
1.3a, b
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
RthJA
RthJF
Typical
40
Maximum
Unit
Maximum Junction-to-Ambienta, c
t 10 s
Steady State
62.5
30
°C/W
Maximum Junction-to-Foot
25
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 110 °C/W.
d. Based on TC = 25 °C.
e. Package limited.
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
1
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si3417DV
Vishay Siliconix
SPECIFICATIONS (T = 25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
VGS = 0 V, ID = - 250 µA
ID = - 250 µA
Drain-Source Breakdown Voltage
- 30
V
V
DS Temperature Coefficient
- 31
4.5
mV/°C
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS = VGS, ID = - 250 µA
- 1
- 3
V
IGSS
VDS = 0 V, VGS
=
20 V
100
- 1
nA
VDS = - 30 V, VGS = 0 V
IDSS
ID(on)
RDS(on)
gfs
Zero Gate Voltage Drain Current
On-State Drain Currenta
µA
A
VDS = - 30 V, VGS = 0 V, TJ = 55 °C
- 5
VDS - 10 V, VGS = - 10 V
VGS = - 10 V, ID = - 7.3 A
- 30
0.0210
0.0300
23
0.0252
0.0360
Drain-Source On-State Resistancea
S
V
GS = - 4.5 V, ID = - 6.1 A
Forward Transconductancea
Dynamicb
VDS = - 10 V, ID = - 7.3 A
Ciss
Coss
Crss
Input Capacitance
1350
215
185
32
15
4
VDS = - 15 V, VGS = 0 V, f = 1 MHz
DS = - 15 V, VGS = - 10 V, ID = - 7.3 A
DS = - 15 V, VGS = - 4.5 V, ID = - 7.3 A
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
pF
V
V
50
25
Qg
Total Gate Charge
nC
Qgs
Qgd
Rg
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
7.5
5.8
10
8
1.2
11.6
15
15
70
25
70
60
70
30
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
V
DD = - 15 V, RL = 2.6
ID - 5.8 A, VGEN = - 10 V, Rg = 1
Turn-Off DelayTime
Fall Time
45
12
42
35
40
16
ns
Turn-On Delay Time
Rise Time
V
DD = - 15 V, RL = 2.6
ID - 5.8 A, VGEN = - 4.5 V, Rg = 1
Turn-Off DelayTime
Fall Time
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current
Pulse Diode Forward Current (t = 100 µs)
Body Diode Voltage
IS
ISM
VSD
trr
TC = 25 °C
- 3.5
- 50
- 1.2
60
A
IS = - 5.8 A, VGS = 0 V
- 0.75
34
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
ns
nC
Qrr
ta
22
40
IF = - 5.8 A, dI/dt = 100 A/µs,
TJ = 25 °C
11
ns
Reverse Recovery Rise Time
tb
23
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si3417DV
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
50
40
30
20
10
0
5
4
3
2
1
0
V
GS
= 10 V thru 5 V
TC = 25 °C
V
= 4 V
GS
TC = 125 °C
TC = - 55 °C
V
= 3 V
GS
0
1
2
3
4
0.0
0.5
1.0
1.5
2.0
VGS - Gate-to-Source Voltage (V)
V
DS
- Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.042
0.036
0.030
0.024
0.018
0.012
2400
1800
1200
600
0
VGS = 4.5 V
C
iss
V
GS = 10 V
C
oss
C
rss
0
10
20
30
40
50
0
6
12
18
24
30
ID - Drain Current (A)
V
- Drain-to-Source Voltage (V)
DS
On-Resistance vs. Drain Current
Capacitance
10
8
1.8
1.5
1.2
0.9
0.6
I
= 7.3 A
D
I
= 7.3 A
D
V
= 10 V
GS
V
DS
= 15 V
6
V
DS
= 7.5 V
V
= 22.5 V
DS
4
2
V
= 4.5 V
GS
0
0
0
9
18
27
36
- 50 - 25
25
50
75
100 125 150
T
J
- Junction Temperature (°C)
Q
- Total Gate Charge (nC)
g
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
3
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si3417DV
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
10
1
0.060
0.045
0.030
0.015
0.000
ID = 7.3A
T
J
= 150 °C
T
= 25 °C
J
TJ = 125 °C
TJ = 25 °C
0.1
0.01
T
J
= - 50 °C
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
4
6
8
10
V
- Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
SD
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
50
40
30
20
0.6
0.4
I
= 250 µA
D
0.2
I
= 1 mA
D
0.0
10
0
- 0.2
-3
-2
10
-1
10
- 50 - 25
0
25
50
75
100 125 150
10
1
10
100
600
Time (s)
T
J
- Temperature (°C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)
*
100 μs
10
1 ms
1
10 ms
100 ms
0.1
10s, 1 s
DC,
TA = 25 °C
Single Pulse
BVDSS Limited
10
0.01
0.1
1
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
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For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si3417DV
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
12
9
6
3
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating*
5
4
3
2
1
0
1.4
1.1
0.7
0.4
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Foot
Power Derating, Junction-to-Ambient
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
5
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si3417DV
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 90 °C/W
thJA
(t)
3. T
JM
-
T
A
= P
Z
DM thJA
4. Surface Mounted
Single Pulse
0.01
-
10
4
-
3
-
2
-1
10
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-
10
4
-
3
-
2
- 1
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62890.
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6
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62890
S13-1815-Rev. A, 12-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
5
4
3
6
1
4
E
1
E
E
1
E
1
2
2
3
-B-
-B-
e
e
b
b
M
M
C
0.15
C
B
A
0.15
B A
5-LEAD TSOP
6-LEAD TSOP
4x
1
-A-
D
0.17 Ref
c
R
R
A
2
A
L
2
Gauge Plane
Seating Plane
Seating Plane
L
0.08
C
A
1
-C-
(L )
1
4x
1
MILLIMETERS
INCHES
Dim
A
A1
A2
b
c
D
E
E1
e
Min
Nom
-
Max
Min
0.036
0.0004
0.035
0.012
0.004
0.116
0.106
0.061
Nom
-
Max
0.91
0.01
0.90
0.30
0.10
2.95
2.70
1.55
1.10
0.10
1.00
0.45
0.20
3.10
2.98
1.70
0.043
0.004
0.039
0.018
0.008
0.122
0.117
0.067
-
-
-
0.32
0.15
3.05
2.85
1.65
0.95 BSC
1.90
-
0.038
0.013
0.006
0.120
0.112
0.065
0.0374 BSC
0.075
-
1.80
2.00
0.50
0.071
0.012
0.079
0.020
e1
L
0.32
0.60 Ref
0.25 BSC
-
0.024 Ref
0.010 BSC
-
L1
L2
R
0.10
0
-
0.004
0
-
4
8
4
8
7
Nom
7 Nom
1
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
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1
AN823
Vishay Siliconix
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
Ramp-Up Rate
+6_C/Second Maximum
120 Seconds Maximum
70 − 180 Seconds
240 +5/−0_C
0.074
1.875
Temperature @ 155 " 15_C
Temperature Above 180_C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
0.014
0.35
0.122
3.1
0.026
0.65
20 − 40 Seconds
+6_C/Second Maximum
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 2. Solder Reflow Temperature Profile
FIGURE 1. Recommended Copper Spreading Footprint
Document Number: 71743
27-Feb-04
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1
AN823
Vishay Siliconix
10 s (max)
255 − 260_C
1X4_C/s (max)
3-6_C/s (max)
217_C
140 − 170_C
60 s (max)
3_C/s (max)
60-120 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
THERMAL PERFORMANCE
On-Resistance vs. Junction Temperature
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
1.6
1.4
1.2
1.0
0.8
0.6
V
= 4.5 V
GS
I
D
= 6.1 A
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rq
30_C/W
jf
−50 −25
0
25
50
75
100 125 150
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
T
− Junction Temperature (_C)
J
FIGURE 4. Si3434DV
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
Document Number: 71743
27-Feb-04
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2
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.099
(2.510)
0.039
0.020
0.019
(1.001)
(0.508)
(0.493)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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26
Document Number: 72610
Revision: 21-Jan-08
Legal Disclaimer Notice
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Disclaimer
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
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