SI3909DV [VISHAY]
Dual P-Channel 20-V (D-S) MOSFET; 双P通道20 - V（D -S）的MOSFET
| 型号： | SI3909DV |
| 厂家： | 
VISHAY |
| 描述： | Dual P-Channel 20-V (D-S) MOSFET |
| 文件： | 总3页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Vishay Siliconix
Dual P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 71511
S-50836 Rev. B, 16-May-05
1
SPICE Device Model Si3909DV
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.1
14
V
A
V
DS = VGS, ID = − 250 µA
VDS = −5 V, VGS = −4.5 V
0.18
0.19
0.25
3.6
0.16
0.19
0.28
3.6
VGS = −4.5 V, ID = − 1.8 A
VGS = −3.6 V, ID = −1.6 A
VGS = −2.5 V, ID = −1 A
Drain-Source On-State Resistancea
rDS(on)
Ω
Forward Transconductancea
Diode Forward Voltagea
gfs
S
V
VDS = −10 V, ID = −1.8 A
VSD
I
S = −1.05 A, VGS = 0 V
−0.78
−0.83
Dynamicb
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
2.5
0.40
0.60
10
2.7
0.40
0.60
11
nC
ns
V
DS = −10 V, VGS = −4.5 V, ID = −1.8 A
8
34
VDD = −10 V, RL = 10 Ω
I
D ≅ −1 A, VGEN = −4.5 V, RG = 6 Ω
Turn-Off Delay Time
Fall Time
td(off)
tf
52
19
7
24
Source-Drain Reverse Recovery Time
trr
20
20
IF = −1.05 A, di/dt = 100 A/µs
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 71511
S-50836 Rev. B, 16-May-05
2
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 71511
S-50836 Rev. B, 16-May-05
3
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