SI4812BDY-T1-E3 [VISHAY]
N-Channel 30-V (D-S) MOSFET with Schottky Diode; N通道30 -V （ D- S）的MOSFET与肖特基二极管
| 型号： | SI4812BDY-T1-E3 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 30-V (D-S) MOSFET with Schottky Diode |
| 文件： | 总9页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4812BDY
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
MOSFET PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
Available
LITTLE FOOT® Plus Power MOSFET
VDS (V)
RDS(on) (Ω)
ID (A)
9.5
0.016 at VGS = 10 V
0.021 at VGS = 4.5 V
•
•
30
7.7
100 % Rg Tested
SCHOTTKY PRODUCT SUMMARY
VSD (V)
VDS (V)
IF (A)
Diode Forward Voltage
0.50 V at 1.0 A
SO-8
30
1.4
D
S
1
2
3
4
8
7
6
5
D
D
S
S
D
D
Schottky Diode
G
G
N-channel MOSFET
S
Top View
Ordering Information:
Si4812BDY-T1-E3 (Lead (Pb)-free)
Si4812BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Limit
Parameter
Symbol
Unit
10 s
Steady State
Drain-Source Voltage (MOSFET)
Reverse Voltage (Schottky)
Gate-Source Voltage (MOSFET)
30
30
20
VDS
V
VGS
ID
TA = 25 °C
TA = 70 °C
9.5
7.7
7.3
5.9
Continuous Drain Current (TJ = 150 °C) (MOSFET)a, b
IDM
IS
Pulsed Drain Current (MOSFET)
Continuous Source Current (MOSFET Diode Conduction)a, b
Average Forward Current (Schottky)
50
A
2.1
1.4
1.2
0.8
IF
IFM
IAS
EAS
Pulsed Forward Current (Schottky)
30
5
Single Pulse Avalanche Current
L = 0.1 mH
Avalanche Energy
1.25
mJ
W
TA = 25 °C
A = 70 °C
TA = 25 °C
2.5
1.6
2.0
1.3
1.4
0.9
1.2
0.8
Maximum Power Dissipation (MOSFET)a, b
T
PD
Maximum Power Dissipation (Schottky)a, b
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Device
Symbol
Typical
40
Maximum
Unit
MOSFET
Schottky
MOSFET
Schottky
MOSFET
Schottky
50
60
Maximum Junction-to-Ambient (t ≤ 10 s)a
50
RthJA
72
90
Maximum Junction-to-Ambient (t = Steady State)a
Maximum Junction-to-Foot (t = Steady State)a
°C/W
85
100
23
18
RthJF
24
30
Notes:
a. Surface Mounted on FR4 board.
b. t ≤ 10 s.
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
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1
Si4812BDY
Vishay Siliconix
MOSFET AND SCHOTTKY SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VDS = VGS, ID = 250 µA
Gate Threshold Voltage
1
3
100
0.100
10
V
VDS = 0 V, VGS
=
20 V
Gate-Body Leakage
nA
VDS = 30 V, VGS = 0 V
0.004
0.7
Zero Gate Voltage Drain Current
(MOSFET and Schottky)
IDSS
VDS = 30 V, VGS = 0 V, TJ = 100 °C
mA
V
DS = 30 V, VGS = 0 V, TJ = 125 °C
VDS ≥ 5 V, VGS = 10 V
3.0
20
On-State Drain Currenta
ID(on)
RDS(on)
gfs
20
A
Ω
S
V
VGS = 10 V, ID = 9.5 A
0.013
0.0165
45
0.016
0.021
Drain-Source On-State Resistancea
Forward Transconductancea
Schottky Diode Forward Voltagea
V
GS = 4.5 V, ID = 7.7 A
VDS = 15 V, ID = 9.5 A
IS = 1.0 A, VGS = 0 V
0.45
0.50
0.42
VSD
IS = 1.0 A, VGS = 0 V, TJ = 125 °C
0.33
Dynamicb
Qg
Qgs
Qgd
Rg
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
8.5
3
13
V
DS = 15 V, VGS = 5 V, ID = 9.5 A
nC
2.6
0.7
15
13
20
8
0.3
1.1
25
20
30
15
35
Ω
td(on)
tr
td(off)
tf
V
DD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Turn-Off Delay Time
Fall Time
ns
trr
IF = 1.0 A, dI/dt = 100 A/µs
Source-Drain Reverse Recovery Time
22
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73038
S-83039-Rev. D, 29-Dec-08
Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
50
40
30
20
10
0
V
GS
= 10 thru 4 V
40
30
20
10
0
T
= 125 °C
C
25 °C
3 V
- 55 °C
3.5
0
1
2
3
4
5
60
10
0.0
0.5
1.0
GS
1.5
2.0
2.5
3.0
4.0
V
DS
- Drain-to-Source Voltage (V)
V
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.030
0.025
0.020
0.015
0.010
0.005
0.000
1300
1040
780
520
260
0
C
iss
V
GS
= 4.5 V
V
= 10 V
GS
C
oss
C
rss
0
10
20
30
40
50
0
5
10
15
20
25
30
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
1.6
1.4
1.2
1.0
0.8
0.6
6
5
4
3
2
1
0
V
D
= 10 V
V
I
= 15 V
GS
= 9.5 A
DS
= 9.5 A
I
D
- 50 - 25
0
25
50
75
100 125 150
0
2
4
6
8
Q
- Total Gate Charge (nC)
T - Junction Temperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
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3
Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
0.05
0.04
0.03
0.02
0.01
0.00
T
= 150 °C
J
10
I
D
= 9.5 A
T
= 25 °C
J
1
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
6
8
10
V
GS
- Gate-to-Source Voltage (V)
V
SD
- Source-to-Drain Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
50
40
30
20
10
0
10
1
0.1
30 V
0.01
0.001
20 V
10 V
0.0001
0.00001
0
25
50
75
100
125
150
0.01
0.1
1
10
100
600
T
- Junction Temperature (°C)
Time (s)
J
Reverse Current (Schottky)
Single Pulse Power (MOSFET)
100
Limited by
R
DS(on)*
10
1
1 ms
10 ms
100 ms
1 s
10 s
0.1
T
= 25 °C
C
Single Pulse
DC
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V > minimum V at which R is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Case
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Document Number: 73038
S-83039-Rev. D, 29-Dec-08
Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 72 °C/W
thJA
(t)
3. T
- T = P
Z
JM
A
DM thJA
Single Pulse
0.01
4. Surface Mounted
-4
-3
-2
-1
10
10
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (MOSFET)
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
P
DM
0.1
0.05
0.02
t
1
t
2
t
t
1
2
1. Duty Cycle, D =
2. Per Unit Base = R
= 85 °C/W
thJA
(t)
3. T
- T = P
Z
JM
A
DM thJA
Single Pulse
10
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (Schottky)
1
10
30
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73038.
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
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5
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
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Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
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Vishay
Disclaimer
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Document Number: 91000
Revision: 11-Mar-11
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