SI6415DQ [VISHAY]
P-Channel 30-V (D-S) MOSFET; P通道30 -V （D -S ）的MOSFET
| 型号： | SI6415DQ |
| 厂家： | 
VISHAY |
| 描述： | P-Channel 30-V (D-S) MOSFET |
| 文件： | 总4页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model Si6415DQ
Vishay Siliconix
P-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 71864
S-60075Rev. B, 23-Jan-06
1
SPICE Device Model Si6415DQ
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.9
276
V
A
V
DS = VGS, ID = −250 µA
V
DS = −5 V, VGS = −1 V
VGS = −10 V, ID = −6.5 A
GS = −4.5 V, ID = −5.2 A
DS = −15 V, ID = −6.5 A
S = −1.5 A, VGS = 0 V
0.016
0.015
0.022
Drain-Source On-State Resistancea
rDS(on)
Ω
0.022
V
Forward Transconductancea
Diode Forward Voltagea
gfs
22
18.5
S
V
V
VSD
I
−0.83
−0.75
Dynamicb
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
46
9.5
8
47
9.5
8
nC
ns
V
DS = −15 V, VGS = −10 V, ID = −6.5 A
22
20
62
65
41
16
17
73
31
40
V
DD = −15 V, RL = 15 Ω
I
D ≅ −1 A, VGEN = −10 V, RG = 6 Ω
Turn-Off Delay Time
Fall Time
td(off)
tf
Source-Drain Reverse Recovery Time
trr
IF = −1.5 A, di/dt = 100 A/µs
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 71864
S-60075Rev. B, 23-Jan-06
2
SPICE Device Model Si6415DQ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 71864
S-60075Rev. B, 23-Jan-06
3
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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1
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