SI7454DP_06 [VISHAY]
N-Channel 100-V (D-S) MOSFET; N沟道100 -V （D -S ）的MOSFET
| 型号： | SI7454DP_06 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 100-V (D-S) MOSFET |
| 文件： | 总4页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model Si7454DP
Vishay Siliconix
N-Channel 100-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 72966
S-60145Rev. B, 13-Feb-06
1
SPICE Device Model Si7454DP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Condition
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
2.8
177
V
A
V
DS = VGS, ID = 250 µA
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 7.8 A
0.028
0.029
30
0.028
0.032
25
Drain-Source On-State Resistancea
rDS(on)
Ω
V
GS = 6 V, ID = 7.2 A
Forward Transconductancea
Forward Voltagea
gfs
VDS = 15 V, ID = 7.8 A
IS = 4 A, VGS = 0 V
S
V
VSD
0.74
0.80
Dynamicb
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
27
7.6
5.4
13
17
31
55
24
7.6
5.4
16
10
35
20
V
DS = 50 V, VGS = 10 V, ID = 7.8 A
nC
ns
VDD = 50 V, RL = 50 Ω
D ≅ 1 A, VGEN = 10 V, RG = 6 Ω
I
Turn-Off Delay Time
Fall Time
td(off)
tf
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 72966
S-60145Rev. B, 13-Feb-06
2
SPICE Device Model Si7454DP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 72966
S-60145Rev. B, 13-Feb-06
3
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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or in any other disclosure relating to any product.
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therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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1
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