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SI7748DP

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描述：N-Channel 30-V (D-S) MOSFET with Schottky Diode

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SI7748DP 概述

N-Channel 30-V (D-S) MOSFET with Schottky Diode N通道30 -V （ D- S）的MOSFET与肖特基二极管

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New Product

Si7748DP

Vishay Siliconix

N-Channel 30-V (D-S) MOSFET with Schottky Diode

FEATURES

PRODUCT SUMMARY

•

Halogen-free

SkyFET™ Monolithic TrenchFET^®

Power MOSFET and Schottky Diode

V_DS(V)

R_DS(on)(Ω)

Q_g(Typ.)

_D(A)^a

•

RoHS

0.0048 at V_GS= 10 V

0.0066 at V_GS= 4.5 V

COMPLIANT

27.8 nC

•

100 % R_gTested

100 % UIS Tested

PowerPAK^®SO-8

APPLICATIONS

•

Notebook

- Vcore Low-Side

6.15 mm

5.15 mm

Schottky Diode

N-Channel MOSFET

Bottom View

Ordering Information: Si7748DP-T1-GE3 (Lead (Pb)-free and Halogen-free)

ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted

Parameter

Symbol

Limit

Unit

V_DS

Drain-Source Voltage

Gate-Source Voltage

V_GS

50^a

23.5^{b, c}

18.6^{b, c}

50^a

4.3^{b, c}

T_C= 25 °C

T_C= 70 °C

T_A= 25 °C

T_A= 70 °C

Continuous Drain Current (T_J= 150 °C)

I_D

I_DM

I_S

Pulsed Drain Current

T_C= 25 °C

Continuous Source-Drain Diode Current

T_A= 25 °C

L = 0.1 mH

T_C= 25 °C

I_AS

Single Pulse Avalanche Current

Single Pulse Avalanche Energy

E_AS

T_C= 70 °C

P_D

Maximum Power Dissipation

4.8^{b, c}

3^{b, c}

T_A= 25 °C

T_A= 70 °C

T_J, T_stg

Operating Junction and Storage Temperature Range

Soldering Recommendations (Peak Temperature)^{d, e}

- 55 to 150

°C

260

THERMAL RESISTANCE RATINGS

Parameter

Maximum Junction-to-Ambient^{b, f}

Maximum Junction-to-Case (Drain)

Symbol

R_thJA

Typical

Maximum

Unit

t ≤ 10 s

°C/W

Steady State

R_thJC

1.7

2.2

Notes:

a. Package limited.

b. Surface Mounted on 1" x 1" FR4 board.

c. t = 10 s.

d. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed

copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and

is not required to ensure adequate bottom side solder interconnection.

e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.

f. Maximum under Steady State conditions is 68 °C/W.

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

www.vishay.com

New Product

Si7748DP

Vishay Siliconix

SPECIFICATIONS T = 25 °C, unless otherwise noted

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Static

V_DS

V_GS(th)

I_GSS

V_GS= 0 V, I_D= 1 mA

V_DS= V_GS, I_D= 1 mA

Drain-Source Breakdown Voltage

Gate-Source Threshold Voltage

Gate-Source Leakage

1.3

2.7

100

0.30

V_DS= 0 V, V_GS

20 V

V_DS= 30 V, V_GS= 0 V

_DS= 30 V, V_GS= 0 V, T_J= 100 °C

V_DS≥ 5 V, V_GS= 10 V

0.075

6.7

I_DSS

I_D(on)

R_DS(on)

g_fs

Zero Gate Voltage Drain Current

On-State Drain Current^a

V_GS= 10 V, I_D= 15 A

0.0039

0.0053

0.0048

0.0066

Drain-Source On-State Resistance^a

Forward Transconductance^a

_GS= 4.5 V, I_D= 10 A

V_DS= 15 V, I_D= 15 A

Dynamic^b

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

3770

575

215

V_DS= 15 V, V_GS= 0 V, f = 1 MHz

V_DS= 15 V, V_GS= 10 V, I_D= 10 A

Q_g

Total Gate Charge

27.8

10.2

7.3

1.0

Q_gs

Q_gd

R_g

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

_DS= 15 V, V_GS= 4.5 V, I_D= 10 A

f = 1 MHz

0.2

2.0

t_d(on)

t_r

t_d(off)

t_f

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

Rise Time

_DD= 15 V, R_L= 1.5 Ω

I_D≅ 10 A, V_GEN= 10 V, R_g= 1 Ω

Turn-Off Delay Time

Fall Time

Turn-On Delay Time

Rise Time

_DD= 15 V, R_L= 1.5 Ω

I_D≅ 10 A, V_GEN= 4.5 V, R_g= 1 Ω

Turn-Off Delay Time

Fall Time

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

I_S

I_SM

V_SD

t_rr

T_C= 25 °C

I_S= 2 A

Pulse Diode Forward Current^a

Body Diode Voltage

0.42

0.55

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

Q_rr

t_a

I_F= 10 A, dI/dt = 100 A/µs, T_J= 25 °C

t_b

Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

www.vishay.com

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

New Product

Si7748DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

= 10 thru 4 V

= 25 °C

= 3 V

= 125 °C

= - 55 °C

0.0

0.5

1.0

1.5

2.0

2.5

- Gate-to-Source Voltage (V)

- Drain-to-Source Voltage (V)

Transfer Characteristics

Output Characteristics

4500

3600

2700

1800

900

0.008

0.007

0.006

0.005

0.004

0.003

iss

= 4.5 V

= 10 V

oss

rss

- Drain-to-Source Voltage (V)

- Drain Current (A)

Capacitance

On-Resistance vs. Drain Current and Gate Voltage

1.8

1.5

1.2

0.9

0.6

0.3

= 20 A

= 10 A

= 10 V

= 4.5 V

= 15 V

= 20 V

- 50 - 25

100 125 150

0.0

12.4

24.8

37.2

49.6

62.0

- Junction Temperature (°C)

- Total Gate Charge (nC)

On-Resistance vs. Junction Temperature

Gate Charge

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

www.vishay.com

New Product

Si7748DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100

0.025

= 15 A

0.020

0.015

0.010

0.005

= 150 °C

= 25 °C

0.1

0.01

= 125 °C

= 25 °C

0.001

0.0

0.2

0.4

0.6

0.8

1.0

- Source-to-Drain Voltage (V)

- Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage

On-Resistance vs. Gate-to-Source Voltage

-1

200

160

120

-2

30 V

-3

20 V

-4

-5

-6

10 V

0.001

0.01

0.1

100

125

150

Time (s)

T - Junction Temperature (°C)

Single Pulse Power, Junction-to-Ambient

Reverse Current (Schottky)

100

Limited by R

DS(on)

1 ms

10 ms

100 ms

1 s

10 s

0.1

= 25 °C

Single Pulse

BVDSS Limited

0.01

0.1

100

- Drain-to-Source Voltage (V)

* V > minimum V at which R is specified

DS(on)

Safe Operating Area, Junction-to-Ambient

www.vishay.com

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

New Product

Si7748DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Package Limited

100

125

150

- Case Temperature (°C)

Current Derating*

2.25

1.80

1.35

0.90

0.45

0.00

100

125

150

100

125

150

- Case Temperature (°C)

- Ambient Temperature (°C)

Power, Junction-to-Ambient

Power, Junction-to-Case

* The power dissipation P_Dis based on T_J(max)= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package

limit.

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

www.vishay.com

New Product

Si7748DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

Notes:

0.1

0.05

0.02

1. Duty Cycle, D =

2. Per Unit Base = R

= 68 °C/W

thJA

(t)

3. T - T = P

DM thJA

Single Pulse

4. Surface Mounted

0.01

-4

-3

-2

-1

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

100

1000

Duty Cycle = 0.5

0.2

0.1

0.05

0.1

0.02

Single Pulse

0.01

-4

-3

-2

-1

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see http://www.vishay.com/ppg?68785.

www.vishay.com

Document Number: 68785

S-81714-Rev. A, 04-Aug-08

Package Information

Vishay Siliconix

PowerPAK^®SO-8, (SINGLE/DUAL)

Backside View of Single Pad

Detail Z

Notes

1. Inch will govern.

Dimensions exclusive of mold gate burrs.

Backside View of Dual Pad

3. Dimensions exclusive of mold flash and cutting burrs.

MILLIMETERS

INCHES

NOM.

0.041

DIM.

MIN.

0.97

0.00

0.33

0.23

5.05

4.80

3.56

1.32

NOM.

1.04

MAX.

1.12

0.05

0.51

0.33

5.26

5.00

3.91

1.68

MIN.

0.038

0.000

0.013

0.009

0.199

0.189

0.140

0.052

MAX.

0.044

0.002

0.020

0.013

0.207

0.197

0.154

0.066

0.41

0.016

0.28

0.011

5.15

0.203

4.90

0.193

3.76

0.148

1.50

0.059

0.57 TYP.

3.98 TYP.

6.15

0.0225 TYP.

0.157 TYP.

0.242

6.05

5.79

3.48

3.68

6.25

5.99

3.84

3.91

0.238

0.228

0.137

0.145

0.246

0.236

0.151

0.154

5.89

0.232

3.66

0.144

3.78

0.149

0.75 TYP.

1.27 BSC

1.27 TYP.

0.030 TYP.

0.050 BSC

0.050 TYP.

0.56

0.51

0.06

0°

0.022

0.020

0.002

0°

0.61

0.71

0.20

12°

0.024

0.028

0.008

12°

0.61

0.024

0.13

0.005

0.15

0.25

0.36

0.006

0.010

0.014

0.125 TYP.

0.005 TYP.

ECN: T10-0055-Rev. J, 15-Feb-10

DWG: 5881

Document Number: 71655

Revison: 15-Feb-10

www.vishay.com

AN821

Vishay Siliconix

PowerPAK SO-8 Mounting and Thermal Considerations

Wharton McDaniel

MOSFETs for switching applications are now available

PowerPAK SO-8 SINGLE MOUNTING

with die on resistances around 1 mΩ and with the

capability to handle 85 A. While these die capabilities

represent a major advance over what was available

just a few years ago, it is important for power MOSFET

packaging technology to keep pace. It should be obvi-

ous that degradation of a high performance die by the

package is undesirable. PowerPAK is a new package

technology that addresses these issues. In this appli-

cation note, PowerPAK’s construction is described.

Following this mounting information is presented

including land patterns and soldering profiles for max-

imum reliability. Finally, thermal and electrical perfor-

mance is discussed.

The PowerPAK single is simple to use. The pin

arrangement (drain, source, gate pins) and the pin

dimensions are the same as standard SO-8 devices

(see Figure 2). Therefore, the PowerPAK connection

pads match directly to those of the SO-8. The only dif-

ference is the extended drain connection area. To take

immediate advantage of the PowerPAK SO-8 single

devices, they can be mounted to existing SO-8 land

patterns.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the

SO-8 package (Figure 1). The PowerPAK SO-8 uti-

lizes the same footprint and the same pin-outs as the

standard SO-8. This allows PowerPAK to be substi-

tuted directly for a standard SO-8 package. Being a

leadless package, PowerPAK SO-8 utilizes the entire

SO-8 footprint, freeing space normally occupied by the

leads, and thus allowing it to hold a larger die than a

standard SO-8. In fact, this larger die is slightly larger

than a full sized DPAK die. The bottom of the die attach

pad is exposed for the purpose of providing a direct,

low resistance thermal path to the substrate the device

is mounted on. Finally, the package height is lower

than the standard SO-8, making it an excellent choice

for applications with space constraints.

Standard SO-8

PowerPAK SO-8

Figure 2.

The minimum land pattern recommended to take full

advantage of the PowerPAK thermal performance see

Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Sili-

conix MOSFETs. Click on the PowerPAK SO-8 single

in the index of this document.

In this figure, the drain land pattern is given to make full

contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and

top of the drawn pattern. This extension will serve to

increase the heat dissipation by decreasing the ther-

mal resistance from the foot of the PowerPAK to the

PC board and therefore to the ambient. Note that

increasing the drain land area beyond a certain point

will yield little decrease in foot-to-board and foot-to-

ambient thermal resistance. Under specific conditions

of board configuration, copper weight and layer stack,

experiments have found that more than about 0.25 to

0.5 in of additional copper (in addition to the drain

land) will yield little improvement in thermal perfor-

mance.

Figure 1. PowerPAK 1212 Devices

Document Number 71622

28-Feb-06

www.vishay.com

AN821

Vishay Siliconix

PowerPAK SO-8 DUAL

For the lead (Pb)-free solder profile, see http://

www.vishay.com/doc?73257.

The pin arrangement (drain, source, gate pins) and the

pin dimensions of the PowerPAK SO-8 dual are the

same as standard SO-8 dual devices. Therefore, the

PowerPAK device connection pads match directly to

those of the SO-8. As in the single-channel package,

the only exception is the extended drain connection

area. Manufacturers can likewise take immediate

advantage of the PowerPAK SO-8 dual devices by

mounting them to existing SO-8 dual land patterns.

To take the advantage of the dual PowerPAK SO-8’s

thermal performance, the minimum recommended

land pattern can be found in Application Note 826,

Recommended Minimum Pad Patterns With Outline

Drawing Access for Vishay Siliconix MOSFETs. Click

on the PowerPAK 1212-8 dual in the index of this doc-

ument.

Ramp-Up Rate

+ 6 °C /Second Maximum

The gap between the two drain pads is 24 mils. This

matches the spacing of the two drain pads on the Pow-

erPAK SO-8 dual package.

Temperature at 155 15 °C

120 Seconds Maximum

Temperature Above 180 °C

Maximum Temperature

Time at Maximum Temperature

Ramp-Down Rate

70 - 180 Seconds

240 + 5/- 0 °C

20 - 40 Seconds

+ 6 °C/Second Maximum

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder

reflow reliability requirements. Devices are subjected

to solder reflow as a test preconditioning and are then

reliability-tested using temperature cycle, bias humid-

ity, HAST, or pressure pot. The solder reflow tempera-

ture profile used, and the temperatures and time

duration, are shown in Figures 3 and 4.

Figure 3. Solder Reflow Temperature Profile

10 s (max)

210 - 220 °C

3 °C(max)

4 °C/s (max)

183 °C

140 - 170 °C

50 s (max)

3 °C(max)

60 s (min)

Reflow Zone

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

www.vishay.com

Document Number 71622

28-Feb-06

AN821

Vishay Siliconix

THERMAL PERFORMANCE

Introduction

Because of the presence of the trough, this result sug-

gests a minimum performance improvement of 10 °C/W

by using a PowerPAK SO-8 in a standard SO-8 PC

board mount.

A basic measure of a device’s thermal performance is

the junction-to-case thermal resistance, Rθ , or the

junction-to-foot thermal resistance, Rθ . This parameter

is measured for the device mounted to an infinite heat

sink and is therefore a characterization of the device

only, in other words, independent of the properties of the

object to which the device is mounted. Table 1 shows a

comparison of the DPAK, PowerPAK SO-8, and stan-

dard SO-8. The PowerPAK has thermal performance

equivalent to the DPAK, while having an order of magni-

tude better thermal performance over the SO-8.

The only concern when mounting a PowerPAK on a

standard SO-8 pad pattern is that there should be no

traces running between the body of the MOSFET.

Where the standard SO-8 body is spaced away from the

pc board, allowing traces to run underneath, the Power-

PAK sits directly on the pc board.

Thermal Performance - Spreading Copper

Designers may add additional copper, spreading cop-

per, to the drain pad to aid in conducting heat from a

device. It is helpful to have some information about the

thermal performance for a given area of spreading cop-

per.

TABLE 1.

DPAK and PowerPAK SO-8

Equivalent Steady State Performance

DPAK

PowerPAK

SO-8

Standard

SO-8

Thermal

Resistance Rθ_jc

1.2 °C/W

1.0 °C/W

16 °C/W

Figure 6 shows the thermal resistance of a PowerPAK

SO-8 device mounted on a 2-in. 2-in., four-layer FR-4

PC board. The two internal layers and the backside layer

are solid copper. The internal layers were chosen as

solid copper to model the large power and ground

planes common in many applications. The top layer was

cut back to a smaller area and at each step junction-to-

ambient thermal resistance measurements were taken.

The results indicate that an area above 0.3 to 0.4 square

inches of spreading copper gives no additional thermal

performance improvement. A subsequent experiment

was run where the copper on the back-side was

reduced, first to 50 % in stripes to mimic circuit traces,

and then totally removed. No significant effect was

observed.

Thermal Performance on Standard SO-8 Pad Pattern

Because of the common footprint, a PowerPAK SO-8

can be mounted on an existing standard SO-8 pad pat-

tern. The question then arises as to the thermal perfor-

mance of the PowerPAK device under these conditions.

A characterization was made comparing a standard SO-8

and a PowerPAK device on a board with a trough cut out

underneath the PowerPAK drain pad. This configuration

restricted the heat flow to the SO-8 land pads. The

results are shown in Figure 5.

Si4874DY vs. Si7446DP PPAK on a 4-Layer Board

SO-8 Pattern, Trough Under Drain

vs. Spreading Copper

(0 %, 50 %, 100 % Back Copper)

Si4874DY

Si7446DP

100 %

0 %

50 %

0.0001

0.01

10000

100

Pulse Duration (sec)

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path

Figure 6. Spreading Copper Junction-to-Ambient Performance

Document Number 71622

28-Feb-06

www.vishay.com

AN821

Vishay Siliconix

SYSTEM AND ELECTRICAL IMPACT OF

PowerPAK SO-8

In any design, one must take into account the change in

Suppose each device is dissipating 2.7 W. Using the

junction-to-foot thermal resistance characteristics of the

PowerPAK SO-8 and the standard SO-8, the die tem-

perature is determined to be 107 °C for the PowerPAK

(and for DPAK) and 148 °C for the standard SO-8. This

is a 2 °C rise above the board temperature for the Pow-

erPAK and a 43 °C rise for the standard SO-8. Referring

to Figure 7, a 2 °C difference has minimal effect on

MOSFET r

with temperature (Figure 7).

DS(on)

On-Resistance vs. Junction Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

whereas a 43C difference has a significant effect

= 10 V

DS(on)

= 23 A

on r

DS(on)

Minimizing the thermal rise above the board tempera-

ture by using PowerPAK has not only eased the thermal

design but it has allowed the device to run cooler, keep

low, and permits the device to handle more cur-

DS(on)

rent than the same MOSFET die in the standard SO-8

package.

CONCLUSIONS

PowerPAK SO-8 has been shown to have the same

thermal performance as the DPAK package while hav-

ing the same footprint as the standard SO-8 package.

The PowerPAK SO-8 can hold larger die approximately

equal in size to the maximum that the DPAK can accom-

modate implying no sacrifice in performance because of

package limitations.

Recommended PowerPAK SO-8 land patterns are pro-

vided to aid in PC board layout for designs using this

new package.

-50

-25

100 125 150

- Junction Temperature (°C)

Figure 7. MOSFET r_DS(on)vs. Temperature

A MOSFET generates internal heat due to the current

passing through the channel. This self-heating raises

the junction temperature of the device above that of the

PC board to which it is mounted, causing increased

power dissipation in the device. A major source of this

problem lies in the large values of the junction-to-foot

thermal resistance of the SO-8 package.

Thermal considerations have indicated that significant

advantages can be gained by using PowerPAK SO-8

devices in designs where the PC board was laid out for

the standard SO-8. Applications experimental data gave

thermal performance data showing minimum and typical

thermal performance in a SO-8 environment, plus infor-

mation on the optimum thermal performance obtainable

including spreading copper. This further emphasized the

DPAK equivalency.

PowerPAK SO-8 minimizes the junction-to-board ther-

mal resistance to where the MOSFET die temperature is

very close to the temperature of the PC board. Consider

two devices mounted on a PC board heated to 105 °C

by other components on the board (Figure 8).

PowerPAK SO-8 therefore has the desired small size

characteristics of the SO-8 combined with the attractive

thermal characteristics of the DPAK package.

PowerPAK SO-8

Standard SO-8

107 °C

148 °C

0.8 °C/W

PC Board at 105 °C

16 C/W

Figure 8. Temperature of Devices on a PC Board

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Document Number 71622

28-Feb-06

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK^®SO-8 Single

0.260

(6.61)

0.150

(3.81)

0.024

(0.61)

0.026

(0.66)

0.050

(1.27)

0.032

(0.82)

0.040

(1.02)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index

Document Number: 72599

Revision: 21-Jan-08

www.vishay.com

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Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE

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Document Number: 91000

Revision: 11-Mar-11

www.vishay.com

SI7748DP 相关器件

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