SI8401DB-T1 [VISHAY]

P-Channel 20-V (D-S) MOSFET; P通道20 -V (D -S )的MOSFET
SI8401DB-T1
型号: SI8401DB-T1
厂家: VISHAY    VISHAY
描述:

P-Channel 20-V (D-S) MOSFET
P通道20 -V (D -S )的MOSFET

文件: 总5页 (文件大小:85K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si8401DB  
Vishay Siliconix  
P-Channel 20-V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
D TrenchFETr Power MOSFET  
VDS (V)  
rDS(on) (W)  
ID (A)  
D New MICRO FOOTr Chipscale Packaging  
Reduces Footprint Area Profile (0.62 mm) and  
On-Resistance Per Footprint Area  
D Pin Compatible to Industry Standard Si3443DV  
APPLICATIONS  
0.065 @ V = 4.5 V  
4.9  
4.1  
GS  
20  
0.095 @ V = 2.5  
V
GS  
D PA, Battery and Load Switch  
D Battery Charger Switch  
D PA Switch  
MICRO FOOT  
S
Bump Side View  
Backside View  
3
4
2
G
D
S
D
G
8401  
xxx  
Device Marking: 8401  
xxx = Date/Lot Traceability Code  
D
1
P-Channel MOSFET  
Ordering Information: Si8401DB-T1  
Si8401DB-T1—E3 (Lead Free)  
ABSOLUTE MAXIMUM RATINGS (T = 25_C UNLESS OTHERWISE NOTED)  
A
Parameter  
Symbol  
5 secs  
Steady State  
Unit  
Drain-Source Voltage  
Gate-Source Voltage  
V
20  
DS  
V
V
GS  
"12  
T
= 25_C  
= 70_C  
3.6  
2.8  
4.9  
3.9  
A
a
Continuous Drain Current (T = 150_C)  
I
D
J
T
A
A
Pulsed Drain Current  
I
DM  
10  
a
continuous Source Current (Diode Conduction)  
I
2.5  
2.77  
1.77  
2.5  
1.47  
0.94  
S
T
= 25_C  
= 70_C  
A
a
Maximum Power Dissipation  
P
W
D
T
A
Operating Junction and Storage Temperature Range  
T , T  
55 to 150  
_C  
J
stg  
c
VPR  
215/245  
b
Package Reflow Conditions  
_C  
c
IR/Convection  
220/250  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
Typical  
Maximum  
Unit  
t v 5 sec  
Steady State  
Steady State  
35  
72  
16  
45  
85  
20  
a
Maximum Junction-to-Ambient  
R
thJA  
R
thJF  
_C/W  
Maximum Junction-to-Foot (drain)  
Notes  
a. Surface Mounted on 1” x 1” FR4 Board.  
b. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering.  
c. Package reflow conditions for lead-free.  
Document Number: 71674  
S-40384—Rev. F, 01-Mar-04  
www.vishay.com  
1
Si8401DB  
Vishay Siliconix  
SPECIFICATIONS (T = 25_C UNLESS OTHERWISE NOTED)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Static  
Gate Threshold Voltage  
Gate-Body Leakage  
V
V
= V , I = 250 mA  
0.45  
0.9  
V
GS(th)  
DS  
GS  
D
I
V
= 0 V, V = "12 V  
"100  
nA  
GSS  
DS  
GS  
V
= 20 V, V = 0 V  
1  
5  
DS  
GS  
Zero Gate Voltage Drain Current  
I
mA  
DSS  
V
DS  
= 20 V, V = 0 V, T = 70_C  
GS  
J
a
On-State Drain Current  
I
V
DS  
v 5 V, V = 4.5 V  
5  
A
D(on)  
GS  
V
= 4.5 V, I = 1 A  
0.057  
0.080  
0.065  
0.095  
GS  
D
a
Drain-Source On-State Resistance  
r
W
DS(on)  
V
= 2.5 V, I = 1 A  
GS  
D
a
Forward Transconductance  
g
6
S
V
V
= 10 V, I = 1 A  
fs  
DS  
D
a
Diode Forward Voltage  
V
SD  
I
= 1 A, V = 0 V  
0.73  
1.1  
S
GS  
Dynamicb  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Turn-On Delay Time  
Rise Time  
Q
11  
2.1  
2.9  
17  
28  
88  
60  
17  
g
Q
Q
V
= 10 V, V = 4.5 V, I = 1 A  
nC  
ns  
gs  
gd  
DS  
GS  
D
t
25  
45  
d(on)  
t
r
V
DD  
= 10 V, R = 10 W  
L
I
D
^ 1 A, V  
= 4.5 V, R = 6 W  
GEN G  
Turn-Off Delay Time  
Fall Time  
t
135  
90  
d(off)  
t
f
Source-Drain Reverse Recovery Time  
t
rr  
I = A, di/dt = 100 A/ms  
F
Notes  
a. Pulse test; pulse width v 300 ms, duty cycle v 2%.  
b. Guaranteed by design, not subject to production testing.  
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)  
Output Characteristics  
Transfer Characteristics  
10  
10  
8
V
= 5 thru 2.5 V  
GS  
8
6
4
2
0
2 V  
6
4
T
= 125_C  
C
2
1.5 V  
25_C  
55_C  
0
0
2
4
6
8
10  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
V
DS  
Drain-to-Source Voltage (V)  
V
GS  
Gate-to-Source Voltage (V)  
Document Number: 71674  
S-40384—Rev. F, 01-Mar-04  
www.vishay.com  
2
Si8401DB  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)  
On-Resistance vs. Drain Current  
Capacitance  
1500  
1200  
900  
600  
300  
0
0.15  
0.12  
C
iss  
V
V
= 2.5 V  
= 4.5 V  
GS  
0.09  
0.06  
0.03  
0.00  
GS  
C
oss  
C
rss  
0
1
2
3
4
5
6
7
0
4
8
12  
16  
20  
I
D
Drain Current (A)  
V
DS  
Drain-to-Source Voltage (V)  
Gate Charge  
On-Resistance vs. Junction Temperature  
10  
8
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
V
D
= 10 V  
V
GS  
= 4.5 V  
DS  
I
= 1  
A
I = 1 A  
D
6
4
2
0
0
4
8
12  
16  
20  
50 25  
0
25  
50  
75  
100 125 150  
Q
Total Gate Charge (nC)  
T
Junction Temperature (_C)  
g
J
Source-Drain Diode Forward Voltage  
On-Resistance vs. Gate-to-Source Voltage  
0.30  
0.24  
0.18  
0.12  
0.06  
0.00  
10  
I
D
= 1 A  
T
= 150_C  
J
1
T
= 25_C  
J
0.1  
0.0  
0
1
2
3
4
5
6
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
SD  
Source-to-Drain Voltage (V)  
V
GS  
Gate-to-Source Voltage (V)  
Document Number: 71674  
S-40384—Rev. F, 01-Mar-04  
www.vishay.com  
3
Si8401DB  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)  
Threshold Voltage  
Single Pulse Power, Juncion-To-Ambient  
0.4  
80  
60  
I
D
= 250 mA  
0.3  
0.2  
40  
20  
0.1  
0.0  
0.1  
0.2  
0
50 25  
0
25  
50  
75  
100 125 150  
0.001  
0.01  
0.1  
1
10  
T
Temperature (_C)  
Time (sec)  
J
Normalized Thermal Transient Impedance, Junction-to-Ambient  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
Notes:  
P
DM  
0.1  
0.05  
0.02  
t
1
t
2
t
t
1
2
1. Duty Cycle, D =  
2. Per Unit Base = R  
= 72_C/W  
thJA  
(t)  
3. T T = P Z  
DM thJA  
JM  
A
Single Pulse  
4. Surface Mounted  
0.01  
4  
3  
2  
1  
10  
10  
10  
10  
1
10  
100  
600  
Square Wave Pulse Duration (sec)  
Normalized Thermal Transient Impedance, Junction-to-Foot  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
Single Pulse  
0.01  
4  
3  
2  
1  
10  
10  
10  
10  
1
10  
Square Wave Pulse Duration (sec)  
Document Number: 71674  
S-40384—Rev. F, 01-Mar-04  
www.vishay.com  
4
Si8401DB  
Vishay Siliconix  
PACKAGE OUTLINE  
MICRO FOOT: 4-BUMP (2 X 2, 0.8-mm PITCH)  
4   O 0.30 X 0.31  
Note 3  
Solder Mask O X 0.40  
e
A
A
2
Silicon  
A
1
Bump Note 2  
b Diamerter  
e
S
e
Recommended Land  
E
8401  
XXX  
e
S
D
Mark on Backside of Die  
NOTES (Unless Otherwise Specified):  
1. Laser mark on the silicon die back, coated with a thin metal.  
2. Bumps are Eutectic solder 63/57 Sn/Pb. (Sn 3.8 Ag, 0.7 Cu for Pb-free bumps)  
3. Non-solder mask defined copper landing pad.  
4. The flat side of wafers is oriented at the bottom.  
MILLIMETERS*  
INCHES  
Dim  
Min  
Max  
Min  
Max  
0.600  
0.260  
0.340  
0.370  
1.520  
1.520  
0.750  
0.370  
0.650  
0.290  
0.360  
0.410  
1.600  
1.600  
0.850  
0.380  
0.0236  
0.0102  
0.0134  
0.0146  
0.0598  
0.0598  
0.0295  
0.0146  
0.0256  
0.0114  
0.0142  
0.0161  
0.0630  
0.0630  
0.0335  
0.0150  
A
A1  
A2  
b
D
E
e
S
* Use millimeters as the primary measurement.  
Document Number: 71674  
S-40384—Rev. F, 01-Mar-04  
www.vishay.com  
5

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