SI8824EDB-T2-E1 [VISHAY]
Small Signal Field-Effect Transistor,;
| 型号： | SI8824EDB-T2-E1 |
| 厂家： | 
VISHAY |
| 描述： | Small Signal Field-Effect Transistor, PC 开关 晶体管 |
| 文件： | 总8页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8824EDB
Vishay Siliconix
www.vishay.com
N-Channel 20 V (D-S) MOSFET
FEATURES
• TrenchFET® power MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω) MAX.
0.075 at VGS = 4.5 V
0.082 at VGS = 2.5 V
0.090 at VGS = 1.8 V
0.125 at VGS = 1.5 V
0.175 at VGS = 1.2 V
ID (A) a
2.9
Qg (TYP.)
• Ultra small 0.8 mm x 0.8 mm outline
• Ultra thin 0.357 mm height
2.7
• Typical ESD protection 2000 V (HBM)
20
2.6
2.7 nC
• Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
2.2
1.5
APPLICATIONS
D
• Ultraportable and wearable devices
• Load switch with low voltage drop
• Load switch for 1.2 V, 1.5 V, and 1.8 V
MICRO FOOT® 0.8 x 0.8
S
2
S
3
power lines
G
xxx
xx
• Small signal and high speed switching
1
G
4
D
1
Backside View
Bump Side View
S
Marking Code: AM
N-Channel MOSFET
Ordering Information:
Si8824EDB-T2-E1 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
5
TA = 25 °C
TA = 70 °C
TA = 25 °C
TA = 70 °C
2.9 a
2.3 a
2.1 b
1.7 b
15
Continuous Drain Current (TJ = 150 °C)
ID
A
Pulsed Drain Current (t = 100 μs)
IDM
IS
TA = 25 °C
TA = 25 °C
TA = 25 °C
TA = 70 °C
TA = 25 °C
TA = 70 °C
0.7 a
0.4 b
0.9 a
0.6 a
0.5 b
0.3 b
-55 to +150
260
Continuous Source-Drain Diode Current
Maximum Power Dissipation
PD
W
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) c
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient a, d
Maximum Junction-to-Ambient b, e
Notes
a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.
SYMBOL
RthJA
TYPICAL
105
MAXIMUM
UNIT
135
260
t ≤ 5 s
°C / W
200
b. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s.
c. Refer to IPC / JEDEC® (J-STD-020), no manual or hand soldering.
d. Maximum under steady state conditions is 185 °C / W.
e. Maximum under steady state conditions is 330 °C / W.
S15-0338-Rev. A, 23-Feb-15
Document Number: 62978
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8824EDB
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS / TJ
ΔVGS(th) / TJ
VGS(th)
VGS = 0 V, ID = 250 μA
ID = 250 μA
20
-
-
V
mV / °C
V
VDS Temperature Coefficient
-
13
-
-
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
-
-2
VDS = VGS , ID = 250 μA
0.35
-
-
0.8
2
IGSS
VDS = 0 V, VGS
=
5 V
-
-
VDS = 20 V, VGS = 0 V
DS = 20 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 4.5 V
-
1
μA
A
Zero Gate Voltage Drain Current
On-State Drain Current a
IDSS
V
-
-
10
ID(on)
10
-
-
-
VGS = 4.5 V, ID = 1 A
0.060
0.065
0.070
0.080
0.090
11
0.075
0.082
0.090
0.125
0.175
-
V
GS = 2.5 V, ID = 1 A
-
Drain-Source On-State Resistance a
RDS(on)
VGS = 1.8 V, ID = 0.5 A
VGS = 1.5 V, ID = 0.5 A
VGS = 1.2 V, ID = 0.1 A
-
Ω
S
-
-
Forward Transconductance a
Dynamic b
gfs
VDS = 10 V, ID = 1 A
-
Input Capacitance
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
-
400
60
-
-
Output Capacitance
V
DS = 10 V, VGS = 0 V, f = 1 MHz
pF
Reverse Transfer Capacitance
Total Gate Charge
35
-
2.7
0.46
0.93
3
6
Gate-Source Charge
Qgs
Qgd
Rg
V
DS = 10 V, VGS = 4.5 V, ID = 1 A
-
nC
Gate-Drain Charge
-
Gate Resistance
f = 1 MHz
-
Ω
Turn-On Delay Time
td(on)
tr
td(off)
tf
5
10
40
35
20
Rise Time
20
VDD = 10 V, RL = 10 Ω
ns
ID ≅ 1 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
17
Fall Time
10
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
IS
ISM
VSD
trr
TC = 25 °C
-
-
-
-
-
-
-
-
-
0.7
15
1.2
20
10
-
A
IS = 1 A, VGS = 0 V
0.7
11
5
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Qrr
ta
IF = 1 A, dI / dt = 100 A / μs, TJ = 25 °C
7
ns
tb
4
-
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S15-0338-Rev. A, 23-Feb-15
Document Number: 62978
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8824EDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10-3
10-4
1.0
0.8
TJ = 150 °C
10-5
TJ = 25 °C
0.6
TJ = 25 °C
10-6
0.4
10-7
0.2
10-8
10-9
0
0
4
8
12
16
0
4
8
12
16
1.5
12
VGS - Gate-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
15
12
9
10
8
VGS = 5 V thru 2 V
VGS = 1.5 V
6
6
4
TC = 25 °C
TC = 125 °C
3
2
VGS = 1 V
TC = - 55 °C
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.3
0.6
0.9
1.2
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
600
500
400
300
200
100
0
0.20
0.16
0.12
0.08
0.04
0
VGS = 1.2 V
Ciss
VGS = 1.5 V
VGS = 1.8 V
VGS = 4.5 V
Coss
VGS = 2.5 V
Crss
0
3
6
9
12
15
0
2
4
6
8
10
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
S15-0338-Rev. A, 23-Feb-15
Capacitance vs. Drain-to-Source Voltage
Document Number: 62978
3
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8824EDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
5
4
3
2
1
0
10
ID = 1 A
TJ = 150 °C
VDS = 10 V
VDS = 5 V
TJ = 25 °C
1
VDS = 16 V
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
1
1
2
2
3
3
Qg - Total Gate Charge (nC)
VSD - Source-to-Drain Voltage (V)
Gate Charge
Source-Drain Diode Forward Voltage
0.7
0.6
0.5
0.4
0.3
0.2
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VGS = 2.5 V, 1.8 V, 1.5 V; ID = 1 A
VGS = 4.5 V; ID = 1 A
VGS = 1.2 V; ID = 0.1 A
ID = 250 μA
- 50 - 25
0
25
50
75
100 125 150
- 50 - 25
0
25
50
75
100 125 150
TJ - Junction Temperature (°C)
TJ - Temperature (°C)
On-Resistance vs. Junction Temperature
Threshold Voltage
0.20
0.16
0.12
0.08
0.04
0
14
12
10
8
ID = 1 A
TJ = 125 °C
TJ = 25 °C
6
4
2
0
0
1
2
3
4
5
0.001
0.01
0.1
1
10
100
1000
VGS - Gate-to-Source Voltage (V)
Time (s)
On-Resistance vs. Gate-to-Source Voltage
S15-0338-Rev. A, 23-Feb-15
Single Pulse Power (Junction-to-Ambient)
Document Number: 62978
4
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8824EDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
Limited by RDS(on)
*
IDM Limited
10
1
ID Limited
100 µs
1 ms
100 ms
0.1
0.01
10 s
1 s, 10ms
DC
TA = 25 °C
BVDSS Limited
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
0.8
0.6
0.4
0.2
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
150
25
50
75
100
125
150
TA - Ambient Temperature (°C)
T
- Ambient Temperature (°C)
A
Current Derating*
Power Derating
Note
When mounted on 1" x 1" FR4 with full copper.
•
* The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S15-0338-Rev. A, 23-Feb-15
Document Number: 62978
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8824EDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
0.05
P
DM
t
1
0.02
t
2
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Base = R
= 185 °C/W
thJA
(t)
3. T - T = P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
1
100
1000
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (on 1" x 1" FR4 board with maximum copper)
1
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
P
DM
0.05
t
1
t
2
0.02
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Base = R
= 330 °C/W
thJA
(t)
3. T - T = P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (on 1" x 1" FR4 board with minimum copper)
1
100
1000
10
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62978.
S15-0338-Rev. A, 23-Feb-15
Document Number: 62978
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
MICRO FOOT®: 4-Bump (0.8 mm x 0.8 mm, 0.4 mm Pitch)
D
S
e
S
4x Ø b
S
S
XXX
G
D
AK
Mark on Backside of die
4-Ø 0.205 to 0.225 Note 5
Solder Mask ~Ø 0.215
b
k
Bump Note 2
b1
e
Note 4
Notes
(1)
Laser mark on the backside surface of die
Bumps are 95.5 % Sn,3.8 % Ag,0.7 % Cu
“i” is the location of pin 1
“b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
Non-solder mask defined copper landing pad.
(2)
(3)
(4)
(5)
MILLIMETERS a
NOM.
0.365
INCHES
NOM.
DIM.
MIN.
0.328
0.136
0.192
0.200
MAX.
0.402
0.184
0.218
0.240
MIN.
MAX.
0.0158
0.0072
0.0086
0.0094
A
A1
A2
b
0.0129
0.0053
0.0076
0.0078
0.0144
0.0062
0.0081
0.0086
0.0068
0.0157
0.0070
0.0299
0.0027
0.160
0.205
0.220
b1
e
0.175
0.400
S
0.160
0.720
0.040
0.180
0.200
0.800
0.100
0.0062
0.0283
0.0015
0.0078
0.0314
0.0039
D
0.760
K
0.070
Note
a. Use millimeters as the primary measurement.
ECN: T15-0053-Rev. A, 16-Feb-15
DWG: 6033
Revision: 16-Feb-15
Document Number: 69442
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
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