SI9122_08 [VISHAY]

500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers; 集成二级同步整流驱动器的500 kHz的半桥DC / DC控制器
SI9122_08
型号: SI9122_08
厂家: VISHAY    VISHAY
描述:

500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers
集成二级同步整流驱动器的500 kHz的半桥DC / DC控制器

驱动器 控制器
文件: 总20页 (文件大小:330K)
中文:  中文翻译
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Si9122  
Vishay Siliconix  
500-kHz Half-Bridge DC/DC Controller  
with Integrated Secondary Synchronous Rectification Drivers  
DESCRIPTION  
FEATURES  
Si9122 is a dedicated half-bridge IC ideally suited to fixed  
telecom applications where efficiency is required at low  
output voltages (e.g. < 3.3 V). Designed to operate within the  
fixed telecom voltage range of 33 to 72 V, the IC is capable  
of controlling and driving both the low and high-side  
switching devices of a half bridge circuit and also controlling  
the switching devices on the secondary side of the bridge.  
Due to the very low on-resistance of the secondary  
MOSFETs, a significant increase in the efficiency can be  
achieved as compared with conventional Schottky diodes.  
Control of the secondary devices is by means of a pulse  
transformer and a pair of inverters. Such a system has  
efficiencies well in excess of 90 % even for low output  
voltages. On-chip control of the dead time delays between  
the primary and secondary synchronous signals keep  
efficiencies high and prevent accidental destruction of the  
power transformer. An external resistor sets the switching  
frequency from 200 kHz to 625 kHz.  
12 V to 72 V input voltage range  
Integrated half-bridge primary drivers  
(1 A drive capability)  
RoHS  
COMPLIANT  
Secondary synchronous signals with  
programmable deadtime delay  
Voltage mode control  
Voltage feedforward compensation  
High voltage pre-regulator operates during start-up  
Current sensing on low-side primary device  
Frequency foldback eliminates constant current tail  
Advanced maximum current control during start-up and  
shorted load  
Low input voltage detection  
Programmable soft-start function  
Over temperature protections  
Si9122 has advanced current monitoring and control  
circuitry which allow the user to set the maximum current in  
the primary circuit. Such a feature acts as protection against  
output shorting and also provides constant current into large  
capacitive loads during start-up or when paralleling power  
supplies. Current sensing is by means of a sense resistor on  
the low-side primary device.  
APPLICATIONS  
Network cards  
Power supply modules  
FUNCTIONAL BLOCK DIAGRAM  
12 V to 72 V  
BST  
Synchronous  
Rectifiers  
DH  
LX  
1 V to 12 V Typ.  
V
+
Si9122  
OUT  
DL  
-
CS2  
V
IN_DET  
CS1  
SR  
H
C
Error  
Amplifier  
L_CONT  
V
CC  
SR  
L
+
-
V
REF  
EP  
Opto Isolator  
Figure 1.  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
1
Si9122  
Vishay Siliconix  
TECHNICAL DESCRIPTION  
Si9122 is a voltage mode controller for the half-bridge  
topology. With 100 V depletion mode MOSFET capability,  
the Si9122 is capable of powering directly from the high  
voltage bus to VCC through an external PNP pass transistor,  
or may be powered through an external regulator directly  
through the VCC pin. With PWM control, Si9122 provides  
peak efficiency throughout the entire line and load range. In  
order to simplify the traditional secondary synchronous  
rectification, Si9122 provides intelligent gate drive signals to  
control the secondary MOSFETs. With independent gate  
drive signals from the controller, transformer design is no  
longer limited by the gate to a source rating of the MOSFETs.  
Si9122 provides constant VGS voltage, independent of line  
voltage to minimize the gate charge loss as well as  
conduction loss. A break-before-make function is included to  
prevent shoot through current or transformer shorting.  
Adjustable Break-Before-Make time is incorporated into the  
IC and is programmable by an external resistor value.  
Si9122 is packaged in TSSOP-20 and MLP65-20 packages.  
Both TSSOP-20 and MLP65-20 packages are available in  
lead (Pb)-free option. In order to satisfy the stringent ambient  
temperature requirements, Si9122 is rated to handle the  
industrial temperature range of - 40 °C to 85 °C. When a  
situation arises which results in a rapid increase in primary  
(or secondary current) such as output shorted or start-up  
with a large output capacitor, control of the PWM generator  
is handed over to the current loop. Monitoring of the load  
current is by means of a sense resistor on the primary low-  
side switch.  
DETAILED BLOCK DIAGRAM  
V
IN  
V
CC  
R
OSC  
High-Side  
Primary  
Driver  
BST  
9.1 V  
V
UVLO  
REG_COMP  
Pre-Regulator  
+
-
D
H
Int  
V
REF  
8.8 V  
L
X
Low-Side  
Driver  
V
CC  
V
INDET  
V
FF  
V
D
UV  
+
-
L
OSC  
V
REF  
EP  
SS  
Ramp  
V
SD  
+
-
PGND  
132 kΩ  
550 mV  
60 kΩ  
Error Amplifier  
V
CC  
-
+
Driver  
Control  
and  
+
-
SR  
H
V
PWM  
Comparator  
REF  
Timing  
2
20 µA  
SYNC  
Driver High  
I
SS  
OTP  
8 V  
V
CC  
SR  
L
CS2  
CS1  
Duty Cycle  
Control  
+
-
Peak DET  
SYNC  
Driver Low  
Si9122  
Over Current Protection  
GND  
C
BBM  
L_CONT  
Figure 2.  
www.vishay.com  
2
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V  
Parameter  
Limit  
75  
Unit  
VIN (Continuous)  
V
IN (100 ms)  
100  
VCC  
14.5  
90  
Continuous  
100 ms  
VBST  
115  
75  
V
VLX  
VBST - VLX  
VREF, ROSC  
Logic Inputs  
15  
- 0.3 to VCC + 0.3  
- 0.3 to VCC + 0.3  
- 0.3 to VCC + 0.3  
Analog Inputs  
HV Pre-Regulator Input Current (Continuous)  
Storage Temperature  
5
mA  
°C  
- 65 to 150  
150  
Operating Junction Temperature  
TSSOP-20  
MLP65-20  
850  
2500  
Power Dissipationa  
mW  
TSSOP-20b  
MLP65-20c  
75  
38  
Thermal Impedance (ΘJA  
)
°C/W  
Notes:  
a. Device Mounted on JEDEC compliant 1S2P test board.  
b. Derate - 14 mW/°C above 25 °C.  
c. Derate - 26 mW/°C above 25 °C.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING RANGE All voltages referenced to GND = 0 V  
Parameter  
Limit  
Unit  
VIN  
12 to 72  
V
CVIN1 || CVIN2  
VCC Operating  
CVCC  
100 µF/ESR 100 mΩ, 0.1 µF  
10 to 13.2  
4.7  
V
µF  
fOSC  
200 to 600  
24 to 72  
22 to 50  
kHz  
ROSC  
kΩ  
RBBM  
h
> 680  
pF  
nF  
CBBM  
CSS  
4.7  
0.1  
CREF  
CBOOST  
CLOAD  
0.1  
µF  
150  
0 V to VCC - 2 V  
0 V to VCC  
0 to 2.5  
Analog Inputs  
V
Digital Inputs  
Reference Voltage Output Current  
mA  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
3
Si9122  
Vishay Siliconix  
a
SPECIFICATIONS  
Test Conditions  
Limits  
Unless Otherwise Specified  
- 40 to 85 °C  
f
NOM = 500 kHz, VIN = 72 V  
Min.b  
Typ.c  
Max.b  
Unit  
VINDET = 7.2 V; 10 V VCC 13.2 V  
Parameter  
Symbol  
Reference (3.3 V)  
Output Voltage  
VREF  
ISREF  
VCC = 12 V, 25 °C Load = 0 mA  
VREF = 0 V  
3.2  
3.3  
3.4  
- 50  
- 75  
V
Short Circuit Current  
mA  
mV  
dB  
I
REF = 0 to - 2.5 mA  
at 100 Hz  
Load Regulation  
Power Supply Rejection  
Oscillator  
dVr/dir  
PSRR  
- 30  
60  
R
OSC = 30 kΩ, fNOM = 500 kHz  
Accuracy (1 % ROSC  
Max Frequencyi  
Foldback Frequencyd  
Error Amplifier  
)
- 20  
500  
20  
%
FMAX  
ROSC = 22.6 kΩ  
625  
100  
750  
kHz  
FFOBK  
fNOM = 500 kHz, VCS2 - VCS1 > 150 mV  
IBIAS  
AV  
VEP = 0 V  
Input Bias Current  
- 40  
- 15  
µA  
Gain  
- 2.2  
5
V/V  
MHz  
dB  
Bandwidth  
BW  
PSRR  
SR  
Power Supply Rejection  
Slew Rate  
at 100 Hz  
60  
0.5  
V/µs  
Current Sense Amplifier  
Input Voltage CM Range  
VCM  
VCS1 - GND, VCS2 - GND  
150  
17.5  
5
mV  
dB  
AVOL  
Input Amplifier Gain  
Input Amplifier Bandwidth  
BW  
MHz  
mV  
VOS  
Input Amplifier Offset Voltage  
CL_CONT Current  
5
dVCS = 0  
120  
0
µA  
ICL_CONT  
dVCS = 100 mV  
dVCS = 170 mV  
> 2  
mA  
IPD = IPU - ICL_CONT = 0  
See Figure 6  
VTLCL  
VTHCL  
Lower Current Limit Threshold  
100  
mV  
V
IPD > 2 mA  
Upper Current Limit Threshold  
Hysteresis  
150  
- 50  
IPU < 500 µA  
IPU = 500 µA  
CL_CONT(min)  
CL_CONT Clamp Level  
PWM Operation  
0.6  
90  
1.5  
95  
DMAX  
DMIN  
VEP = 0 V  
fOSC = 500 kHz  
92  
< 15  
3
Duty Cyclee  
VEP = 1.75 V  
%
V
CS2 - VCS1 > 150 mV  
Pre-Regulator  
+ VIN  
ILKG  
IIN = 10 µA  
Input Voltage  
72  
10  
V
VIN = 72 V, VCC > VREG  
VIN = 72 V, VINDET < VSD  
VIN = 72 V, VINDET > VREF  
Input Leakage Current  
µA  
mA  
µA  
mA  
IREG1  
IREG2  
ISOURCE  
ISINK  
86  
8
200  
14  
Regulator Bias Current  
- 29  
50  
- 19  
82  
- 9  
VCC = 12 V  
VCC < VREG  
Regulator_Comp  
110  
ISTART  
Pre-Regulator Drive Capacility  
20  
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4
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
a
SPECIFICATIONS  
Test Conditions  
Limits  
Unless Otherwise Specified  
- 40 to 85 °C  
f
NOM = 500 kHz, VIN = 72 V  
Min.b  
Typ.c  
Max.b  
Unit  
VINDET = 7.2 V; 10 V VCC 13.2 V  
Parameter  
Symbol  
Pre-Regulator  
7.4  
8.5  
9.1  
9.1  
9.2  
8.8  
8.8  
10.4  
9.7  
VREG1  
VREG2  
VINDET > VREF  
VCC Pre-Regulator Turn Off  
Threshold Voltage  
TA = 25 °C  
VINDET = 0 V  
VCC Rising  
V
7.15  
8.1  
9.8  
9.3  
VUVLO  
Undervoltage Lockout  
TA = 25 °C  
VUVLO Hysteresisg  
Soft-Start  
VUVLOHYS  
0.5  
ISS  
Soft-Start Current Output  
Start-Up Condition  
Normal Operation  
12  
20  
28  
µA  
VSS_COMP  
Soft-Start Completion Voltage  
Shutdown  
7.35  
8.05  
8.85  
V
VINDET Shutdown FN  
VSD  
VINDET Rising  
VINDET  
350  
550  
200  
720  
mV  
V
VINDET Hysteresis  
VINDET Input Threshold Voltages  
V
V
INDET - VIN Under Voltage  
UV Hysteresis  
VUV  
VINDET Rising  
VINDET  
3.13  
0.23  
3.3  
0.3  
3.46  
0.35  
Over Temperature Protection  
Activating Temperature  
TJ Increasing  
TJ Decreasing  
160  
130  
°C  
µA  
mA  
De-Activating Temperature  
Converter Supply Current (VCC  
)
ICC1  
ICC2  
ICC3  
Shutdown, VINDET = 0 V  
VINDET < VREF  
Shutdown  
50  
4
350  
12  
Switching Disabled  
Switching w/o Load  
8
VINDET > VREF, fNOM = 500 kHz  
VCC = 12 V, CDH = CDL = 3 nF  
5
10  
15  
Switching with CLOAD  
ICC4  
21  
C
SRH = CSRL = 0.3 nF  
Output MOSFET DH Driver (High-Side)  
VOH  
VBST - 0.3  
Output High Voltage  
Output Low Voltage  
Boost Current  
Sourcing 10 mA  
Sinking 10 mA  
V
mA  
A
VOL  
IBST  
ILX  
VLX + 0.3  
2.7  
VLX = 72 V, VBST = VLX + VCC  
VLX = 72 V, VBST = VLX + VCC  
1.3  
1.9  
- 0.7  
- 1.0  
1.0  
LX Current  
- 1.3  
- 0.4  
ISOURCE  
ISINK  
tr  
Peak Output Source  
Peak Output Sink  
Rise Time  
- 0.75  
VCC = 10 V  
CDL = 3 nF  
0.75  
35  
ns  
tf  
Fall Time  
35  
Output MOSFET DL Driver (Low-Side)  
VOH  
VCC - 0.3  
Output High Voltage  
Output Low Voltage  
Peak Output Source  
Peak Output Sink  
Rise Time  
Sourcing 10 mA  
Sinking 10 mA  
V
A
VOL  
ISOURCE  
ISINK  
tr  
0.3  
- 1.0  
1.0  
35  
- 0.75  
VCC = 10 V  
CDH = 3 nF  
0.75  
ns  
tf  
Fall Time  
35  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
5
Si9122  
Vishay Siliconix  
a
SPECIFICATIONS  
Test Conditions  
Limits  
Unless Otherwise Specified  
- 40 to 85 °C  
f
NOM = 500 kHz, VIN = 72 V  
Min.b  
Typ.c  
Max.b  
Unit  
VINDET = 7.2 V; 10 V VCC 13.2 V  
Parameter  
Symbol  
Synchronous Rectifier (SRH, SRL) Drivers  
VOH  
VOL  
VCC - 0.4  
Output High Voltage  
Output Low Voltage  
Sourcing 10 mA  
Sinking 10 mA  
V
0.4  
tBBM1  
tBBM2  
tBBM3  
tBBM4  
ISOURCE  
ISINK  
tr  
55  
40  
TA = 25 °C, RBBM = 33 kΩ, See Figure 3  
TA = 25 °C, RBBM = 33 kΩ, LX = 72 V  
VCC = 10 V  
Break-Before-Make Timef  
ns  
35  
55  
Peak Output Source  
Peak Output Sink  
Rise Time  
- 100  
100  
35  
mA  
ns  
CSRH = CSRL = 0.3 nF  
tf  
Fall Time  
35  
Voltage Mode  
td1DH  
td2DL  
Input to High-Side Switch Off  
Input to Low-Side Switch Off  
< 200  
< 200  
Error Amplifier  
Current Mode  
Current Amplifier  
ns  
ns  
td3DH  
td4DL  
Input to High-Side Switch Off  
Input to Low-Side Switch Off  
< 200  
< 200  
Notes:  
a. Refer to PROCESS OPTION FLOWCHART for additional information.  
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C).  
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature.  
e. Measured on SRL or SRH outputs.  
f. See figure 3 for Break-Before-Make time definition.  
g. VUVLO tracks VREG1 by a diode drop.  
h. CBBM may be required to reduce noise into BBM pin for non-optimum layout.  
i. Guaranteed by design and characterization, not tested in production.  
www.vishay.com  
6
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
TIMING DIAGRAM FOR MOS DRIVERS  
V
CC  
PWM  
PWM  
PWM  
PWM  
GND  
V
CC  
D
L
D
L
GND  
V
CC  
SR  
L
SR  
L
GND  
V
BST  
D
H
D
H
V
MID  
D
H
D
H
GND  
V
CC  
SR  
H
SR  
H
GND  
Time  
D
H
t
t
t
t
BBM4  
BST = L + V  
BBM1  
BBM2  
BBM3  
X
CC  
50 %  
V L  
X
L
X
D , L  
H
X
D , L  
V
V
H
X
MID  
SR  
H
CC  
50 %  
D , L  
H
X
GND  
t
t
BBM4  
BBM3  
D
L
SR  
L
SR  
L
V
CC  
GND  
Return to: Specification Table  
Rectification Timing Sequence  
t
t
BBM2  
BBM1  
Primary MOSFET Drivers  
Secondary MOSFET Drivers  
Figure 3.  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
7
Si9122  
Vishay Siliconix  
PIN CONFIGURATION  
Si9122DQ (TSSOP-20)  
Si9122DLP (MLP65-20)  
V
BST  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IN  
REG_COMP  
D
H
V
BST  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IN  
V
CC  
L
X
REG_COMP  
D
H
2
3
V
D
L
V
CC  
L
X
REF  
GND  
PGND  
V
D
L
4
REF  
R
SR  
H
GND  
PGND  
5
OSC  
EP  
SR  
L
R
6
SR  
H
OSC  
V
SS  
EP  
7
SR  
L
INDET  
CS1  
CS2  
BBM  
V
8
SS  
INDET  
CS1  
CS2  
BBM  
C
9
L_CONT  
C
10  
L_CONT  
Top View  
Top View  
ORDERING INFORMATION  
Lead (Pb)-free  
Part Number  
Temperature Range  
Package  
Si9122DQ-T1-E3  
Si9122DLP-T1-E3  
TSSOP-20  
MLP65-20  
- 40 °C to 85 °C  
Eval Kit  
Temperature Range  
Board Type  
Si9122DB  
Issue 3  
- 10 °C to 70 °C  
Surface Mount and Thru-Hole  
PIN DESCRIPTION  
Pin Number  
Name  
Function  
VIN  
1
2
3
4
5
6
7
Input supply voltage for the start-up circuit  
Control signal for an external pass transistor  
Supply voltage for internal circuitry  
REG_COMP  
VCC  
VREF  
3.3 V reference, decoupled with 1 µF capacitor  
Ground  
GND  
ROSC  
External resistor connection to oscillator  
Voltage control input  
EP  
VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET  
falls below preset threshold voltages and provides the feed forward voltage.  
Current limit amplifier negative input  
VINDET  
8
9
CS1  
CS2  
10  
11  
12  
13  
14  
Current limit amplifier positive input  
CL_CONT  
Current limit compensation  
BBM  
SS  
Programmable break-before-make time connection to an external resistor to set time delay  
Soft-start control - external capacitor connection  
SRL  
Signal transformer drive, sequenced with the primary side  
SRH  
15  
16  
17  
18  
19  
20  
Signal transformer drive, sequenced with the primary side  
Power ground  
PGND  
DL  
Low-side gate drive signal - primary  
LX  
DH  
High-side source and transformer connection node  
High-side gate drive signal - primary  
BST  
Bootstrap voltage to drive the high-side N-Channel MOSFET switch  
www.vishay.com  
8
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
V
CC  
V
IN  
Pre-Regulator  
+
-
V
REG  
9.1 V  
Bandgap  
Reference  
3.3 V  
9.1 V  
V
REF  
V
UVLO  
+
-
+
-
V
V
UV  
High-Side  
V
INDET  
V
REF  
8.8 V  
Primary  
C
L_CONT  
Driver  
SD  
BST  
+
-
Voltage  
Feedforward  
Frequency  
Foldback  
160 °C Temp  
Protection  
High Voltage  
Interface  
D
H
550 mV  
L
X
V
SD  
V
V
UV UVLO  
R
OSC  
OSC  
OTP  
Oscillator  
Clock  
V
CC  
Clock  
Logic  
Low-Side  
Driver  
132 kΩ  
D
L
60 kΩ  
EP  
-
+
+
Logic  
Timer  
V
/2  
REF  
PGND  
PWM  
Generator  
Current  
Control  
Gain  
V
V
CC  
Synchronous  
Driver  
CS2  
CS1  
Loop  
+
-
Control  
(High)  
SR  
H
100 mV  
Blanking  
CC  
Synchronous  
Driver  
C
L_CONT  
GND  
(Low)  
V
CC  
SR  
L
BBM  
Si9122  
20 µA  
8 V  
Soft-Start  
SS  
SS Enable  
Figure 4. Detailed Functional Block  
DETAILED OPERATION  
Start-Up  
When VINEXT rises above 0 V, the internal pre-regulator  
begins to charge up the VCC capacitor. Current into the  
external VCC capacitor is limited to typically 40 mA by the  
internal DMOS device. When Vcc exceeds the UVLO voltage  
of 8.8 V a soft-start cycle of the switch mode supply is  
initiated. The VCC supply continues to be charged by the  
pre-regulator until VCC equals VREG. During this period,  
between VUVLO and VREG, excessive load current will result  
in VCC falling below VUVLO and stopping switch mode  
operation. This situation is avoided by the hysteresis  
between VREG and VUVLO and correct sizing of the VCC  
capacitor, bootstrap capacitor and the soft-start capacitor.  
The value of the VCC capacitor should therefore be chosen  
to be capable of maintaining switch mode operation until the  
VCC can be supplied from the external circuit (e.g via a power  
transformer winding and zener regulator). Feedback from the  
output of the switch mode supply charges VCC above VREG  
and fully disconnects the pre-regulator, isolating VCC from  
VIN. VCC is then maintained above VREG for the duration of  
switch mode operation. In the event of an over voltage  
condition on VCC, an internal voltage clamp turns on at  
14.5 V to shunt excessive current to GND.  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
9
Si9122  
Vishay Siliconix  
Care needs to be taken if there is a delay prior to the external  
circuit feeding back to the VCC supply. To prevent excessive  
power dissipation within the IC it is advisable to use an  
external PNP device. A pin has been incorporated on the IC,  
(REG_COMP) to provide compensation when employing the  
external device. In this case the VIN pin is connected to the  
base of the PNP device and controls the current, while the  
REG_COMP pin determines the frequency compensation of  
the circuit. The value of the REG_COMP capacitor cannot be  
too big, otherwise it will slow down the response of the  
pre-regulator in the case that fault situations occur and  
pre-regulator needs to be turned on again. To understand  
the operation please refer to Figure 5.  
Half-Bridge and Synchronous Rectification Timing  
Sequence  
The PWM signal generated within the Si9122 controls the  
low and high-side bridge drivers on alternative cycles. A  
period of inactivity always results after initiation of the soft-  
start cycle until the soft-start voltage reaches approximately  
1.2 V and PWM controlled switching begins. The first bridge  
driver to switch is always the low-side, DL as this allows  
charging of the high-side boost capacitor.  
The timing and coordination of the drives to the primary and  
secondary stages is very important and shown in Figure 3. It  
is essential to avoid the situation where both of the  
secondary MOSFETs are on when either the high or the low-  
side switch are active. In this situation the transformer would  
effectively be presented with a short across the output. To  
avoid this, a dedicated break-before-make circuit is included  
which will generate non overlapping waveforms for the  
primary and the secondary drive signals. This is achieved by  
a programmable timer which delays the switching on of the  
primary driver relative to the switching off of the related  
secondary and subsequently delays the switching on of the  
secondary relative to the switching off of the related primary.  
The soft-start circuit is designed for the dc-dc converter to  
start-up in an orderly manner and reduce component stress  
on the IC. This feature is programmable by selecting an  
external CSS. An internal 20 µA current source charges CSS  
from 0 V to the final clamped voltage of 8 V. In the event of  
UVLO or shutdown, VSS will be held low (< 1 V) disabling  
driver switching. To prevent oscillations, a longer soft-start  
time may be needed for high capacitive loads and high peak  
output current applications.  
Reference  
Typical variation in the tBBM3 and tBBM4 delay with LX voltage  
is shown in graphs tBBM3, tBBM4 and for RBBM = 33 kΩ. This  
is due to a reduction in propagation delay through the high-  
side driver path as the LX voltage increases and must be  
considered in setting the delay for the system level design.  
Variation of BBM time with RBBM is shown in graph tBBM1 to  
The reference voltage of Si9122 is set at 3.3 V. The  
reference voltage is de-coupled externally with 0.1 µF  
capacitor. The VREF voltage is 0 V in shutdown mode and  
has 50 mA source capability.  
Voltage Mode PWM Operation  
tBBM4 vs. RBBM  
.
Under normal load conditions, the IC operates in voltage  
mode and generates a fixed frequency pulse width  
modulated signal to the drivers. Duty cycle is controlled over  
a wide range to maintain output voltage under line and load  
variation. Voltage feed forward is also included to take  
account of variations in supply voltage VIN.  
Primary High- and Low-Side MOSFET Drivers  
The drive voltage for the low-side MOSFET switch is  
provided directly from VCC. The high-side MOSFET however  
requires the gate voltage to be enhanced above VIN. This is  
achieved by bootstraping the VCC voltage onto the LX  
voltage (the high-side MOSFET source). In order to provide  
the bootstrapping an external diode and capacitor are  
required as shown on the application schematic. The  
capacitor will charge up after the low-side driver has turned  
on. The switch gate drive signals DH and DL are shown in  
Figure 3.  
In the half-bridge topology requiring isolation between output  
and input, the reference voltage and error amplifier must be  
supplied externally, usually on the secondary side. The error  
information is thus passed to the power controller through an  
opto-coupling device. This information is inverted, hence 0 V  
represents the maximum duty cycle, whilst 2 V represents  
minimum duty cycle. The error information enters the IC via  
pin EP, and is passed to the PWM generator via an inverting  
amplifier. The relationship between Duty cycle and VEP is  
shown in the Typical Characteristic Graph, Duty Cycle vs.  
VEP 25 °C , page 12. Voltage feedforward is implemented by  
taking the attenuated VIN signal at VINDET and directly  
modulating the duty cycle. The relationship between Duty  
cycle and VINDET is shown in the Typical Characteristic  
Graph, Duty Cycle vs. VINDET, page 16.  
Secondary MOSFET Drivers  
The secondary side MOSFETs are driven from the Si9122  
via a center tapped pulse transformer and inverter drivers.  
The waveforms from the IC SRH and SRL are shown in  
Figure 3. Of importance is the relative voltage between SRH  
and SRL, i.e. that which is presented across the primary of  
the pulse transformer. When both potentials of SRL and SRH  
are equal then by the action of the inverting driver both  
secondary MOSFETs are left on.  
At start-up, i.e., once VCC is greater than VUVLO, switching is  
initiated under soft-start control which increases primary  
switch on-times linearly from DMIN to DMAX over the soft-start  
period. Start-up from a VINDET power down is also initiated  
under soft-start control.  
Oscillator  
The oscillator is designed to operate at a nominal frequency  
of 500 kHz. The 500 kHz operating frequency allows the  
converter to minimize the inductor and capacitor size,  
improving the power density of the converter. The oscillator  
and therefore the switching frequency is programmable by  
attaching a resistor to the ROSC pin. Under overload  
www.vishay.com  
10  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
conditions the oscillator frequency is reduced by the current  
overload protection to enable a constant current to be  
maintained into a low impedance circuit.  
VIN Voltage Monitor - VINDET  
The chip provides a means of sensing the voltage of VIN, and  
withholding operation of the output drivers until a minimum  
voltage of VREF (3.3 V, 300 mV hysteresis), is achieved. This  
is achieved by choosing an appropriate resistive tap between  
the ground and VIN, and comparing this voltage with the  
reference voltage. When the applied voltage is greater than  
VREF, the output drivers are activated as normal. VINDET also  
provides the input to the voltage feed forward function.  
Current Limit  
Current mode control providing constant current operation is  
achieved by monitoring the differential voltage VCS between  
the CS1 and CS2 pins, which are connected to a current  
sense resistor on the primary low-side MOSFET. In the  
absence of an overcurrent condition, VCS is less than lower  
current limit threshold VTLCL (typical 100 mV); CL_CONT is  
pulled up linearly via the 120 µA current source (IPU) and  
both DL and DH switch at half the oscillator set frequency.  
When a moderate overcurrent condition occurs (VTLCL < VCS  
< VTHCL), the CL_CONT capacitor will be discharged at a rate  
that is proportional to VCS - 100 mV by the IPD current  
source. Both driver outputs are in frequency fold-back mode  
and the switching frequency becomes roughly 20 % of  
normal switching frequency. When a severe overcurrent  
condition occurs (VTHCL < VCS), the NMOS discharges  
CL_CONT capacitor immediately at 2 mA rate and the  
CL_CONT voltage will be clamped to 1.2 V disabling both DL  
and DH outputs.  
However, if the divided voltage applied to the VINDET pin is  
greater than VCC - 0.3 V, the high-side driver, DH, will stop  
switching until the voltage drops below VCC - 0.3 V. Thus, the  
resistive tap on the VIN divider must be set to accommodate  
the normal VCC operating voltage to avoid this condition.  
Alternatively, a zener clamp diode from VINDET to GND may  
also be used.  
Shutdown Mode  
If VINDET is forced below the lower threshold, a minimum of  
350 mV (VSD), the device will enter SHUTDOWN mode. This  
powers down all unnecessary functions of the controller,  
ensures that the primary switches are off and results in a low  
level current demand from the VIN or VCC supplies.  
Before VCS reaches severe overcurrent condition, a lowering  
of the CL_CONT voltage results in PWM control of the output  
drive being taken over by the current limit control loop  
through CL_CONT. Current control initially reduces the  
switching duty cycle toward the minimum the chip can reach  
(DMIN). If this duty cycle reduction still cannot lower the load  
current, then the switching frequency will start to fold back to  
minimum 1/5 of the nominal frequency. This prevents the  
on-time of the primary drivers from being reduced to below  
100 ns and avoids current tails. If VCS > VTHCL, the switching  
will then stop.  
V
INEXT  
R
EXT  
V
IN  
PNP Ext  
(Si9122)  
Auxillary  
CC  
HV  
DMOS  
V
V
CC  
REG_COMP  
EXT  
C
VCC  
0.5 µF  
C
2 nF  
14.5 V  
With constant current mode control and frequency foldback,  
protection of the MOSFET switches is increased. The  
converter reverts to voltage mode operation immediately  
when the primary current falls below the limit level, and  
CL_CONT capacitor is charged up and clamped to 6.5 V. The  
soft-start function does not apply during current limit period,  
as this would constitute hiccup mode operation.  
V
REF  
GND  
Figure 5. High-Voltage Pre-Regulator Circuit  
V
CC  
OSC  
AV  
I
PU  
120 µA (nom)  
+
-
GM  
Peak Detect  
V
C
L_CLAMP  
OFFSET  
C
R
L_CONT  
CS1  
CS2  
-
AV  
A
150 mV  
100 mV  
V
+
EXT  
Blank  
+
-
C
EXT  
GM  
I
PD  
0 to 240 µA (nom)  
A
V
Figure 6 . Current Limit Circuit  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
11  
Si9122  
Vishay Siliconix  
TYPICAL CHARACTERISTICS  
600  
3.300  
3.295  
3.290  
3.285  
3.280  
3.275  
3.270  
500  
400  
300  
200  
20  
30  
40  
50  
60  
70  
80  
- 50  
- 25  
0
25  
Temperature (°C)  
VREF vs. Temperature, VCC = 12 V  
50  
75  
100  
R
(kΩ)  
OSC  
F
vs. R  
at V  
= 12 V  
CC  
OSC  
OSC  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
10.0  
3.6 V = V  
INDET  
9.5  
9.0  
8.5  
8.0  
7.5  
4.8 V  
7.2 V  
V
INDET  
> V  
REF  
TC = - 11 mV/C  
V
CC  
= 12 V  
0.0  
0.5  
1.0  
1.5  
2.0  
- 50 - 25  
0
25  
50  
75  
100 125 150  
V
(V)  
EP  
Temperature (°C)  
VREG vs. Temperature, VIN = 48 V  
SRL, SRH Duty Cycle vs. VEP  
8.20  
8.15  
8.10  
8.05  
8.00  
7.95  
7.90  
25  
23  
21  
19  
17  
15  
V
CC  
= 13 V  
TC = + 1.25 mV/°C  
V
CC  
= 12 V  
> V  
V
INDET  
REF  
V
CC  
= 10 V  
- 50 - 25  
0
25  
50  
75  
100 125 150  
- 50  
- 25  
0
25  
Temperature (°C)  
ISS vs. Temperature  
50  
75  
100  
125  
Temperature (°C)  
VSS vs. Temperature, VCC = 12 V  
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12  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
TYPICAL CHARACTERISTICS  
11  
13  
12  
11  
10  
9
10  
9
8
7
6
8
5
7
- 50  
- 25  
0
25  
Temperature (°C)  
IREG2 vs. Temperature  
50  
75  
100  
- 50  
- 25  
0
25  
50  
75  
100  
Temperature (°C)  
ICC3 vs. Temperature  
250  
200  
150  
100  
50  
250  
V
CC  
= 12 V  
V
CC  
= 12 V  
200  
150  
100  
50  
0
0
0
200  
400  
(mV)  
600  
800  
0
200  
400  
(mV)  
600  
800  
V
V
OL  
OH  
DH, DL ISINK vs. VOL  
DH, DL ISOURCE vs. VOH  
35  
30  
25  
20  
15  
10  
5
35  
30  
25  
20  
15  
10  
5
V
CC  
= 12 V  
V
CC  
= 12 V  
0
0
0
200  
400  
(mV)  
600  
800  
0
200  
400  
(mV)  
600  
800  
V
V
OH  
OL  
SRL, SRH ISINK vs. VOL  
SRL, SRH ISOURCE vs. VOH  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
13  
Si9122  
Vishay Siliconix  
TYPICAL CHARACTERISTICS  
65  
55  
45  
35  
25  
15  
100  
t
t
BBM4  
V = 12 V  
CC  
V
CC  
= 12 V  
t
t
BBM1  
90  
80  
70  
60  
50  
40  
30  
20  
BBM1  
BBM4  
t
t
BBM2  
BBM3  
t
t
BBM3  
BBM2  
25  
30  
35  
(kΩ)  
40  
45  
25  
30  
35  
40  
45  
R
(kΩ)  
R
BBM  
BBM  
tBBM vs. RBBM, VEP = 0 V  
tBBM vs. RBBM, VEP = 1.65 V  
60  
55  
50  
45  
40  
35  
30  
80  
70  
60  
50  
40  
30  
V
= 12 V  
CC  
R
t
= 13 V  
t
= 10 V  
BBM1  
BBM1  
= 33 kΩ  
BBM  
t
= 12 V  
BBM1  
t
t
= 12  
BBM1  
= 13  
BBM1  
t
= 10 V  
BBM1  
V
= 12 V  
= 33 kΩ  
CC  
R
BBM  
t
= 10 V  
BBM2  
t
= 10 V  
t
= 12 V  
BBM2  
BBM2  
t
= 12 V  
BBM2  
t
= 13 V  
BBM2  
t
= 13 V  
BBM2  
- 50  
- 25  
0
25  
50  
75  
100  
125  
- 50  
- 25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
BBM1, 2 vs. Temperature, VEP = 1.65 V  
Temperature (°C)  
tBBM1, 2 vs. Temperature, VEP = 0 V  
t
80  
70  
60  
50  
40  
30  
20  
70  
V
= 1.65 V  
EP  
R
t
= 10 V  
V
= 0 V  
BBM  
BBM4  
EP  
R
t
= 13 V  
= 33 kΩ  
BBM4  
BBM  
= 33 kΩ  
65  
60  
55  
50  
45  
40  
35  
30  
t
= 12 V  
BBM4  
t
= 12 V  
BBM4  
t
= 10 V  
BBM4  
t
= 13 V  
BBM4  
t
= 13 V  
BBM3  
t
= 12 V  
BBM3  
t
= 10 V  
t
= 12 V  
BBM3  
BBM3  
t
= 10 V  
t
= 13 V  
BBM3  
BBM3  
- 50  
- 25  
0
25  
Temperature (°C)  
tBBM3, 4 vs. Temperature, VEP = 1.65 V  
50  
75  
100  
125  
- 50  
- 25  
0
25  
Temperature (°C)  
BBM3, 4 vs. Temperature, VEP = 0 V  
50  
75  
100  
125  
t
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14  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Si9122  
Vishay Siliconix  
TYPICAL CHARACTERISTICS  
80  
55  
50  
45  
40  
35  
t
t
= 13 V  
= 10 V  
BBM1  
t
= 13 V  
BBM1  
70  
t
= 12 V  
BBM1  
BBM1  
t
t
= 12 V  
BBM1  
BBM1  
60  
50  
40  
30  
= 10 V  
= 13 V  
V
EP  
= 0 V  
V
EP  
= 1.65 V  
t
= 12 V  
t
= 10 V  
BBM2  
BBM2  
t
BBM2  
t
= 13 V  
BBM2  
t
= 12 V  
5.5  
BBM2  
t
= 10 V  
4.5  
BBM2  
3.5  
4.5  
6.5  
7.5  
3.5  
5.5  
6.5  
7.5  
V
INDER  
(V)  
V
INDER  
(V)  
tBBM1, 2 vs. VCC vs. VINDET  
tBBM1, 2 vs. VINDET vs. VCC  
80  
70  
60  
50  
40  
30  
65  
60  
55  
50  
45  
40  
35  
30  
t
= 10 V  
BBM4  
V
= 0 V  
EP  
t
t
= 12 V  
= 13 V  
BBM4  
t
= 12 V  
t
= 10 V  
BBM4  
BBM4  
BBM4  
t
= 13 V  
BBM4  
V
= 1.65 V  
EP  
t
= 12 V  
BBM3  
t
= 10 V  
BBM3  
t
= 12 V  
BBM3  
t
= 13 V  
BBM3  
t
= 10 V  
BBM3  
t
= 13 V  
4.5  
BBM3  
3.5  
5.5  
6.5  
7.5  
3.5  
4.5  
5.5  
6.5  
7.5  
V
INDER  
(V)  
V
INDER  
(V)  
t
BBM3, 4 vs. VINDET vs. VCC  
tBBM3, 4 vs. VCC vs. VINDET  
500  
500  
400  
300  
200  
100  
0
50  
60  
50  
40  
30  
20  
10  
0
Frequency  
D%  
45  
40  
35  
30  
25  
20  
15  
10  
5
Frequency  
D%  
400  
300  
200  
D
DL  
D
SRL  
I
OUT  
100  
0
V
ROSC  
V
OUT  
0
1
2
3
4
5
0.0  
0.2  
0.4  
0.6  
(Ω)  
0.8  
1.0  
V
(V)  
R
CLCONT  
LOAD  
Current Sense Duty Cycle vs. VCLCONT  
VINDET = 7.2 V 25 °C  
IOUT vs. RLOAD (VIN = 7.2 V)  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
www.vishay.com  
15  
Si9122  
Vishay Siliconix  
TYPICAL WAVEFORMS  
SRL 10 V/div  
SRL 10 V/div  
I
5 A /div  
5 V/div  
I
5 A /div  
OUT  
OUT  
D
L
10 V/div  
D
L
CS2 5 V/div  
CS2 50 mV/div  
2 µs/div  
2 µs/div  
Figure 8. Normal Mode, RL = 0.1 Ω  
Figure 7. Foldback Mode, RL = 0.02 Ω  
V
2 V/div  
2 V/div  
CL  
V
IN  
2 V/div  
V
EP  
I
10 A/div  
OUT  
V
OUT  
2 V/div  
V
CC  
2 V/div  
200 µs/div  
2 ms/div  
Figure 10. Overload Recovery - Minimum Overshoot  
Figure 9. VCC Ramp-Up  
DH 5 V/div  
LX 20 V/div  
SRL 5 V/div  
D
L
5 V/div  
SRH 2 V/div  
SRL 2 V/div  
SRH 5 V/div  
500 ns/div  
500 ns/div  
Figure 11. Effective BBM - Measured On Secondary  
Figure 12. Drive Waveforms  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see http://www.vishay.com/ppg?71815.  
www.vishay.com  
16  
Document Number: 71815  
S-80038-Rev. J, 14-Jan-08  
Package Information  
Vishay Siliconix  
TSSOP: 20-LEAD (POWER IC ONLY)  
B
D
4X  
N
0.20  
C
H
AB  
AB  
D
D
0.20  
2X N/2 TIPS  
E
1
E
M
bbb  
C
A−B  
D
b
9
0.05  
C
A
2
E/2  
A
C
1
2 3  
aaa  
C
H
A
1
e
1.00 DIA.  
SEATING  
PLANE  
1.00  
A
D
(14_)  
SIDE VIEW  
MILLIMETERS  
Dim  
Min  
Nom  
Max  
1.10  
0.15  
0.95  
0.25  
A
A1  
A2  
aaa  
b
b1  
bbb  
c
c1  
D
E
E1  
e
L
PARTING  
LINE  
0.05  
0.85  
+
+
0.90  
0.076  
H
0.19  
0.19  
0.30  
0.25  
6
L
()  
0.22  
0.10  
c
1.00  
B
B
0.09  
0.09  
0.20  
0.16  
(14_)  
0.127  
6.50 BSC  
6.40 BSC  
4.40  
0.65 BSC  
0.60  
20  
DETAIL ‘A’  
(SCALE: 30/1)  
(VIEW ROTATED 90_ C.W.)  
4.30  
0.50  
4.50  
0.70  
C
L
N
4.2  
P
3.0  
P1  
0_  
8_  
e/2  
ECN: S-40082—Rev. A, 02-Feb-04  
DWG: 5923  
SEE  
DETAIL ‘A’  
X
X = A and B  
END VIEW  
LEAD SIDES  
TOP VIEW  
Document Number: 72818  
28-Jan-04  
www.vishay.com  
1
Package Information  
Vishay Siliconix  
PowerPAKr MLP65-18/20 (POWER IC ONLY)  
D
D/2  
NXb  
Index Area  
D/2 E/2  
M
bbb  
A
B
C
-A-  
NXb  
E/2  
E2/2  
E2  
E
2.00  
NXL  
2x  
Index Area  
D/2 E/2  
Detail D  
D2/2  
aaa  
C
D2  
TOP VIEW  
BOTTOM VIEW  
A
A3  
// ccc  
0.08  
C
C
SEATING  
PLANE  
-C-  
NX  
SIDE VIEW  
A1  
# IDENTIFIER TYPE A  
Chamber  
e/2  
e
Terminal Tip  
5
Terminal Tip  
5
e
EVEN TERMINAL SIDE  
ODD TERMINAL SIDE  
DETAIL B  
Document Number: 73182  
15-Oct-04  
www.vishay.com  
1
Package Information  
Vishay Siliconix  
PowerPAK MLP65-18/20 (POWER IC ONLY)  
N = 18/20 PITCH: 0.5 mm, BODY SIZE: 6.00 x 5.00  
MILLIMETERS*  
INCHES  
Dim  
A
A1  
Min  
Nom  
0.90  
0.02  
Max  
Min  
Nom  
Max  
Notes  
1, 2  
1, 2  
0.80  
0.00  
0.00  
1.00  
0.05  
1.00  
0.031  
0.000  
0.000  
0.035  
0.001  
0.003  
0.008 REF  
0.006  
0.010  
0.004  
0.009  
0.004  
0.236 BSC  
1.63  
0.039  
0.002  
0.004  
A2  
0.65  
1, 2  
A3  
0.20 REF  
0.15  
aaa  
b
0.18  
0.30  
0.25  
0.007  
0.012  
8
bbb  
C’  
0.10  
0.225  
0.10  
4, 10  
ccc  
D
6.00 BSC  
4.15  
1, 2  
1, 2  
1, 2  
1, 2  
D2  
4.00  
4.25  
0.157  
0.167  
E
5.00 BSC  
3.15  
0.197 BSC  
0.124  
0.020  
0.022  
18, 20  
9
E2  
3.00  
3.25  
0.118  
0.128  
e
0.50  
L
0.45  
0.55  
0.65  
0.018  
0.026  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
N
18, 20  
9
ND(18)  
NE(18)  
ND(20)  
NE(20)  
0
0
10  
10  
0
0
* Use millimeters as the primary measurement.  
ECN: S-41946—Rev. A, 18-Oct-04  
DWG: 5939  
NOTES:  
1.  
2.  
3.  
4.  
Dimensioning and tolerancing conform to ASME Y14.5M-1994.  
All dimensions are in millimeters. All angels are in degrees.  
N is the total number of terminals.  
The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SSP-022. Details of terminal #1 identifier are optional,  
but must be located within the zone indicated. A dot can be marked on the top side by pin 1 to indicate orientation.  
5.  
6.  
7.  
8.  
ND and NE refer to the number of terminals on the D and E side respectively.  
Depopulation is possible in a symmetrical fashion.  
NJR refers to NON JEDEC REGISTERED.  
Dimension “b” applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has optional radius on  
the other end of the terminal, the dimension “b” should not be measured in that radius area.  
9.  
Coplanarity applies to the exposed heat slug as well as the terminal.  
10. The 45_ chamfer dimension C’ is located by pin 1 on the bottom side of the package.  
Document Number: 73182  
15-Oct-04  
www.vishay.com  
2
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular  
product with the properties described in the product specification is suitable for use in a particular application. Parameters  
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All  
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree  
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and  
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay  
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to  
obtain written terms and conditions regarding products designed for such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
Document Number: 91000  
Revision: 11-Mar-11  
www.vishay.com  
1

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