SI9140 [VISHAY]
SMP Controller For High Performance Process Power Supplies; SMP控制器为高性能处理电源
| 型号： | SI9140 |
| 厂家： | 
VISHAY |
| 描述： | SMP Controller For High Performance Process Power Supplies |
| 文件： | 总15页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9140
Vishay Siliconix
SMP Controller For High Performance Process Power Supplies
FEATURES
• Runs on 3.3- or 5-V Supplies
• Adjustable, High Precision Output Voltage
• High Frequency Operation (>1 MHz)
• High Efficiency Synchronous Switching
• Full Set of Protection Circuitry
• 2000-V ESD Rating (Si9140CQ/DQ)
DES CRIPTION
Siliconix’ Si9140 Buck converter IC is a high-performance,
surface-mount switchmode controller made to power the new
generation of low-voltage, high-performance micro-
processors. The Si9140 has an input voltage range of 3 to
6.5 V to simplify power supply designs in desktop PCs. Its
high-frequency switching capability and wide bandwidth
feedback loop provide tight, absolute static and transient load
regulation. Circuits using the Si9140 can be implemented with
low-profile, inexpensive inductors, and will dramatically
minimize power supply output and processor decoupling
capacitance. The Si9140 is designed to meet the stringent
regulation requirements of new and future high-frequency
microprocessors, while improving the overall efficiency in new
“green” systems.
are current requirements, but operating voltages are going
down. These simultaneous changes have made dedicated,
high-frequency, point-of-use buck converters an essential part
of any system design. These point-of-use converters must
operate at higher frequencies and provide wider feedback
bandwidths than existing converters, which typically operate
at less than 250 kHz and have feedback bandwidths of less
than 50 kHz. The Si9140’s 100-kHz feedback loop bandwidth
ensures a minimum improvement of one-half the required
output/decoupling capacitance, resulting in a tremendous
reduction in board size and cost of implementation.
With the microprocessing power of any PC representing an
investment of hundreds of dollars, designers need to ensure
that the reliable operation of the processor will not be affected
by the power supply. The Si9140 provides this assurance. A
demo board, the Si9140DB, is available.
Today’s state-of-the-art microprocessors run at frequencies
over 100 MHz. Processor clock speeds are going up and so
AP P LICATION CIRCUIT
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ABS OLUTE MAXIMUM RATINGS
Voltages Referenced to GND.
Thermal Impedance (Θ )
JA
16-Pin SOIC (Y Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W
16-Pin TSSOP (Q Suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . 135°C/W
V
P
V
, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
DD
GND
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.3 V
Operating Temperature
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C
D Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° to 85°C
to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V
DD
S
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to V +0.3 V
DD
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to V +0.3 V
Notes
DD
Peak Output Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . .350 mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C above 25°C.
c. Derate 7.4 mW/°C above 25°C.
a
Power Dissipation (Package)
b
16-Pin SOIC (Y Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
16-Pin TSSOP (Q Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW
c
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause
permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be
applied at any one time.
RECOMMENDED OP ERATING RANGE
Voltages Referenced to GND.
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 V to 6.5 V
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pF to 200 pF
OSC
DD
V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 V to 6.5 V
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
S
DD
DD
f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 kHz to 2 MHz
OSC
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kΩ to 250 kΩ
V
Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >150 kΩ
OSC
REF
S P ECIFICATIONS
Limits
Test Conditions
C Suffix 0 to 70°C
D Suffix -40 to 85°C
Unless Otherwise Specifieda
3 V ≤ V ≤ 6.5 V, V = V
DD
DD
GND
S
Parameter
Reference
Symbol
Minb
Typ
Maxb
Unit
GND = P
I
= -10 µA
1.455
1.477
1.545
1.523
REF
Output Voltage
V
V
REF
T = 25°C
1.50
A
Oscillator
c
Maximum Frequency
f
f
V
= 5 V, C
= 47 pF, R = 5.0 kΩ
OSC
2.0
MAX
OSC
DD
OSC
MHz
V
= 5 V
DD
Accuracy
0.85
1.0
1.0
1.15
8
C
= 100 pF, R
= 7.50 kΩ, T = 25°C
OSC
OSC A
R
Voltage
V
V
OSC
ROSC
c
Voltage Stability
Temperature Stability
4 V ≤ V ≤ 6 V, Ref to 5 V, T = 25°C
-8
DD
A
∆f/f
%
c
Referenced to 25°C
±5
Error Amplifier (COSC = GND, OSC Disabled)
Input Bias Current
Open Loop Voltage Gain
Offset Voltage
I
V
= V
, V = 1.0 V
-1.0
47
1.0
15
µA
dB
FB
NI
REF
FB
A
55
0
VOL
V
V
= V
REF
-15
mV
MHz
OS
NI
c
Unity Gain Bandwidth
BW
10
-2.0
0.8
60
Source (V = 1 V, NI = V
)
REF
-1.0
FB
Output Current
I
mA
dB
EA
Sink (V = 2 V, NI = V
)
REF
0.4
FB
c
Power Supply Rejection
P
3 V < V < 6.5 V
DD
SRR
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S P ECIFICATIONS
Limits
C Suffix 0 to 70°C
D Suffix -40 to 85°C
Test Conditions
Unless Otherwise Specifieda
3 V ≤ V ≤ 6.5 V, V = V
DD
DD
GND
S
Parameter
Symbol
Minb
Typ
Maxb
Unit
GND = P
UVLOSET Voltage Monitor
V
V
UVLO
UVLO
High to Low
Low to High
0.85
1.0
1.2
1.15
100
UVLOHL
SET
SET
Under Voltage Lockout
V
UVLOLH
Hysteresis
V
V
V
UVLOLH - UVLOHL
175
mV
nA
HYS
UVLO(SET)
UVLO Input Current
Output Drive (DR AND DS)
Output High Voltage
Output Low Voltage
Peak Output Current
Peak Output Current
Break-Before-Make
Logic
I
V
= 0 to V
-100
4.7
UVLO
DD
V
V
= V = 5 V, I
= -10 mA
= V = 5 V, I = 10 mA
OUT
4.8
0.2
OH
S
DD
OUT
V
V
V
0.3
OL
SOURCE
S
DD
I
V
V
= V = 5 V, V
= 0 V
= 5 V
-380
300
40
-260
S
S
DD
OUT
OUT
mA
nS
I
= V = 5 V, V
200
SINK
DD
t
V
= 6.5 V
BBM
DD
ENABLE Turn-On Delay
ENABLE Logic Low
ENABLE Logic High
ENABLE Input Current
t
ENABLE Delay to Output, EN , V = 5 V
1.5
µs
V
dEN
LH
DD
V
0.2 V
DD
ENL
ENH
V
0.8 V
DD
I
ENABLE = 0 to V
-1.0
1.0
45
1
µA
EN
DD
VGOOD Comparator (Voltage-Good Comparator)
Input Offset Voltage
Input Hysteresis
V
-45
0
10
0
OS
V
Common Mode Voltage = V , V = 5 V
mV
IN
REF DD
V
INHYS
BMON
Input Bias Current
Output Sink I
I
V
= V , V = 5 V
-1
6
µA
mA
mV
IN
REF DD
I
V
= 5 V, V = 5 V
9
SINK
OUT
DD
Output Low Voltage
Supply
V
I
= 2 mA, V = 5 V
350
500
OL
OUT
DD
Supply Current-Normal Mode
Supply Current-Standby Mode
f
= 1 MHz, R
= 7.50 kΩ
OSC
1.6
2.3
mA
µA
OSC
I
DD
ENABLE < 0.4 V
250
330
Notes
a. 100 pF includes C
on C
.
OSC
STRAY
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Guaranteed by design, not subject to production testing.
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TYP ICAL CHARACTERIS TICS (2 5 °C UNLES S OTHERWIS E NOTED)
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TYP ICAL CHARACTERIS TICS (2 5 °C UNLES S OTHERWIS E NOTED)
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TYP ICAL CHARACTERIS TICS (2 5 °C UNLES S OTHERWIS E NOTED)
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P IN CONFIGURATIONS
ORDERING INFORMATION
ORDERING INFORMATION
Temperature Range
Part Number
Temperature Range
Part Number
0° to 70°C
Si9140CY
Si9140DY
0° to 70°C
Si9140CQ
Si9140DQ
-40° to 85°C
-40° to 85°C
P IN DES CRIP TION
Pin 1: VDD
Pin 5: FB
The inverting input of the error amplifier. An external resistor
divider is connected to this pin to set the regulated output
voltage. The compensation network is also connected to this
pin.
The positive power supply for all functional blocks except
output driver. A bypass capacitor of 0.1 µF (minimum) is
recommended.
Pin 2: MON
Pin 6: NI
Non-inverting input of a comparator. Inverting input is tied
internally to reference voltage. This comparator is typically
used to monitor the output voltage and to flag the processor
when the output voltage falls out of regulation.
The non-inverting input of the error amplifier. In normal
operation it is externally connected to VREF or an external
reference.
Pin 7: VREF
Pin 3: VGOOD
This pin supplies a 1.5-V reference.
This is an open drain output. It will be held at ground when
the voltage at MON (Pin 2) is less than the internal reference.
An external pull-up resistor will pull this pin high if the MON
Pin 8: GND (Ground)
pin (Pin 2) is higher than the VREF
.
(Refer to Pin 2
description.)
Pin 9: ENABLE
A logic high on this pin allows normal operation. A logic low
places the chip in the standby mode. In standby mode normal
operation is disabled, supply current is reduced, the oscillator
stops and DS goes high while DR goes low.
Pin 4: COMP
This pin is the output of the error amplifier. A compensation
network is connected from this pin to the FB pin to stabilize
the system. This pin drives one input of the internal pulse
width modulation comparator.
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Pin 10: ROSC
Pin 13: PGND
A resistor connected from this pin to ground sets the
oscillator’s capacitor COSC, charge and discharge current.
See the oscillator section of the description of operation.
The negative return for the VS supply.
Pin 14: DS
This CMOS push-pull output pin drives the external p-channel
Pin 11: COSC
MOSFET. This pin will be high in the standby mode.
break-before-make function between DS and DR is built-in.
A
An external capacitor is connected to this pin to set the
oscillator frequency.
Pin 15: DR
0.75
OSC × COSC
-----------------------------------
fOSC
(at VDD = 5.0 V)
R
This CMOS push-pull output pin drives the external n-channel
MOSFET. This pin will be low in the standby mode.
A
break-before-make function between the DS and DR is built-in.
Pin 12: UVLOSET
Pin 16: VS
This pin will place the chip in the standby mode if the
UVLOSET voltage drops below 1.2 V. Once the UVLOSET
voltage exceeds 1.2 V, the chip operates normally. There is a
built-in hysteresis of 165 mV.
The positive terminal of the power supply which powers the
CMOS output drivers. A bypass capacitor is required.
FUNCTIONAL BLOCK DIAGRAM
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TIMING WAVEFORMS
DES CRIPTION OF OP ERATION
Schematics of the Si9140 dc-to-dc conversion solutions for
high-performance PC microprocessors are shown in Figure 1
and 2 respectively. These solutions are geared to meet the
extremely demanding transient regulation and power
requirements of these new microprocessors at minimal cost
and with a minimal parts count. The two solutions are nearly
identical, except for slight variations in output voltage, load
transient amplitude, and specified power. Figure 3 is a
schematic diagram for a 3.3-V logic converter.
FIGURE 1. 2.9 V @ 10 A
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FIGURE 2. 2.5 V @ 8.5 A
FIGURE 3. 3.3 V @ 5 A
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FIGURE 4. 1.5-V Converter for GTL+ Bus @ 5 A
Figure 4 is a schematic diagram of a converter which
produces 1.5 V for a GTL bus.
(first-order RC system). Current mode has the advantage of
providing an inherently good line regulation. But the
situations where line voltage is fixed, as in the point-of-use
conversion for microprocessors, this feature is wasted.
Current mode control also provides automatic pulse-to-pulse
current limiting. This feature requires a current sense resistor
as stated above. These characteristics make voltage mode
control ideal for high-end microprocessor power supplies.
Each of these dc-to-dc converters has four major sections:
• PWM Controller-regulates the output voltage
• Switch and Synchronous Rectification MOSFETs-delivers
the power to the load
• Inductor-filters and stores the energy
• Input/Output Capacitor-filters the ripple
The functions of each circuit are explained in detail below.
Design equations are provided to optimize each application
circuit.
P WM CONTROLLER
There are generally two types of controllers, voltage mode or
current mode. In voltage mode control, an error voltage is
generated by comparing the output voltage to the reference
voltage. The error voltage is then compared to an artificial
ramp, and the result is the duty cycle necessary to regulate
the output voltage. In current mode, an actual inductor
current is used, in place of the artificial ramp, to sense the
voltage across the current sense resistor.
The logic and timing sequence for voltage mode control is
shown in Figure 5. The Si9140 offers voltage mode control,
which is better suited for applications requiring both fast
transient response and high output current.
FIGURE 5. Voltage Mode Logic and Timing Diagram
The error amplifier of the PWM controller plays a major role in
determining the output voltage, stability, and the transient
Current mode control requires a current sense resistor to
monitor the inductor current. A 10-mΩ sense resistor in a 10-A
design will dissipate 1 W, decreasing efficiency by 3.5%.
Such a design would require a 2-W resistor to satisfy derating
criteria, besides requiring additional board space. Voltage
mode control is a second-order LC system and has a faster
natural transient response compared to current mode control
response of the power supply.
In the Si9140, the
non-inverting input of the error amplifier is available for use
with an external precision reference for tighter tolerance
regulation. With a two-pair lead-lag compensation network, it
is easy to create a stable 100-kHz closed loop converter with
the Si9140 error amplifier.
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The Si9140 achieves the 5-µS transient response by
generating a 100-kHz closed-loop bandwidth. This is possible
only by switching above 400 kHz and utilizing an error
amplifier with at least a 10-MHz bandwidth. The Si9140
controller has a 25-MHz unity gain bandwidth error amplifier.
The switching frequency must be at least four times greater
than the desired closed-loop bandwidth to prevent oscillation.
To respond to the stimuli, the error amplifier bandwidth needs
to be at least 10 times larger than the desired bandwidth.
Figure 7 is the measured transient response (time domain) for
the 10-A step response. The measured transient response
shows the processor voltage regulating to 70 mV, well within
the 0.145-V regulation.
The Si9140’s switching frequency is determined by the
external ROSC and COSC values, allowing designers to set the
switching frequency of their choice. For applications where
space is the main constraint, the switching frequency can be
set as high as 2 MHz to minimize inductor and output
capacitor size. In applications where efficiency is the main
concern, the switching frequency can be set low to maximize
battery life. The switching frequency for high-performance
processors applications circuits are set for 400 kHz. The
equation for switching frequency is:
0.75
OSC × COSC
-----------------------------------
fOSC
≈
(at VDD = 5.0 V)
R
The precision reference is set at 1.5 V ± 1.5%. The reference
is capable of sourcing up to 1 mA. The combination of 1.5%
reference and 3.5% transient load regulation safely complies
with the ±5% regulation requirement. If additional margin is
desired, an external precision reference can be used in place
of the internal 1.5-V reference.
FIGURE 6. 100-kHz BW Synchronous Buck Converter
S WITCHING AND S YNCHRONOUS
RECTIFICATION MOS FETS
The Si9140 solution requires only three 330-µF OS-CON
capacitors on the output of power supply to meet the 10-A
transient requirement. Other converter solutions on the
market with 20- to 50-kHz closed loop bandwidths typically
require two to five times the output capacitance specified
above to match the Si9140’s performance.
The synchronous gate drive outputs of Si9140 PWM controller
drive the high-side p-channel switch MOSFET and the
low-side n-channel synchronous rectifier MOSFET. The
physical difference between the non-synchronous to
synchronous rectification requires an additional MOSFET
across the free-wheeling diode (D1). The inductor current will
reach 0 A if the peak-to-peak inductor current equals twice the
output current. In synchronous rectification mode, current is
allowed to flow backwards from the inductor (L1) through the
synchronous MOSFET (Q3) and to the output capacitors (C2)
once the current reaches 0 A. Refer to schematic on
Figure 1. In non-synchronous rectification, the diode (D1)
prevents the current from flowing in the reverse direction. This
minor difference has a drastic affect on the performance of a
power supply. By allowing the current to flow in the reverse
direction, it preserves the continuous inductor current mode,
maintaining the wide converter bandwidth and improving
efficiency. Also, maintaining the continuous current mode
during light load to full load guarantees consistent transient
response throughout a wide range of load conditions.
The theoretical issues and analytical steps involved in
compensating a feedback network are beyond the scope of
this application note. However, to ease the converter design
for today’s high-performance microprocessors, typical
component values for the feedback network are provided in
Table 1 for various combinations of output capacitance.
Figure 6 shows the Bode plot (frequency domain) of the 2.9-V
converter shown schematically in Figure 1.
TABLE 1. Feedback Network Component Values
Total Output and
Decoupling Capacitance
C4
C5
R5
3 x 330 µFa . . . . . . . . . . .Os-con
6 x 100 µFb . . . . . . . . . . .Tantalum
25 x 1 µFb . . . . . . . . . . . .Ceramic
5.6 pF
180 pF
240 k
2 x 330 µFa . . . . . . . . . . .Os-con
4 x 100 µFb . . . . . . . . . . .Tantalum
25 x 1 µFb . . . . . . . . . . . .Ceramic
10 pF
10 pF
220 pF
100 pF
200 k
100 k
3 x 330 µFa . . . . . . . . . . .Tantalum
4 x 100 µFb . . . . . . . . . . .Tantalum
25 x 1 µFb . . . . . . . . . . . .Ceramic
Notes:
a. Power supply output capacitance.
b. µprocessor decoupling capacitance.
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The transition from stop clock and auto halt to active mode is
a perfect example. The microprocessor current can vary from
0.5 A to 10 A or greater during these transitions. If the
converter were to operate in discontinuous current mode
during the stop clock and auto halt modes, the transfer
function of the converter would be different compared to
operation in the active mode. In discontinuous current mode,
the converter bandwidth can be 10 to 15 times lower than the
continuous current mode (Figure 8). Therefore, the response
time will also be 10 to 15 times slower, violating the
microprocessor’s regulator requirements. This could result in
unreliable operation of the microprocessor.
FIGURE 7.
For these reasons, synchronous rectification is a must in
today’s microprocessors power supply design. Pulse-
skipping modes are undesirable in high-performance
microprocessor power supplies, especially when the minimum
load current is as high as 500 mA. This pulse-skipping mode
disables the synchronous rectification during light load and
generates a random noise spectrum which may produce EMI
problems.
Siliconix’ TrenchFET™ technology has resulted in 20-mΩ
n-channel (Si4410DY) and 35-mΩ p-channel (Si4435DY)
MOSFETs in the SO-8 surface-mount package. These
LITTLE FOOT® products totally eliminate the need for an
external heatsink.
FIGURE 8. Non-Synchronous Converter BW
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Worst case current of 10 A can be handled with two paralleled
Si4435DY and two paralleled Si4410DY MOSFETs, which
results in the efficiency levels shown in Figure 9.
Good electrical designs must provide an adequate margin for
the specification, but they should not be grossly overdesigned
to lower costs. LITTLE FOOT power MOSFETs allow
designers to balance cost and performance considerations
without sacrificing either. If the design requires only an 8.5-A
continuous current, for example, one Si4410DY can be
eliminated. Table 2 shows the number of MOSFETs required
to handle the various output current levels of today’s high-
performance microprocessors. For other output power levels,
the equations below should be used to calculate the power
handling capability of the MOSFET.
FIGURE 9. Efficiency
TABLE 2. Converter Requirements Figure 1, 2, and 3)
IO (A)
Maximum
Quantity High-side
P-Channel SI4435DY
Quantity Low-side
N-Channel SI4410DY
Quantity Input (C1-C3)
Capacitor OS-CON 220 µF
5 A
8.5 A
10 A
1
2
2
3
1
1
2
2
1
2
2
3
14.5 A
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Q
SW × VIN × fOSC
I
PP × VO × τC × fOSC
PDissipation in switch = IRMS SW2 × RSW + --------------------------------------------- + ----------------------------------------------------
2
2
VO
(IPEAK2 + IPP2 + IPEAK × IPP) ×
------------------
IRMS SW
=
3 × VIN
Q
RECT × VIN × fOSC
PDissipation in synchronous rectification = IRMS RECT2 × RRECT + ---------------------------------------------------
2
V
IN – VO
(IPEAK2 + IPP2 + IPEAK × IPP) ×
----------------------
IRMS RECT
=
3 × VIN
IPP = IPEAK + ∆I
I
R
I
R
Q
Q
V
V
I
f
η
=
=
=
=
=
=
=
=
=
=
=
=
Switch rms current
Switch on resistance
RMSSW
SW
Synchronous rectifier rms current
Synchronous rectifier on resistance
Total gate charge of switch
Total gate charge of synchronous rectifier
Input voltage
Output voltage
Output current
Switching frequency
efficiency
2
RMSRECT
VO
∆I = ------------------------------------
L × fOSC × VIN
RECT
SW
RECT
IN
P
IN – (0.5 × VO × ∆I)
IPEAK = -----------------------------------------------------
O
VO
O
OSC
V
O × IO
PIN = ------------------
τ
Crossover time
C
η
Current
I
O
I
PP
I
PEAK
0 A
time
frequency, but the core size is fairly large. If the power supply
is designed on the motherboard and space is not a critical
issue, ferrite is a better choice.
INDUCTOR
The size and value of the inductor are critical in meeting
overall circuit dimensional requirements and in assuring
proper transient voltage regulation. The size of the core is
determined by the output power, the material of the core, and
the operating frequency. To handle higher output power, the
core must be larger. Luckily, a higher switching frequency will
lower the inductance value, decreasing the core size.
However, a higher switching frequency can also mean greater
core loss.
The higher switching frequency reduces the core size by
decreasing the amount of energy that must be stored between
switching periods. It also accelerates the transient response
to the load by decreasing the inductance value. The
inductance is calculated with following equation:
2
VO
L = --------------------------------------
V
IN × ∆I × fOSC
In applications where the dc flux density is high and the ac
flux density swing is only 100 to 200 gauss, the core loss will
be negligible compared to the wire loss. Kool Mu is the best
material to use at 500 kHz to deliver 30 W in the minimum
volume. Ferrite has a lower core cost and loss at this
∆I = desired output current ripple. Typically ∆I = 25% of
maximum output current.
FaxBack 408-970-5600, request 70026
S-58034—Rev. G, 15-Mar-99
www.siliconix.com
15
相关型号：
SI9140DY-T1
IC 0.35 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16, SOIC-16, Switching Regulator or Controller
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