SI9166 [VISHAY]

High Frequency Programmable Topology Controller; 高频可编程控制器拓扑


型号：	SI9166
厂家：	VISHAY
描述：	High Frequency Programmable Topology Controller 高频可编程控制器拓扑控制器
文件：	总8页 (文件大小：211K)
中文：	中文翻译
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Si9166

New Product

Vishay Siliconix

Si9166

High Frequency Programmable Topology Controller

FEATURES

• Buck or Boost Configuration

• Voltage Mode Control

• Integrated UVLO and POR

• Integrated Soft-Start

• Synchronization

• 2.7-V to 6-V Input Voltage Range for V_DDand V_S

• Programmable PWM/PSM Control

– Up to 2-MHz Switching Frequency in PWM

– Synchronous Rectification in PWM

– Less than 200-µA I_DDin PSM

• Shutdown Current <1 µA

DESCRIPTION

The Si9166 is a programmable topology controller for today’s

continuous changing portable electronic market. Si9166

provides flexibility of utilizing various battery configurations

and chemistries such as NiCd, NiMhy, or Li+ with input

voltage range of 2.7 V to 6 V. An additional flexibility is

provided with topology programmability to power multiple

loads such as power amplifiers, microcontrollers, or baseband

logic IC’s. The converters can be programmed to be

synchronous Buck or Boost topology. For ultra-high efficiency,

converters are designed to operate in synchronous rectified

PWM mode under full load while transforming into externally

controlled pulse skipping mode (PSM) under light load. All

these features are provided by the Si9166 without sacrificing

system integration requirements of fitting these circuits into

ever demanding smaller and smaller space. The Si9166 is

capable of switching up to 2 MHz to minimize the output

inductor and capacitor size in order to decrease the overall

converter size.

The Si9166 is available in TSSOP-16 pin package and

specified to operate over the industrial temperature range of

-25°C to 85°C.

TYPICAL APPLICATION CIRCUIT

FaxBack 408-970-5600, request 70847

S-60752—Rev. B, 05-Apr-99

www.siliconix.com

Si9166

Vishay Siliconix

New Product

ABSOLUTE MAXIMUM RATINGS

Voltages Referenced to GND

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C

MODE, PWM/PSM, SYNC, SD, V , R

COMP, FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V

Power Dissipation (Package)

REF OSC

+ 0.3 V

16-Pin TSSOP (Q Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V + 0.3 V

Thermal Impedance (θ )

16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135°C/W

PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Notes

Voltages Referenced to PGND

a. Device mounted with all leads soldered or welded to PC board.

b. Derate 7.4 mW/°C above 25°C.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V

DH, DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V + 0.3 V

Peak Output Current (DH, DL) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Voltages Referenced to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 kHz to 2 MHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kΩ to 300 kΩ

Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 µF

osc

MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . 0 V to V

Voltages Referenced to PGND

osc

REF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V

SPECIFICATIONS

Limits

Test Conditions

Unless Otherwise Specified

-25°C to 85°C

Parameter

Reference

Symbol

Min^a

Typ^b

Max^a

Unit

2.7 V ≤ V , V ≤ 6 V

= 0A

1.268

1.280

1.3

1.332

1.320

REF

Output Voltage

REF

= 0, T = 25°C

REF

Load Regulation

Power Supply Rejection

UVLO

∆V

= 3.3 V, -500 µA < I <0

REF

SRR

Under Voltage Lockout

(turn-on)

2.3

2.4

0.1

2.5

UVLOLH

Hysteresis

- V

HYS

UVLOLH UVLOHL

Soft-start Time

SS time

tss

Mode

Logic High

0.7 V

Logic Low

0.3 V

Input Current

SD, SYNC, PWM/PSM

Logic High

-1.0

2.4

1.0

µA

Logic Low

0.8

1.0

Input Current

-1.0

µA

S-60752—Rev. B, 05-Apr-99

FaxBack 408-970-5600, request 70847

www.siliconix.com

Si9166

New Product

Vishay Siliconix

SPECIFICATIONS

Limits

-25°C to 85°C

Test Conditions

Unless Otherwise Specified

Parameter

Symbol

Min^a

Typ^b

Max^a

Unit

2.7 V ≤ V , V ≤ 6 V

Oscillator

Maximum Frequency

Accuracy

MHz

OSC

Nominal 1.60 MHz, R

= 30 kΩ

-20

OSC

Maximum Duty Cycle—

Buck

= 2 MHz (non LDO mode)

MAX

Maximum Duty Cycle—

Boost

= 2 MHz

SYNC Range

1.2

1.5

SYNC OSC

SYNC Low Pulse Width

SYNC High Pulse Width

SYNC t , t

Error Amplifier

Input Bias Current

= 1.4 V

-1

µA

BIAS

Open Loop Voltage Gain

1.30

VOL

T = 25°C

1.270

1.258

1.330

1.342

FB Threshold

Unity Gain BW

MHz

Source (V = 1.05 V), V

COMP

-3

-1

0.75 V

Output Current

Sink (V = 1.55 V), V

= 0.75 V

COMP

Power Supply Rejection

Output Drive (DH and DL)

Output High Voltage

Output Low Voltage

Peak Output Source

Peak Output Sink

Break-Before-Make

Supply

PSRR

= 3.3 V, I

= -20 mA

= 3.3 V, I = 20 mA

OUT

3.18

500

3.24

0.06

-750

750

OUT

0.12

-500

SOURCE

= 3.3 V, DH = DL = V /2

SINK

V = V = 3.3 V

S DD

BBM

Normal Mode

= 3.3 V, F

= 2 MHz

500

180

750

250

OSC

PSM Mode

= 3.3 V

µA

Shutdown Mode

= 3.3 V, SD = 0 V

Notes

a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.

b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

FaxBack 408-970-5600, request 70847

S-60752—Rev. B, 05-Apr-99

www.siliconix.com

Si9166

Vishay Siliconix

New Product

TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)

S-60752—Rev. B, 05-Apr-99

FaxBack 408-970-5600, request 70847

www.siliconix.com

Si9166

New Product

Vishay Siliconix

TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)

PIN CONFIGURATION

ORDERING INFORMATION

Part Number

Temperature Range

Package

Si9166BQ-T1

-25 to 85°C

Tape and Reel

Eval Kit

Temperature Range

Board Type

Si9166DB

-25 to 85°C

Surface Mount

PIN DESCRIPTION

Symbol

Description

Input supply voltage for the output driver section. Input voltage range is 2.7 V to 6V

Not Used

N/C

The gate drive output for the high-side p-channel MOSFET. The p-channel MOSFET is the main switch for

buck topology and the synchronous rectifier for the boost topology.

PWM/PSM

SYNC

GND

Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled.

Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If

not used, the pin must be connected to V , or logic high.

Low power controller ground

1.3-V reference. Decoupled with 0.1-µF capacitor

Output voltage feedback connected to the inverting input of an error amplifier.

Error amplifier output for external compensation network.

External resistor to determine the switching frequency.

Input supply voltage for the analog circuit. Input voltage range is 2.7 V to 6 V.

Direct output voltage sense

REF

COMP

OSC

PGND

Power ground for output drive stage

The gate drive output for the low-side n-channel MOSFET. The n-channel MOSFET is the synchronous

rectifier for the buck topology and the main switch for the boost topology.

Shuts down the IC completely and decreases current consumed by the IC to < 1 µA.

MODE

Determines the converter topology. Connect to AGND for Buck or V for Boost.

FaxBack 408-970-5600, request 70847

S-60752—Rev. B, 05-Apr-99

www.siliconix.com

Si9166

Vishay Siliconix

New Product

FUNCTIONAL BLOCK DIAGRAM

DETAIL OPERATIONAL DESCRIPTION

Start-Up

Note that the Si9166 will always soft start in the PWM mode

regardless of the voltage level on the PWM/PSM pin.

The UVLO circuit prevents the controller output driver and

oscillator circuit from turning on, if the voltage on V_DDpin is

less than 2.5 V. With typical UVLO hysteresis of 0.1 V,

controller is continuously powered on until the V_DDvoltage

drops below 2.4 V. This hysteresis prevents the converter

from oscillating during the start-up phase and unintentionally

locking up the system. Once the V_DDvoltage exceeds the

UVLO threshold, and with no other shutdown condition

detected, an internal power-on-reset timer is activated while

most circuitry, except the output driver, are turned on. After

the POR time-out of about 1 ms, the internal soft-start

capacitor is allowed to charge. When the soft-start capacitor

voltage reaches 0.5 V, the PWM circuit is enabled.

Thereafter, the constant current charging the soft-start

capacitor will force the converter output voltage to rise

gradually without overshooting. To prevent negative

undershoot, the synchronous switch is tri-stated until the duty

cycle reaches about 10%. In tri-state, the high-side p-channel

MOSFET is turned off by pulling up the gate voltage (DH) to

V_Spotential. The low-side n-channel MOSFET is turned off

by pulling down the gate voltage (DL) to PGND potential.

Shutdown

The Si9166 is designed to conserve battery life by decreasing

current consumption of IC during normal operation as well as

the shutdown mode. With logic low-level on the SD pin,

current consumption of the Si9166 decreases to less than

1 µA by shutting off most of the circuits. The logic high

enables the controller and starts up as described in Start-Up

section above.

MODE Selection

The Si9166 can be programmed to operate as Buck or Boost

converter. If the MODE pin is connected to AGND, it operates

in buck mode. If the MODE pin is connected to V_DD, it

operates in boost mode. The DH gate drive output is

designed to drive high-side p-channel MOSFET, acting as the

main switch in buck topology and the synchronous rectifier in

boost topology. The DL gate drive output is designed to drive

low-side n-channel MOSFET, acting as the synchronous

rectifier in buck topology and the main switch in boost

topology.

S-60752—Rev. B, 05-Apr-99

FaxBack 408-970-5600, request 70847

www.siliconix.com

Si9166

New Product

Vishay Siliconix

PWM Mode

Pulse Skipping Mode

With PWM/PSM mode pin in logic high condition, the Si9166

operates in constant frequency (PWM) mode. As the load

and line varies, switching frequency remain constant. The

switching frequency is programmed by the R_OSCvalue. In the

PWM mode, the synchronous drive is always enabled, even

The gate charge losses produced from the Miller capacitance

of MOSFETs are the dominant power dissipation parameter

during light load (i.e. < 10 mA). Therefore, less gate switching

will improve overall converter efficiency. This is exactly why

the Si9166 is designed with pulse skipping mode. If the

PWM/PSM pin is connected to logic low level, converter

operates in pulse skipping modulation (PSM) mode. During

the pulse skipping mode, quiescent current of the controller is

decreased to approximately 200 µA, instead of 500 µA during

the PWM mode. This is accomplished by turning off most of

internal control circuitry and utilizing a simple constant on-

time control with feedback comparator. The controller is

designed to have a constant on-time and a minimum off-time

acting as the feedback comparator blanking time. If the output

voltage drops below the desired level, the main switch is first

turned on and then off. If the applied on-time is insufficient to

provide the desired voltage, the controller will force another on

and off sequence, until the desired voltage is accomplished. If

the applied on-time forces the output to exceed the desired

level, as typically found in the light load condition, the

converter stays off. The excess energy is delivered to the

output slowly, forcing the converter to skip pulses as needed

to maintain regulation. The on-time and off-time are set

internally based on inductor used (1.5-µH typical), MODE pin

selection and maximum load current. Therefore, with this

control method, duty cycle ranging from 0 to near 100% is

possible depending on whether buck or boost is chosen. In

pulse skipping mode, synchronous rectifier drive is also

disabled to further decrease the gate charge loss and

increase overall converter efficiency.

when the output current reaches 0 A.

Therefore, the

converter always operates in continuous conduction mode

(CCM) if a synchronous switch is used. In CCM, transfer

function of the converter remains almost constant, providing

fast transient response.

If the converter operates in

discontinuous conduction mode (DCM), overall loop gain

decreases and transient response time can be ten times

longer than if the converter remain in continuous current

mode.

This transient response time advantage can

significantly decrease the hold-up capacitors needed on the

output of dc/dc converter to meet the transient voltage

regulation. The PWM/PSM pin is available to dynamically

program the controller. If the synchronous rectifier switch is

not used, the converter will operate in DCM at light load.

The maximum duty cycle of the Si9166 can reach 100% in

buck mode. The duty cycle will continue to increase as the

input voltage decreases until it reaches 100%. This allows the

system designers to extract the maximum stored energy from

the battery. Once the controller delivers 100% duty cycle, the

converter operates like a saturated linear regulator. At 100%

duty cycle, synchronous rectification is completely turned off.

Up to 80% maximum duty cycle at 2-MHz switching

frequency, the controller maintains perfect output voltage

regulation. If the input voltage drops below the level where

the converter requires greater than 80% duty cycle, the

controller will deliver 100% duty cycle. This instantaneous

jump in duty cycle is due to fixed BBM time, MOSFET delay/

rise/fall time, and the internal propagational delays. In order to

maintain regulation, controller might fluctuate its duty cycle

back and forth from 100% to something lower than 80% while

the converter is operating in this input voltage range. If the

input voltage drops further, controller will remain on 100%. If

the input voltage increases to a point where it’s requiring less

than 80% duty cycle, synchronous rectification is once again

activated.

Reference

The reference voltage for the Si9166 is set at 1.3 V. The

reference voltage is internally connected to the non-inverting

inputs of the error amplifier. The reference pin requires 0.1-µF

decoupling capacitor.

Error Amplifier

The error amplifier gain-bandwidth product and slew rate are

critical parameters which determines the transient response

of converter. The transient response is function of both small

and large signal responses. The small signal response is

determined by the feedback compensation network while the

large signal is determined by the error amplifier dv/dt and the

inductor di/dt slew rate. Besides the inductance value, error

amplifier determines the converter response time. In order to

minimize the response time, the Si9166 is designed with

2-MHz error amplifier gain-bandwidth product to generate the

widest converter bandwidth and 3.5 V/µsec slew rate for

ultra-fast large signal response.

The maximum duty cycle under boost mode is internally

limited to 70% to prevent inductor saturation. If the converter

is turned on for 100% duty cycle, inductor never gets a chance

to discharge its energy and eventually saturate. In boost

mode, synchronous rectifier is always turned on for minimum

or greater duration as long as the switch has been turned on.

The controller will deliver 0% duty cycle, if the input voltage is

greater than the programmed output voltage. Because of

signal propagation time and MOSFET delay/rise/fall time,

controller will not transition smoothly from minimum

controllable duty cycle to 0% duty cycle. For example,

controller may decrease its duty cycle from 5% to 0% abruptly,

instead of gradual decrease you see from 70% to 5%.

FaxBack 408-970-5600, request 70847

S-60752—Rev. B, 05-Apr-99

www.siliconix.com

Si9166

Vishay Siliconix

New Product

Oscillator

Break-Before-Make Timing

The oscillator is designed to operate up to 2-MHz minimal.

The 2-MHz operating frequency allows the converter to

minimize the inductor and capacitor size, improving the power

A proper BBM time is essential in order to prevent shoot-

through current and to maintain high efficiency. The break-

before-make time is set internally at 20 to 60 ns @ V_S= 3.6 V.

The high- and low-side gate drive voltages are monitored and

when the gate to source voltage reaches 1.75 V above or

below the initial starting voltage, 20 to 60 ns BBM time is set

before the other gate drive transitions to its proper state. The

maximum and minimum duty cycle is limited by the BBM time.

Since the BBM time is fixed, controllable maximum duty cycle

will vary depending on the switching frequency.

density of the converter.

Even with 2-MHz switching

frequency, quiescent current is only 500 µA with unique power

saving circuit design. The switching frequency is easily

programmed by attaching resistor to R_OSCpin. See oscillator

frequency versus R_OSCcurve to select the proper timing

values for desired operating frequency. The tolerance on the

operating frequency is (20% with 1% tolerance resistor).

Synchronization

Output Driver Stage

The synchronization to external clock is easily accomplished

by connecting the external clock into the SYNC pin. The logic

high-to-low transition synchronizes the clock. The external

clock frequency must be within 1.2 to 1.5 times the internal

clock frequency.

The DH pin is designed to drive the high-side p-channel

MOSFET, independent of topology. The DL pin is designed to

drive the low-side n-channel MOSFET, independent of

topology. The driver stage is sized to sink and source peak

currents up to 450 mA with V_S= 3.3 V. The ringing from the

gate drive output trace inductance can produce negative

voltage on the DH and DL respect to PGND. The gate drive

circuit is capable of withstanding these negative voltages

without any functional defects.

S-60752—Rev. B, 05-Apr-99

FaxBack 408-970-5600, request 70847

www.siliconix.com

SI9166 [VISHAY]

相关型号：

SI9166BQ-T1

SI9166BQ-T1-E3

SI9166DB

SI9166_04

SI9167

SI9168

SI9168BQ-T1

SI9168BQ-T1-E3

SI9169

SI9169-T1

SI9169BQ-T1

SI9169BQ-T1-E3