SIA419DJ [VISHAY]
P-Channel 20-V (D-S) MOSFET; P通道20 -V （D -S ）的MOSFET
| 型号： | SIA419DJ |
| 厂家： | 
VISHAY |
| 描述： | P-Channel 20-V (D-S) MOSFET |
| 文件： | 总4页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SiA419DJ
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 74896
S-71495Rev. A, 23-Jul-07
1
SPICE Device Model SiA419DJ
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
0.66
165
V
A
V
DS = VGS, ID = −250 µA
VDS ≤ −5 V, VGS = −4.5 V
0.027
0.033
0.043
46
0.025
0.032
0.042
20
VGS = −4.5 V, ID = −5.9 A
VGS = −2.5 V, ID = −5.1 A
VGS = −1.8 V, ID = −2 A
Drain-Source On-State Resistancea
rDS(on)
Ω
Forward Transconductancea
Diode Forward Voltagea
gfs
S
V
VDS = −10 V, ID = −5.9 A
VSD
I
S = −7 A
−0.94
−0.80
Dynamicb
Input Capacitance
Ciss
Coss
Crss
1550
203
135
14
1500
210
150
19
pF
nC
V
DS = −10 V, VGS = 0 V, f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
VDS = −10 V, VGS = −5 V, ID = −8.8 A
Total Gate Charge
Qg
13
17.5
2.1
V
DS = −10 V, VGS = −4.5 V, ID = −8.8 A
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
2.1
5.2
5.2
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 74896
S-71495Rev. A, 23-Jul-07
2
SPICE Device Model SiA419DJ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 74896
S-71495Rev. A, 23-Jul-07
3
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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Document Number: 91000
Revision: 18-Jul-08
www.vishay.com
1
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