SIHU5N80AE-GE3 [VISHAY]
Power Field-Effect Transistor,;
| 型号： | SIHU5N80AE-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Power Field-Effect Transistor, |
| 文件： | 总7页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiHU5N80AE
Vishay Siliconix
www.vishay.com
E Series Power MOSFET
FEATURES
D
• Low figure-of-merit (FOM) Ron x Qg
• Low effective capacitance (Ciss
IPAK
(TO-251)
)
• Reduced switching and conduction losses
• Ultra low gate charge (Qg)
D
G
• Avalanche energy rated (UIS)
• Integrated Zener diode ESD protection
S
D
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
G
N-Channel MOSFET
APPLICATIONS
PRODUCT SUMMARY
VDS (V) at TJ max.
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
850
RDS(on) typ. (Ω) at 25 °C
VGS = 10 V
1.17
Qg max. (nC)
16.5
3
Q
gs (nC)
gd (nC)
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
Q
6
Configuration
Single
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
ORDERING INFORMATION
Package
IPAK (TO-251)
Lead (Pb)-free and halogen-free
SiHU5N80AE-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-source voltage
Gate-source voltage
VDS
800
V
VGS
30
T
C = 25 °C
4.4
Continuous drain current (TJ = 150 °C)
VGS at 10 V
ID
TC = 100 °C
2.8
A
Pulsed drain current a
IDM
7
0.5
Linear derating factor
W/°C
mJ
W
Single pulse avalanche energy b
EAS
PD
17
Maximum power dissipation
62.5
-55 to +150
70
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dv/dt d
TJ, Tstg
°C
TJ = 125 °C
For 10 s
dv/dt
V/ns
°C
0.3
Soldering recommendations (peak temperature) c
260
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 1.1 A
c. 1.6 mm from case
d. ISD ≤ ID, di/dt = 100 A/μs, starting TJ = 25 °C
S19-1146-Rev. A, 13-Jan-2020
Document Number: 92304
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N80AE
Vishay Siliconix
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MAX.
62
UNIT
Maximum junction-to-ambient
Maximum junction-to-case (drain)
RthJA
RthJC
°C/W
2
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-source breakdown voltage
VDS
VGS = 0 V, ID = 250 μA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 μA
800
-
-
-
V
V/°C
V
VDS temperature coefficient
ΔVDS/TJ
VGS(th)
-
2
-
-
-
-
-
-
0.8
Gate-source threshold voltage (N)
-
4
VGS
VGS
=
=
20 V
30 V
-
-
10
50
Gate-source leakage
IGSS
IDSS
μA
μA
VDS = 800 V, VGS = 0 V
-
1
Zero gate voltage drain current
VDS = 640 V, VGS = 0 V, TJ = 125 °C
-
10
1.35
-
Drain-source on-state resistance
Forward transconductance a
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 1.5 A
1.17
1.2
Ω
VDS = 30 V, ID = 2 A
S
Input capacitance
Ciss
Coss
Crss
-
-
-
321
20
4
-
-
-
VGS = 0 V,
Output capacitance
V
DS = 100 V,
f = 1 MHz
Reverse transfer capacitance
pF
nC
Effective output capacitance, energy
related a
Co(er)
Co(tr)
-
-
14
71
-
-
VDS = 0 V to 480 V, VGS = 0 V
Effective output capacitance, time
related b
Total gate charge
Qg
Qgs
Qgd
td(on)
tr
-
-
11
3
16.5
-
Gate-source charge
Gate-drain charge
Turn-on delay time
Rise time
VGS = 10 V
ID = 2 A, VDS = 640 V
-
6
-
-
12
8
24
16
20
56
6.4
-
VDD = 640 V, ID = 2 A,
GS = 10 V, Rg = 9.1 Ω
ns
V
Turn-off delay time
Fall time
td(off)
tf
-
10
28
3.2
-
Gate input resistance
Drain-Source Body Diode Characteristics
Rg
f = 1 MHz, open drain
1.6
Ω
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
Continuous source-drain diode current
Pulsed diode forward current
IS
-
-
-
-
4.4
7
A
G
ISM
S
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
VSD
trr
TJ = 25 °C, IS = 2 A, VGS = 0 V
-
-
-
-
-
1.2
534
2.4
-
V
ns
μC
A
267
1.2
7.5
TJ = 25 °C, IF = IS = 2 A,
di/dt = 100 A/μs, VR = 25 V
Qrr
IRRM
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 V to 480 V VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 V to 480 V VDSS
S19-1146-Rev. A, 13-Jan-2020
Document Number: 92304
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N80AE
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
8
6
4
2
0
10000
1000
100
3.0
2.5
2.0
1.5
1.0
0.5
0
10000
1000
TJ = 25 °C
ID =2 A
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
VGS = 10 V
100
6 V
5 V
10
10
0
0
0
5
10
15
20
-60 -40 -20
0
20 40 60 80 100 120 140 160
VDS - Drain-to-Source Voltage (V)
TJ - Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Axis Title
Axis Title
5
4
3
2
1
0
10000
1000
100
10 000
10000
1000
100
15 V
VGS = 0 V, f = 1 MHz
TJ = 150 °C
14 V
C
C
iss = Cgs + Cgd, Cds shorted
rss = Cgd
13 V
7 V
12 V
11 V
10 V
9 V
Coss = Cds + Cgd
1000
100
10
Ciss
6 V
5 V
Coss
Crss
10
1
10
5
10
15
20
0
100
200
300
400
500
600
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Axis Title
Axis Title
8
6
4
2
0
10000
1000
100
10 000
1000
100
4
3
2
1
0
TJ = 25 °C
Coss
Eoss
TJ = 150 °C
VDS = 30.8 V
10
10
5
10
15
20
0
100
200
300
400
500
600
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Coss and Eoss vs. VDS
S19-1146-Rev. A, 13-Jan-2020
Document Number: 92304
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N80AE
Vishay Siliconix
www.vishay.com
Axis Title
Axis Title
12
9
10000
1000
100
5
4
3
2
1
0
10000
1000
100
VDS = 640 V
V
DS = 400 V
DS = 160 V
V
6
3
0
10
10
0
3
6
9
12
25
50
75
100
125
150
Qg - Total Gate Charge (nC)
TC - Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
Axis Title
Axis Title
1.2
1.1
1
10000
1000
100
10
10000
1000
100
TJ = 150 °C
1
TJ = 25 °C
0.9
0.8
VGS = 0 V
1.2
ID = 250uA
0.1
10
10
0.2
0.4
0.6
0.8
1.0
1.4
-60 -40 -20
0
20 40 60 80 100 120 140 160
VSD - Source-Drain Voltage (V)
TJ - Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 11 - Normalized Breakdown Voltage vs. Temperature
Axis Title
100
10
10000
Operation in this area
limited by RDS(on)
IDM limited
1000
a
BVDSS limited
Limited by RDS(on)
1
100 µs
100
0.1
0.01
1 ms
TC = 25 °C,
T
J = 150 °C,
10 ms
single pulse
10
1000
1
10
100
VDS - Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
S19-1146-Rev. A, 13-Jan-2020
Document Number: 92304
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N80AE
Vishay Siliconix
www.vishay.com
Axis Title
1
10000
1000
100
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001
10
1
0.001
0.01
0.1
Pulse Time (s)
Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
D.U.T.
VDD
Rg
+
V
-
DD
VDS
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
Qg
10 V
90 %
Qgs
Qgd
10 %
VGS
VG
td(on) tr
td(off) tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
VDS
Vary tp to obtain
required IAS
50 kΩ
12 V
0.2 μF
0.3 μF
D.U.T.
Rg
+
-
VDD
+
-
VDS
D.U.T.
IAS
10 V
VGS
tp
0.01 Ω
3 mA
IG
ID
Fig. 15 - Unclamped Inductive Test Circuit
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
Document Number: 92304
S19-1146-Rev. A, 13-Jan-2020
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N80AE
Vishay Siliconix
www.vishay.com
Peak Diode Recovery dv/dt Test Circuit
+
Circuit layout considerations
D.U.T.
•
•
Low stray inductance
Ground plane
3
• Low leakage inductance
current transformer
-
+
2
4
-
+
-
1
Rg
• dv/dt controlled by Rg
+
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
VDD
-
• D.U.T. - device under test
1
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V a
GS
D.U.T. ISD waveform
D.U.T. VDS waveform
2
Reverse
recovery
current
Body diode forward
current
di/dt
3
Diode recovery
dv/dt
VDD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
4
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?92293.
S19-1146-Rev. A, 13-Jan-2020
Document Number: 92304
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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Revision: 01-Jan-2019
Document Number: 91000
1
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