SIP21301LH-15-E3 [VISHAY]
Analog Circuit, CMOS, PDSO8;
| 型号： | SIP21301LH-15-E3 |
| 厂家： | 
VISHAY |
| 描述： | Analog Circuit, CMOS, PDSO8 光电二极管 |
| 文件： | 总11页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiP21301
Vishay Siliconix
Series Linear Regulator Controller
FEATURES
DESCRIPTION
•
Programmable Non Rush Current on Start up
SiP21301 is a single channel series regulator controller to
drive N-Channel MOSFET. It is the perfect choice for the low
voltage, high current application.
This controller provides the complete features, such as
non-rush current on soft start-up, short circuit protection and
thermal shutdown.
In addition, it has under-voltage lock-out for safe operation.
SiP21301 is designed to maintain regulation while delivering
up to 7 A peak current, making it ideal for systems that have
a high surge current upon turn-on.
SiP21301 provides an adjustable output as well as fixed
output voltage options 1.2 V and 1.5 V.
(NRCS)
•
•
•
•
•
•
Short Circuit Protection (SCP)
Thermal Shutdown
UVLO and Latch Function
Fixed 1.2 V and 1.5 V Output Voltage Options
N-Channel MOSFET driver
MSOP8 Package
RoHS
COMPLIANT
APPLICATIONS
•
Game Console
•
Set Top Box
SiP21301 is available in a lead (Pb)-free MSOP8 package
for operating over temperature range (- 10 °C to 100 °C).
TYPICAL APPLICATION CIRCUIT
Q1
V
OUT
V
IN
R2’
U1
NRCS/SC
R2
V
D
C
IN
GND
EN
V
G
10 µF
SiP21301
V
S
EN
5 V
V
CC
V
FB
R1’
C
NRCS
C
VCC
R1
0.1 µF
1 µF
GND
GND
SiP21301 Adjustable Version
Figure 1.
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
www.vishay.com
1
SiP21301
Vishay Siliconix
Q1
V
OUT
V
IN
U1
NRCS/SC
V
D
V
V
C
G
IN
GND
EN
10 µF
SiP21301
S
EN
5 V
V
FB
V
CC
C
VCC
1 µF
GND
GND
SiP21301 - Fixed Version
Figure 2.
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
Supply Input Voltage (VCC
)
)
- 0.3 to 6
- 0.3 to 6
- 0.3 to 6
666
Drain Voltage (VD)
V
Enable Input Voltage (VEN
Power Dissipationa (Pd)
mW
°C
Storage Temperature (Tstg
)
- 65 to 150
150
Maximum Junction Temperature
Package Thermal Resistanceb (θJA
)
150
°C/W
Notes:
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 6.6 mW/°C above TA = 25 °C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
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2
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
SiP21301
Vishay Siliconix
RECOMMENDED OPERATING RANGE
Parameter
Limit
Unit
Supply Voltage (VCC
Drain Voltage (VD)
)
4.5 to 5.5
0.65 to 5.5
- 0.3 to 5.5
0.001 to 1
0.65 to 2.5
- 10 to 100
V
Enable Input Voltage (VEN
)
Capacitor On NRCS/SCP Terminal (CNRCS
Maximum Output Voltage Range (VO)
)
µf
V
Operating Temperature Range (TOPR
)
°C
ELECTRICAL SPECIFICATIONS
Test Conditions
CC = 5 V, VD = VIN = 3.3 V,VEN = 3 V,
V
R1 = R1' = ∞ Ω, R2 = R2' = 0 Ω
TA = 25 °C.
Unless Otherwise Specified
Parameter
Symbol
Temp
Mina
Typb
Maxa
Unit
Supply Section
Supply Current
ICC
ISD
Room
Room
Room
Room
1.0
0.1
0.1
0.5
1.7
10
mA
µA
VEN = 0 V
VCC = 4.5 V to 5.5 V, IO = 50 mA
IO = 0 A to 3 A
Shutdown Supply Current
Line Regulation
ΔVO/ΔVCC
ΔVO/ΔIO
0.5
10
%/V
mV
Load Regulation
Adjustable Version Only
Feedback Voltage 1
VFB1
VFB2
IO = 50 mA
Room
Full
0.643
0.634
0.650
0.650
0.657
0.666
IO = 50 mA, VCC = 4.5 V to 5.5 V,
TA = - 10 °C to 100 °C
Feedback Voltage 2
Output Voltage
V
nA
%
R1 = R1’ = 3.9 kΩ
R2 = R2’ = 3.3 kΩ
VO
IFB
Room
Room
1.2
80
V
FB Input Bias Current
Fixed Version Only
VFB1
VFB2
IO = 50 mA
Feedback Voltage 1
Room
Full
- 1.0
- 2.5
0
0
1.0
2.5
IO = 50 mA, VCC = 4.5 V to 5.5 V,
TA = - 10 °C to 100 °C
Feedback Voltage 2
Enable Section
VENH
VENL
IEN
High Level Enable Input Voltage
Low Level Enable Input Voltage
Room
Room
Room
2
V
0.8
10
VEN = 3 V
Enable Input Current
Source Section
7
µA
VS Input Bias Current
Room
Room
1.2
2.4
mA
mA
mA
V
S Stand-by Current
150
Output Drive Section (Adjustable Version Only)
IGSO
IGSI
VFB = 0.6 V, VG = 2.5 V
VFB = 0.7 V, VG = 2.5 V
Driver Source Current
Drive Sink Current
Room
Room
2
2
3
3
4
4
Output Drive Section (Fixed version Only)
IGSO
IGSI
VFB = VO - 0.1 V, VG = 2.5 V
VFB = VO + 0.1 V, VG = 2.5 V
Driver Source current
Driver Sink Current
UVLO Section
Room
Room
2
2
3
3
4
4
VCCUV
VCCHYS
VDUV
VCC: Sweep up
VCC: Sweep down
VD: Sweep up
VCC UVLO
Room
Room
Room
4.20
100
4.35
160
4.50
220
V
mV
V
VCC UVLO Hysteresis
VD UVLO
0.6 x VO 0.7 x VO 0.8 x VO
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
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3
SiP21301
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions
CC = 5 V, VD = VIN = 3.3 V,VEN = 3 V,
V
R1 = R1' = ∞ Ω, R2 = R2' = 0 Ω
TA = 25 °C.
Unless Otherwise Specified
Parameter
Symbol
Temp
Room
Room
Mina
Typb
0
Maxa
Unit
nA
Drain Voltage Sensing Section (Adjustable Version Only)
VD Input Bias Current ID
Drain Voltage Sensing Section (Fixed Version Only)
VD Input Bias Current
NRCS/SCP Section
NRCS Charge Current
SCP Charge Current
SCP Discharge Current
SCP Threshold Voltage
Short Detect Voltage
NRCS Stand-by Voltage
ID
VD = 3.3 V
100
200
µA
VNRCS/SCP = 0.5 V
VNRCS/SCP = 0.5 V
VNRCS/SCP = 0.5 V
NRCS
ISCP
Room
Room
Room
Room
Room
Room
14
14
20
20
26
26
µA
mA
V
ISCPD
VSCP
VOSCP
VNS
0.3
1.2
1.3
1.4
VO x 0.3 VO x 0.35 VO x 0.4
50
mV
Notes:
a. The algebraic convention whereby the most negative value is a minimum and most positive is a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
PIN CONFIGURATION
MSOP8 Package (Top View)
NRCS/SC
GND
V
V
V
V
D
G
EN
S
V
CC
FB
Figure 3.
PIN DESCRIPTION
Pin Number
Name
Function
1
2
NRCS/SCP
GND
Non-rush current on Start-up/Short circuit protection
Ground pin
By applying less than 0.8 V to this pin, the device will be turned off
Connect this pin to VCC if unused
3
4
EN
VCC
Input supply pin
Feedback input
VFB
- Adjustable version: Connect feedback resistors to program the output voltage for the regulator
- Fixed version: Connect this pin to VS pin
5
VS
VG
VD
6
7
8
Output of regulator. Connect to source of N-channel MOSFET
Connect to gate of N-Channel MOSFET
Connect to drain of N-Channel MOSFET
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Document Number: 73952
S-72100-Rev. B, 15-Oct-07
SiP21301
Vishay Siliconix
ORDERING INFORMATION
Part Number
Marking
01AD
0112
Temperature Range
Package
SiP21301LH-AD-E3
SiP21301LH-12-E3
SiP21301LH-15-E3
- 10 °C to 100 °C
MSOP8
0115
FUNCTIONAL BLOCK DIAGRAM
VCC
+
VD
Logic
UVLO
-
0.455 V
EN
UVLO
Logic
UVLO
0.455 V
0.65 V
Reference
+
+
-
NRCS
0.65 V
VG
VS
0.35 V x V
O
Enable
EN
EN
TSD
SCP
UVLO
Logic
EN
-
+
VFB
0.35 V x V
O
Thermal
Shutdown
SCP
SCP
TSD
NRCS
NRCS
: Adjustable Version Only
: Fixed Version Only
NRCS/SCP
GND
Figure 4.
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
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SiP21301
Vishay Siliconix
DETAILED OPERATION DESCRIPTION
SiP21301 is the LDO controller for the low voltage, high
current application. It consists of enable, device UVLO, LDO
UVLO, thermal shutdown, NRCS (None Rush Current
Start-up), SCP (LDO Output Short Circuit Protection),
reference voltage and error amplifier.
The typical input UVLOthreshold voltage is set to 0.7 x VO. If
the VD voltage is greater than 0.455 V, the LDO UVLO will be
unlocked.
NRCS
The NRCS circuit begins initiated when the EN pin active
high and the voltage on NRCS/SCP pin begins to ramp up
because the external NRCS/SCP capacitor is being charged
up by an internal 20 µA constant current source. When
controller UVLO and LDO UVLO are released with 75 µs
delay, NRCS circuit completed initialization. The voltage on
NRCS/SCP keeps ramping up to 1 V. Once it reaches 1 V, the
voltage on NRCS/SCP starts to discharge to ground for
output short circuit protection. The voltage on NRCS/SCP
pin is allowed to recharge up to 1.3 V for short circuit
protection after startup. During this start-up period, the
voltage on NRCS/SCP is the positive input of the error
amplifier in the driving circuit.
ENABLE
The ENABLE block is to generate the enable and disable
signal to turn the LDO control block on and off. If the voltage
on EN pin is applied greater than 2.0 V, the control block are
enable. If the voltage on EN pin applied less than 0.8 V, the
control block are disabled. EN pin is an active high pin. When
EN pin actives high, an internal 20 µA current source will
charge up the external NRCS/SCP capacitor with out any
delay.
Reference Voltage
The reference voltage is enabled, when the enable active
high signal is applied to the EN pin. The reference voltage
block is composed of a self-biased shunt reference circuit
and generates following several references to for the control
block:
1. 1.0 V for the NRCS circuit
2. 0.455 V for LDO UVLO circuit
3. 1.3 V for short circuit protection circuit
4. 0.65 V for output regulation
5. 0.35*VO for short circuit detection
SCP
The SCP sense function starts to monitor the output voltage
of the LDO once the EN input active high. After the startup,
The voltage on NRCS/SCP pin is allowed to recharge up to
1.3 V for short circuit protection. If the LDO is under the
output short circuit condition, which output is lower than
0.35 x VO, The external NRCS/SCP capacitor will be
recharged up to 1.3 V to activate the SCP by an internal
20 µA constant current source. During this recharge period,
if the output short circuit condition is maintained until the
voltage on NRCS/SCP reach 1.3 V, the output will be turned
of with latch mode.
Thermal Shutdown
SiP21301 has a thermal shutdown circuit to protection itself.
When the junction temperature is around 175 °C, the thermal
shutdown function is activated, the output jumps into
shutdown mode.
Error Amplifier
The error amplifier is
a
conventional operation
Controller UVLO
Transconductance amplifier (OTA). This OTA has two
positive inputs and one negative input. The negative input as
a feedback signal to sense the voltage of LDO output. The
LDO output feedback voltage on the negative input of OTA
will follow the NRCS/SCP voltage during the start up period.
Once the NRCS/SCP voltage exceed the reference voltage
(0.65 V) on another positive input of OTA, the feedback
voltage on the negative input of the OTA will follow 0.65 V
reference voltage to regulate the output voltage of LDO.
The function of controller UVLO is the under-voltage lockout
function for SiP21301 itself. This function block consists of an
input detection circuit and UVLO circuit. The input detection
circuit senses the voltage on VCC pin to check for the safe
operation for the rest of the control block. If the VCC voltage
is lower than 3.5 V, this VCC detection circuit will make the
output turn off to prevent improper operation of SiP21301. To
drive an external N-Channel MOSFET without any charge
pump circuit built-in as well as externally, it requires an
enough voltage difference between VCC and VO to drive the
external power MOSFET properly. The controller UVLO is
built-in to ensure proper voltage difference between the gate
and source of the external power MOSFET. The VCC need
to reach 4.35 V to unlock UVLO. It has 160 mV hysteresis.
Power Reset
The output short circuit and input power failure will make
SiP21301 go into latch shutdown mode. Toggling the EN
from its high condition to a low condition, and then back to a
high condition can reset an output short circuit latch and input
power failure condition.
LDO UVLO
The LDO UVLO checks the drain voltage of the external
N-Channel MOSFET independently and guarantees the VD
voltage from abnormal condition. For fixed output version,
the VD pin is typically connected to the input of LDO. If the VD
voltage is greater than 0.7 x VO, the LDO UVLO will be
unlocked. For adjustable version, an external voltage divider
is required to set the UVLO voltage in the input side of LDO.
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Document Number: 73952
S-72100-Rev. B, 15-Oct-07
SiP21301
Vishay Siliconix
TYPICAL CHARACTERISTICS
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
0.660
V
V
= 5 V
= 1.2 V
CC
O
V
CC
= 5 V
0.655
0.650
0.645
0.640
0.635
4.5
4.7
4.9
5.1
(V)
5.3
5.5
5.5
135
- 40
- 15
10
35
60
85
110
135
V
Temperature (°C)
VCC vs. Temperature
CC
VO vs. VCC
1.215
1.55
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
V
V
= 5 V
CC
V
V
= 5 V
= 1.2 V
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.175
= 1.5 V
CC
O
O
- 40
- 15
10
35
60
85
110
135
4.5
4.7
4.9
5.1
(V)
5.3
Temperature (°C)
VO vs. Temperature
V
CC
VO vs. VCC
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
1.475
1.470
V
CC
= 5 V
= 1.5 V
V
O
- 40
- 15
10
35
60
85
110
- 40
- 15
10
35
60
85
110
135
Temperature (°C)
ICC vs. Temperature
Temperature (°C)
O vs. Temperature
V
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
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SiP21301
Vishay Siliconix
TYPICAL CHARACTERISTICS
1.2
100000
10000
1000
100
1.1
1.0
0.9
0.8
10
1
4.5
5.0
5.5
6.0
0
1
2
3
4
5
I
(A)
O
V
CC
(V)
Stable Zone (SUD40N02-08)
ICC vs. VCC
100000
10000
1000
100
100000
10000
1000
100
10
10
1
1
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0
1
2
3
4
5
I
(A)
I
O
O
Stable Zone (Si3460DV)
Stable Zone (Si4866)
80
70
60
50
40
30
20
10
0
10
100
1000
10000
100000
Frequency
V
CC
= 5 V, V = V = 3.3 V, V = 3 V,
IN D EN
V
= 1.2 V, Q = SUD40N02
O
1
PSRR
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Document Number: 73952
S-72100-Rev. B, 15-Oct-07
SiP21301
Vishay Siliconix
TYPICAL WAVEFORMS
EN (500 mV/div)
NRCS/SCP
(200 mV/div)
EN (500 mV/div)
V
(500 mV/div)
G
V
G
(1 V/div)
V
O
(200 mV/div)
NRCS/SCP
(200 mV/div)
V
O
(200 mV/div)
1 ms/div
VCC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
2 ms/div
VCC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
EN Pin ENABLE Start-Up with Output Short
V
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
V
EN Pin ENABLE Soft Start-Up
V
(200 mV/div)
O
V
(500 mV/div)
D
V
(1 V/div)
G
V
D
(500 mV/div)
NRCS/SCP
(200 mV/div)
NRCS/SCP
(200 mV/div)
V
O
(200 mV/div)
V
G
(1 V/div)
V
D
= 0.7 x V
O
V
D
= 0.7 x V
O
2 ms/div
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
2 ms/div
VCC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
V
V
Power-In Soft Start-Up
Power-In Soft Start-Up with Output Short
NRCS/SCP
(200 mV/div)
V
O
(200 mV/div)
V
(1 V/div)
CC
V
CC
(1 V/div)
V
(1 V/div)
G
V
G
(500 mV/div)
V
O
(200 mV/div)
NRCS/SCP
(200 mV/div)
1 ms/div
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
CC Power-In Soft Start-Up
1 ms/div
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
CC Power-In Soft Start-Up with Output Short
V
V
V
V
Document Number: 73952
S-72100-Rev. B, 15-Oct-07
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SiP21301
Vishay Siliconix
TYPICAL WAVEFORMS
V
IN
V
O
= 1.7 V
= 1.2 V
V
IN
V
O
= 1.7 V
= 1.2 V
V
(50 mV/div)
(1 V/div)
O
V
(50 mV/div)
O
V
G
(1 V/div)
V
G
I
(2 A/div)
OUT
I
(2 A/div)
OUT
50 µs/div
20 µs/div
V
CC = 5 V, VIN = VD = 1.7 V, VEN = 3 V,
V
CC = 5 V, VIN = VD = 1.7 V, VEN = 3 V,
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
Rising Edge of Transient Response
Falling Edge of Transient Response
V
O
(200 mV/div)
V
(200 mV/div)
(500 mV/div)
O
V
(1 V/div)
G
V
V
(500 mV/div)
G
D
EN (500 mV/div)
20 µs/div
200 µs/div
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
V
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
V
V
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
VO = 1.2 V, IO = 5 A, Q1 = SUD40N02
EN Active Low Power Down
Input Power Fail
V
O
(200 mV/div)
V (1 V/div)
G
NRCS/SCP
(200 mV/div)
V
O
(200 mV/div)
V
CC
(1 V/div)
V
G
(1 V/div)
50 µs/div
1 ms/div
CC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
Output Short Circuit After Start-Up
VCC = 5 V, VIN = VD = 3.3 V, VEN = 3 V,
O = 1.2 V, IO = 5 A, Q1 = SUD40N02
CC Power Fail
V
V
V
V
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?73952.
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Document Number: 73952
S-72100-Rev. B, 15-Oct-07
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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1
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IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, 3 X 3 MM, LEAD FREE, MLP-10, Fixed Positive Multiple Output LDO Regulator
VISHAY
SIP2210DMP-DK-E3
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, 3 X 3 MM, LEAD FREE, MLP-10, Fixed Positive Multiple Output LDO Regulator
VISHAY
SIP2210DMP-DN-E3
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, 3 X 3 MM, LEAD FREE, MLP-10, Fixed Positive Multiple Output LDO Regulator
VISHAY
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