SUM23N15-73_06 [VISHAY]
N-Channel 150-V (D-S), 175Celsius MOSFET; N沟道150 - V（D -S） 175Celsius MOSFET的
| 型号： | SUM23N15-73_06 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 150-V (D-S), 175Celsius MOSFET |
| 文件： | 总4页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUM23N15-73
Vishay Siliconix
N-Channel 150-V (D-S), 175°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 72331
S-60543Rev. B, 10-Apr-06
1
SPICE Device Model SUM23N15-73
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Condition
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
3
V
A
V
DS = VGS, ID = 250 µA
84
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 15 A
0.059
0.011
0.134
0.064
0.89
0.059
VGS = 10 V, ID = 15 A, TJ = 125°C
VGS = 10 V, ID = 15 A, TJ = 175°C
VGS = 6 V, ID = 10 A
Drain-Source On-State Resistancea
rDS(on)
Ω
0.062
1
Forward Voltagea
VSD
IF = 23 A, VGS = 0 V
V
Dynamicb
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
Ciss
Coss
Crss
Qg
1290
150
60
1290
160
70
V
GS = 0 V, VDS = 25 V, f = 1 MHz
pF
nC
22
22
VDS = 75 V, VGS = 10 V, ID = 23 A
Qgs
Qgd
td(on)
tr
6
6
7.5
37
7.5
10
29
60
VDD = 75 V, RL = 3.26 Ω
ns
Turn-Off Delay Timec
Fall Timec
td(off)
tf
29
30
I
D ≅ 23 A, VGEN = 10 V, RG = 2.5 Ω
12
45
Notes
a.
b.
c.
Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
Guaranteed by design, not subject to production testing.
Independent of operating temperature.
www.vishay.com
Document Number: 72331
S-60543Rev. B, 10-Apr-06
2
SPICE Device Model SUM23N15-73
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 72331
S-60543Rev. B, 10-Apr-06
3
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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Document Number: 91000
Revision: 18-Jul-08
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