SUM90P10-19L [VISHAY]
P-Channel 100-V (D-S) MOSFET; P沟道100 -V （D -S ）的MOSFET
| 型号： | SUM90P10-19L |
| 厂家： | 
VISHAY |
| 描述： | P-Channel 100-V (D-S) MOSFET |
| 文件： | 总3页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUM90P10-19L
Vishay Siliconix
P-Channel 100-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 74169
S-61262Rev. A, 24-Jul-06
1
SPICE Device Model SUM90P10-19L
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.9
313
V
A
V
DS = VGS, ID = −250 µA
VDS = −5 V, VGS = −10 V
0.0157
0.0156
0.0173
0.80
VGS = −10 V, ID = −20 A
VGS = −4.5 V, ID = −15 A
Drain-Source On-State Resistancea
rDS(on)
VSD
Ω
Forward Voltagea
0.88
V
VDS = −15 V, IF = −20 A
Dynamicb
Input Capacitance
Ciss
Coss
Crss
10710
556
11100
700
pF
nC
V
DS = −.50 V, VGS = 0 V, f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
1214
1690
217
VDS = − 50 V, VGS = −10 V, ID = −90 A
c
Qg
Total Gate Charge
117
42
97
c
Qgs
Qgd
42
51
Gate-Source Charge
V
DS = −50 V, VGS = −4.5 V, ID = −90 A
c
51
Gate-Drain Charge
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
Document Number: 74169
S-61262Rev. A, 24-Jul-06
2
SPICE Device Model SUM90P10-19L
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 74169
S-61262Rev. A, 24-Jul-06
3
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