TFDS6500 [VISHAY]
Interface Circuit;
| 型号： | TFDS6500 |
| 厂家： | 
VISHAY |
| 描述： | Interface Circuit 接口集成电路 |
| 文件： | 总17页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Fast Infrared Transceiver Module Family
(FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation
Description
The
TFDU6102E,
TFDS6402,
TFDS6502E, smallest FIR transceiver available on the market. This
TFDT6502E are a family of low–power infrared wide selection provides flexibility for a variety of
transceiver modules compliant to the IrDA physical applications and space constraints. The transceivers
layer standard for fast infrared data communication, are capable of directly interfacing with a wide variety
supporting IrDA speeds up to 4.0 Mbit/s (FIR), of I/O devices which perform the modulation/
HP-SIR, Sharp ASK and carrier based remote control demodulation
function,
including
National
modes up to 2 MHz. Integrated within the transceiver Semiconductor’s PC87338, PC87108 and PC87109,
modules are a photo PIN diode, an infrared emitter SMC’s FDC37C669, FDC37N769 and CAM35C44,
(IRED), and a low–power CMOS control IC to provide and Hitachi’s SH3. At a minimum, a current–limiting
a total front–end solution in a single package.
resistor in series with the infrared emitter and a
bypass capacitor are the only external
components required implementing a complete
solution.
V
CC
Vishay Telefunken’s FIR transceivers are available in
four package options, including our Baby Face
package (TFDU610xE), the standard setting, once
FD eCaotmuprleiasnt to the IrDA physical layer specification
D High Efficiency Emitter
D Baby Face (Universal) Package Capable of
Surface Mount Soldering to Side and Top View
Orientation
(Up to 4 Mbit/s),
HP–SIR , Sharp ASK and TV Remote Control
D For 3.0 V and 5.0 V Applications
D Operates from 2.6 V to 5.5 V within specification,
D Directly Interfaces with Various Super I/O and
operational down to 2.4 V
Controller Devices
D Low Power Consumption (3 mA Supply Current)
D Power Shutdown Mode (1 mA Shutdown Current)
D Four Surface Mount Package Options
D Built–In EMI Protection – No External Shielding
Necessary
D Few External Components Required
–
–
–
–
Universal (9.7 × 4.7 × 4.0 mm)
Side View (13.0 × 5.95 × 5.3 mm)
Top View (13.0 × 7.6 × 5.95 mm)
Dracula (11.2 × 5.6 × 2.2 mm)
D Backward Pin to Pin Compatible to all Vishay
Telefunken SIR and FIR Infrared Transceivers
D Split power supply, transmitter and receiver can be
operated from two power supplies with relaxed
requirements, thus saving costs
D Push-Pull-Receiver Output, grounded in
shutdown mode
AD pNpotleicboaotkioConmsputers, Desktop PCs,
D Telecommunication Products
Palmtop Computers (Win CE, Palm PC), PDAs
(Cellular Phones, Pagers)
D Internet TV Boxes, Video Conferencing Systems
D External Infrared Adapters (Dongles)
D Digital Still and Video Cameras
D Printers, Fax Machines, Photocopiers,
Screen Projectors
D Medical and Industrial Data Collection Devices
www.vishay.com
DocumentNumber82526
Rev. B1.6, 02–Nov–00
1
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Package Options
TFDU6102E
Baby Face (Universal)
weight 0.20 g
TFDS6402
Dracula Side View
weight 0.30 g
TFDS6502E
Side View
weight 0.39 g
TFDT6502E
Top View
weight 0.39 g
Ordering Information
Part Number
TFDU6102E–TR3
TFDU6102E–TT3
TFDS6402–TR3
TFDS6502E–TR3
TFDT6502E–TR3
Qty / Reel
Description
1000 pcs
1000 pcs
1000 pcs
750 pcs
750 pcs
Oriented in carrier tape for side view surface mounting
Oriented in carrier tape for top view surface mounting
Side View
Side View
Top View
FunctionalBlock Diagram
VCC
Driver
Rxd
Comparator
Amplifier
IRED Anode
AGC
Logic
SD/Mode
Txd
IRED Cathode
Open Drain Driver
GND
Figure 1. Functional Block Diagram
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2
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Pin Description
Pin Number
Function
Description
I/O Active
“U” and “T” Option “S” Option
1
8
IRED Anode IRED anode, to be externally connected
to V through a current control resistor.
CC
This pin is allowed to be supplied from
an uncontrolled power supply separated
from the controlled V supply
CC
2
1
IRED Cathode IRED cathode, internally connected to
driver transistor
3
4
7
2
Txd
Rxd
Transmit Data Input
I
O
HIGH
LOW
Received Data Output, push-pull CMOS
driver output capable of driving a stan-
dard CMOS or TTL load. No external
pull-up or pull-down resistor is required.
Pin is floating when
device is in shutdown mode
5
6
7
6
3
5
SD/Mode
Shutdown/ Mode
Supply Voltage
HIGH: High speed mode;
I
I
HIGH
V
CC
Mode
LOW: Low speed mode, SIR only
(see chapter “Mode Switching”)
8
4
GND
Ground
“U” Option Baby Face (Universal)
and Dracula
“S” Option Side View
“T” Option Top View
IRED
Detector
IRED
Detector
IRED
Detector
14885
Figure 2. Pinnings
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DocumentNumber82526
Rev. B1.6, 02–Nov–00
3
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Absolute Maximum Ratings
Reference point Pin: GND unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Supply Voltage Range,
Transceiver
Test Conditions
Symbol
Min.
– 0.5
Typ.
Max.
6
Unit
V
0 V <V
<6 V
V
CC2
CC1
Supply Voltage Range,
Transmitter
0 V <V
<6 V
V
– 0.5
6
V
CC1
CC2
Input Currents
For all Pins, Except IRED
Anode Pin
10
mA
Output Sinking Current
Power Dissipation
Junction Temperature
Ambient Temperature
Range (Operating)
Storage Temperature
Range
25
mA
mW
°C
See Derating Curve
P
T
J
T
amb
350
125
+85
D
–25
–25
°C
T
stg
+85
240
°C
°C
Soldering Temperature
See Recommended Solder
Profile (see Figure 11)
Average Output Current
Repetitive Pulsed Output <90 µs, t <20%
I
I
(DC)
(RP)
130
600
mA
mA
IRED
on
IRED
Current
IRED Anode Voltage
Transmitter Data Input
Voltage
Receiver Data Output
Voltage
Virtual Source Size
V
V
– 0.5
– 0.5
6
V
V
IREDA
V
V
+0.5
Txd
CC1
V
– 0.5
2.5
+0.5
V
Rxd
CC1
Method:
d
2.8
mm
(1–1/e) encircled energy
Maximum Intensity for
Class 1 Operation of
EN60825, 1997,
unidirectional operation,
320
mW/sr
IEC825–1 or EN60825–1 worst case test mode
(worst case IrDA FIR
pulse pattern)
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4
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
ElectricalCharacteristics
T
= 25_C, V = 2.6V to 5.5 V unless otherwise noted.
amb
CC
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Transceiver
Supply Voltage
Test Conditions / Pins
Symbol
Min.
2.6
Typ.
Max.
5.5
Unit
V
V
CC
Dynamic Supply Current
Receive mode only.
In transmit mode, add additional 85 mA (typ) for IRED current
SD = Low, E = 0 klx
I
CC
I
CC
I
SD
3
3
4.5
4.5
mA
mA
e
SD = Low, E = 1 klx *)
e
Standby Supply Current
SD = High,
Mode = Floating,
T = 25°C, E = 0 klx
1
1.5
µA
µA
e
T = 25°C, E = 1 klx *)
e
SD = High, T = 85°C,
Mode = Floating,
Not Ambient Light
Sensitive
I
5
µA
SD
Operating Temperature
Range
Output Voltage Low
T
–25
+85
0.8
°C
V
A
R
load
C
load
= 2.2 kW,
= 15 pF
V
0.5
OL
Output Voltage High
R
load
C
load
= 2.2 kW,
= 15 pF
V
V –0.5
CC
V
OH
Input Voltage Low
V
0
0.8
V
IL
(Txd, SD/ Mode, Mode)
Input Voltage High
(Txd, SD/ Mode, Mode)
CMOS level **)
TTL level, V ≥ 4.5 V
V
V
I
0.9 x V
2.4
V
V
µA
IH
IH
L
CC
CC
Input Leakage Current
(Txd, SD/ Mode)
Input Leakage Current,
Mode
–10
+10
+80
5
I
–80
µA
L
Input Capacitance
C
pF
I
*)
**)
Standard Illuminant A
The typical threshold level is between 0.5 x V
(V = 3 V) and 0.4 x V (V = 5.5 V) .
CC CC CC
CC/2
It is recommended to use the specified min/ max values to avoid increased operating current.
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DocumentNumber82526
Rev. B1.6, 02–Nov–00
5
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
OptoelectronicCharacteristics
T
= 25_C, V = 2.6 V to 5.5 V unless otherwise noted.
amb
CC
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Receiver
Minimum Detection
Threshold Irradiance, 9.6 kbit/s to 115.2 kbit/s
SIR Mode
Test Conditions
Symbol
Min.
Typ.
20
Max.
35
Unit
2
2
2
2
2
2
TFDS6502E/ TFDT6502E
E
E
E
E
E
E
mW/m
e
e
e
e
e
e
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
9.6 kbit/s to 115.2 kbit/s
l = 850 nm to 900 nm
25
50
65
65
85
10
40
mW/m
mW/m
mW/m
mW/m
mW/m
Minimum Detection
Threshold Irradiance, 1.152 Mbit/s
MIR Mode
TFDS6502E/ TFDT6502E
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
1.152 Mbit/s
l = 850 nm to 900 nm
TFDS6502E/ TFDT6502E
Minimum Detection
Threshold Irradiance, 4.0 Mbit/s
FIR Mode
100
100
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
4.0 Mbit/s
l = 850 nm to 900 nm
l = 850 nm to 900 nm
2
Maximum Detection
Threshold Irradiance
Logic LOW Receiver
Input Irradiance
Rise Time of Output
Signal––,,,,klll
Fall Time of Output
Signal
E
E
5
4
kW/m
mW/m
ns
e
e
2
10% to 90%, @2.2 kΩ, 15 pF
90% to 10%, @2.2 kΩ, 15 pF
Input pulse length 20 µs, 9.6 kbit/s
t
t
10
10
40
40
20
r (Rxd)
f (Rxd)
ns
Rxd Pulse Width of
Output Signal, 50%
SIR Mode
t
t
1.2
1.2
10
µs
µs
PW
PW
Input pulse length 1.41 ms,
115.2 kbit/s
1/2 bit
length
Rxd Pulse Width of
Output Signal, 50%
MIR Mode
Input pulse length 217 ns,
1.152 Mbit/s
t
110
260
ns
PW
Rxd Pulse Width of
Output Signal, 50%
FIR Mode
Stochastic Jitter,
Leading Edge,
FIR Mode
Input pulse length 125 ns, 4.0 Mbit/s
Input pulse length 250 ns, 4.0 Mbit/s
t
t
100
200
160
290
ns
ns
ns
PW
PW
2
Input Irradiance = 100 mW/m ,
±10
4.0 Mbit/s
Latency
t
120
300
µs
L
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6
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
OptoelectronicCharacteristics (continued)
T
= 25_C, V = 2.6 V to 5.5 V unless otherwise noted.
amb
CC
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Transmitter
IRED Operating Current R1*) = 7.2 Ω, V = 5.0 V
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
I
0.4
170
0.55
350
A
CC
D
Output Radiant Intensity
(see Figure 3)
V
= 5.0 V, α = 0_, 15_
I
120
mW/sr
CC
e
Txd = High, SD = Low, R1 = 7.2 Ω
Output Radiant Intensity
V
= 5.0 V, α = 0_, 15_
I
0.04
mW/sr
CC
e
Txd = Low, SD = High,
(Receiver is inactive as long as
SD = High) R1 = 7.2 Ω
Output Radiant Intensity,
Angle of Half Intensity
a
±24
°
Peak – Emission
Wavelength
Optical Output Pulse
Duration
l
880
207
117
242
900
227
133
258
nm
ns
ns
ns
µs
ns
%
P
Input pulse width 217 ns,
1.152 Mbit/s
Input pulse width 125 ns,
4 Mbit/s
Input pulse width 250 ns,
4 Mbit/s
Input pulse width t < 80 µs
Input pulse width t ≥ 80 µs
t
t
t
t
217
125
250
t
opt
opt
opt
opt
80
40
Optical Rise Time,
Fall Time
Optical Overshoot
t
t
,
10
ropt
fopt
10
*)
R1: control series resistor for current limitation
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DocumentNumber82526
Rev. B1.6, 02–Nov–00
7
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Vishay Telefunken transceivers integrate a sensitive
Recommended Circuit Diagram
receiver and a built-in power driver. The combination
of both needs a careful circuit board layout. The use of
thin, long, resistive and inductive wiring should be
avoided. The inputs (Txd, SD/ Mode) and the output
Rxd should be directly (DC) coupled to the I/O circuit.
The only required component for designing an
IrDA 1.3
solution
using
Vishay
Telefunken
transceivers is a current limiting resistor, R1, to the
IRED. However, depending on the entire system
design and board layout, additional components may
be required (see figure 3).
R1 is used for controlling the current through the
IR emitter. For increasing the output power of the
IRED, the value of the resistor should be reduced.
Similarly, to reduce the output power of the IRED, the
value of the resistor should be increased. For typical
values of R1 see figure 4. For IrDA compliant
operation, a current control resistor of 7.2 Ω is
recommended. For compensating losses of the cos-
metic window, reducing that value to 5.6 Ω is
acceptable. The upper drive current limitation is
dependent on the duty cycle and is given by the
absolute maximum ratings on the data sheet.
V
V
CC2
R1
CC1
IRED
IRED
Anode
Cathode
R2
Rxd
Rxd
Txd
TFDx6x0xE
Vcc
SD/Mode
C1
C2
R2, C1 and C2 are optional and dependent on the
GND
Mode
GND
quality of the supply voltage V and injected noise.
CC
Anunstablepowersupplywithdroppingvoltageduring
transmission may reduce sensitivity (and transmission
range) of the transceiver.
SD/Mode
Txd
Note: outlined components are optional depending
on the quality of the power supply
The placement of these parts is critical. It is strongly
recommendedtopositionC2asnearaspossibletothe
transceiver power supply pins. An electrolytic
capacitor should be used for C1 while a ceramic
capacitor is used for C2.
Figure 3. Recommended Application Circuit
Table 1. Recommended Application Circuit Components
Component
Recommended Value
4.7 mF, Tantalum
0.1 µF, Ceramic
5 V supply voltage: 7.2 Ω , 0.25 W
(recommend using
Vishay Part Number
293D 475X9 016B 2T
VJ 1206 Y 104 J XXMT
C1
C2
R1
two 3.6 W, 0.125 W resistors in series)
3.3 V supply voltage: 3.6 Ω , 0.25 W
(recommend using
CRCW–1206–3R60–F–RT1
two 1.8 W, 0.125 W resistors in series)
47 Ω , 0.125 W
CRCW–1206–1R80–F–RT1
CRCW–1206–47R0–F–RT1
R2
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8
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
drivers are available from SMSC and Vishay
Semiconductor GmbH. This software is intended to
work with Windows 95 , too. Alternatively the
HP/ Sharp settings can be selected. The Microsoft
500
400
300
200
100
0
max. intensity in
emission cone "15°
5.25V
5.0V
min. R , min. V
dson F
Operating
Systems
NT 5.0
Beta 2
and
Windows 2000 provide Miniport device drivers.
Mode Switching
5.0V
The TFDU6102E, TFDS6402, TFDS6502E and
TFDT6502E do not power on with a default mode,
therefore the data transfer rate has to be set by a pro-
gramming sequence using the Txd and SD/ Mode
inputs as described below or selected by setting the
Mode Pin. The Mode Pin can be used to statically set
the mode (Mode Pin: LOW: SIR, HIGH: 0.576 Mbit/s
to 4.0 Mbit/s). When using the Mode Pin, the standby
current may increase to about 50 to 60 mA when high
or low. If not used or in standby mode, the mode input
should float to minimize standby current. The low
frequency mode covers speeds up to 115.2 kbit/s. Sig-
nals with higher data rates should be detected in the
high frequency mode. Lower frequency data can also
be received in the high frequency mode but with re-
duced sensitivity. To switch the transceivers from low
frequency mode to the high frequency mode and vice
versa, the programming sequences described below
are required.
max.R , max.V
dson F
V
cc
=4.75V
min. intensity in emission cone "15°
0
2
4
6
8
10 12 14 16
14379
Current Control Resistor ( W )
Figure 4. Intensity Ie vs. Current Control Resistor R1,
5 V Applications
700
max. intensity in
3.6V
emission cone "15°
600
min. R , min. V
dson F
500
400
300
200
100
0
min. intensity in
emission cone "15°
3.3V
max. R , max. V
dson F
50%
SD/Mode
3.3V
=3.0V
V
cc
t
s
t
h
0
2
4
6
8
10
12
High : FIR
Low : SIR
15111
Current Control Resistor ( W )
50%
50%
Txd
Figure 5. Intensity Ie vs. Current Control Resistor R1,
3 V Applications
14873
In addition, when connecting the described circuit to
the power supply, low impedance wiring should be
used.
Figure 6. Mode Switching Timing Diagram
Setting to the High Bandwidth Mode
(0.576 Mbit/s to 4.0 Mbit/s)
I/O and Software
In the description, already different I/Os are
mentioned. Differnt combinations are tested and the
function verified with the special drivers available from
the I/O suppliers. In special cases refer to the I/O
manual, the Vishay application notes, or contact
directly Vishay Sales, Marketing or Application.
1. Set SD/MODE input to logic “HIGH”.
2. Set Txd input to logic “HIGH”. Wait t ≥ 200 ns.
s
3. Set SD/MODE to logic “LOW” (this negative edge
latches state of Txd, which determines speed
setting).
Control: Differences to TFDx6000 Series
4. After waiting t ≥ 200 ns Txd can be set to logic
h
“LOW”. The hold time of Txd is limited by the
maximum allowed pulse length.
For applications using I/Os from NSC, Winbond and TI
no software upgrade is necessary. In combination with
the latest SMSC controllers for Microsoft Txd is now enabled as normal Txd input for the high
Windows 98 a software upgrade is necessary, bandwidth mode.
www.vishay.com
DocumentNumber82526
Rev. B1.6, 02–Nov–00
9
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
3. Set SD/MODE to logic “LOW” (this negative edge
Setting to the Lower Bandwidth Mode
(2.4 kbit/s to 115.2 kbit/s)
latches state of Txd, which determines speed
setting).
4. Txd must be held for t ≥ 200 ns.
1. Set SD/MODE input to logic “HIGH”.
h
Txd is now enabled as normal Txd input for the lower
bandwidth mode.
2. Set Txd input to logic “LOW”. Wait t ≥ 200 ns.
s
Recommended SMD Pad Layout
The leads of the device should be soldered in the center position of the pads.
7 x 1 = 7
0.6 (≤ 0.7)
2.5 (≥ 2.0)
1
8
1
16524
Figure 7. TFDU6102E BabyFace (Universal)
Figure 8. TFDS6402 (Dracula)
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10
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
11.8
5.08
2.54 2.54
8
7
6
5
1.8
0.63
0.63
1.1
1.0
8.3
1
2.2
1
2
3
4
2.54 2.54
5.08
15069
Figure 9. TFDS6502E Side View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
8.89
1.27
0.8
1.8
1
8
15068
Figure 10. TFDT6502E Top View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
Note: Leads of the device should be at least 0.3 mm within the ends of the pads.
Recommended Solder Profile
Current Derating Diagram
600
500
400
300
240
210
180
150
120
90
10 s max.
@ 230°C
2 - 4°C/s
120 - 180 s
90 s max.
Current derating as a function of
200
the maximum forward current of
IRED. Maximum duty cycle: 25%.
60
2 - 4°C/s
100
30
0
0
–40 –20
0
20 40 60 80 100 120 140
0
50 100 150 200 250 300 350
Time ( s )
14874
14875
Temperature( °C )
Figure 11. Recommended Solder Profile
Figure 12. Current Derating Diagram
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DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
TFDU6102E – Baby Face (Universal) Package
(MechanicalDimensions)
12249
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12
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
TFDS6402Package (Mechanical Dimensions)
15971
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DocumentNumber82526
Rev. B1.6, 02–Nov–00
13
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
TFDS6502E – Side View Package (Mechanical Dimensions)
14322
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14
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
TFDT6502E – Top View Package (Mechanical Dimensions)
14325
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15
DocumentNumber82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
Revision History:
B1.1, 01/03/1999: New edition for optimized E family. TFDxxx01E – RXD output is grounded when the device
is switched to shutdown mode.
B1.2, 15/03/1999: A clean tri-state version with floating output in shutdown mode was added as 02 version. The
output radiant intensity was increased.
B1.4a, 26/10/1999:TR3 changed to TR4 for 01 types, weight of packages added.
B1.4b, 22/11/1999:Max. operating current changed from 4.0 mA to 4.5 mA, Dracula package version added,
some typos corrected.
B1.5, 13/10/2000: First typos corrected
B1.6, 02/11/2000: SMD pad layout tolerances added
www.vishay.com
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
Ozone Depleting Substances Policy Statement
It is the policy of VishaySemiconductorGmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating
systems with respect to their impact on the health and safety of our employees and the public, as well as
their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbidtheir use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
VishaySemiconductorGmbH has been able to use its policy of continuous improvements to eliminate the use of
ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitionalsubstances) respectively.
Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substancesand do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer application
by the customer. Should the buyer use Vishay Semiconductorsproducts for any unintended or unauthorized application, the
buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or
indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
www.vishay.com
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