TFDU8108 [VISHAY]
Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s), Serial Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range; 非常快速红外收发器模块（ VFIR ， 16兆位/秒） ，串行接口兼容2.7 V至5.5 V电源电压范围
| 型号： | TFDU8108 |
| 厂家： | 
VISHAY |
| 描述： | Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s), Serial Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range |
| 文件： | 总27页 (文件大小：820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TFDU8108
Vishay Semiconductors
Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s), Serial
Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range
Description
The TFDU8108 transceiver is part of a family of low-
power consumption infrared transceiver modules
compliant to the IrDA physical layer standard for VFIR
infrared data communication, supporting IrDA speeds
up to 16 Mbit/s (VFIR) and carrier based remote con-
trol modes up to 2 MHz. Integrated within the trans-
ceiver module are a PIN photodiode, an infrared
emitter (IRED), and a low-power BiCMOS control IC
18102
to provide a total front-end solution in a single pack-
age.
Vishay Semiconductors VFIR transceivers are avail-
able in the BabyFace package. This provides flexibil-
ity for a variety of applications and space constraints.
The transceivers are capable of directly interfacing
• Power Shutdown Mode
(< 1 µA Shutdown Current)
• Surface Mount Package Options
with a wide variety of I/O devices, which perform the
- Universal (L 9.7 mm × W 4.7 mm × H 4.0 mm)
modulation/ demodulation function. At a minimum, a
- Side and Top View
V
CC bypass capacitor is the only external component
• Tri-State-Receiver Output, Weak Pull-up when in
Shutdown Mode
required implementing a complete solution. For limit-
ing the transceiver internal power dissipation one
additional resistor might be necessary. The trans-
ceiver can be operated with logic I/O voltages as low
as 1.5 V. The functionality of the device is equivalent
to the TFDU6108 with the VFIR functionality added.
The IRED current is programmable to different levels,
no external current limiting resistor is necessary.
• High Efficiency Emitter
• Baby Face (Universal) Package Capable of
Surface Mount Soldering to Side and Top
View Orientation
• Eye safety class 1 (IEC60825-1, ed. 2001), limited
LED on-time, LED current is controlled, no single
fault to be considered
Features
• Built - In EMI Protection including GSM bands. -
EMI Immunity in GSM Bands > 300 V/m verified
No External Shielding Necessary
• Compliant to the latest IrDA physical layer stan-
dard (Up to 16 Mbit/s) and TV Remote Control
• Few External Components Required
• Compliant to the IrDA "Serial Interface
Specification for Transceivers"
• Pin to Pin Compatible to Legacy Vishay Semicon-
ductors SIR and FIR Infrared Transceivers
• For 3.0 V and 5.0 V Applications, fully specified
2.7 V to 5.5 V
• Compliant to all logic levels between 1.5 V and 5 V
• Split power supply, transmitter and receiver can be
operated from two power supplies with relaxed
requirements saving costs,
US Patent No. 6,157,476
• Compliant with IrDA EMI and Background Light
Specification
• Low Power Consumption
(typ. 2.0 mA Supply Current)
• TV Remote Control Support
• Lead (Pb)-free device
• Device in accordance to RoHS 2002/95/EC and
WEEE 2002/96/EC
Document Number 82558
Rev. 1.6, 12-Aug-04
www.vishay.com
1
TFDU8108
Vishay Semiconductors
Applications
• Notebook Computers, Desktop PCs, Palmtop
Computers (Win CE, Palm PC), PDAs
• Printers, Fax Machines, Photocopiers,
Screen Projectors
• Telecommunication Products
(Cellular Phones, Pagers)
• Internet TV Boxes, Video Conferencing Systems
• External Infrared Adapters (Dongles)
• Medical and Industrial Data Collection Devices
• Digital Still and Video Cameras
• MP3 Players
Parts Table
Part
TFDU8108-TR3
TFDU8108-TT3
Description
Qty / Reel
Oriented in carrier tape for side view surface mounting
Oriented in carrier tape for top view surface mounting
1000 pcs
1000 pcs
Functional Block Diagram
Vlogic
VCC1
Driver
Rxd
Comparator
Amplifier
Ω
200
IRED Anode
VCC2
AGC
SCLK
Txd
Logic
Current controlled
driver
IRED Cathode
17086
GND
Pin Description
Pin Number
Function
Description
Connect IRED anode directly to V
I/O
Active
1
IRED Anode
. An unregulated separate
CC2
power supply separated can be used at this pin.
IRED cathode, internally connected to driver transistor
Transmit Data Input, dynamically loaded
2
3
4
IRED Cathode
Txd
Rxd
I
HIGH
LOW
Received Data Output, push-pull CMOS driver output capable of
driving a standard CMOS or TTL load. No external pull-up or pull-
down resistor is required. Pin is current limited for protection against
programming errors. The output is loaded with a weak 500 kΩ pull-
up when in SD mode
O
5
SCLK
Serial Clock, dynamically loaded
I
HIGH
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2
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Pin Number
6
Function
Description
I/O
Active
V
Supply Voltage
CC
7
V
Supply voltage for digital part, 1.5 V to 5.5 V, defines logic swing for
Txd, SCLK, and Rxd
logic
8
GND
Ground
Pinout
Definitions:
TFDU8108
weight 200 mg
In the Vishay transceiver data sheets the following nomenclature is
used for defining the IrDA operating modes:
SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared
standard with the physical layer version IrPhy 1.0
MIR 576 kbit/s to 1152 kbit/s
FIR 4 Mbit/s
"U" Option BabyFace
(Universal)
VFIR 16 Mbit/s
IRED
Detector
MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy
1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the
Low Power Option to MIR and FIR and VFIR was added with IrPhy
1.4. A new version of the standard in any case obsoletes the former
version.
1
2
3
4
5
6
7 8
17087
Remark:
Throughout the documentation the not correct term LED (Light
Emitting Diode) is used for Infrared Emitting Diode (IRED). We are
following the trend to use the term light for infrared radiation, which
is wrong but common usage.
Document Number 82558
Rev. 1.6, 12-Aug-04
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3
TFDU8108
Vishay Semiconductors
Absolute Maximum Ratings
Reference point Ground (pin 8) unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter
Test Conditions
Symbol
Min
Typ.
Max
+ 6
Unit
V
Supply voltage range,
transceiver
0 V < V
0 V < V
0 V < V
< 6 V
< 6 V
< 6 V
V
V
V
- 0.5
CC2
CC1
CC1
CC1
CC2
logic
Supply voltage range,
transmitter
- 0.5
- 0.5
+ 6
+ 6
10
V
V
Supply voltage range,
transceiver logic
Input currents
for all pins, except IRED anode
pin
mA
Output sinking current
Junction temperature
25
mA
°C
T
125
J
Power dissipation
see derating curve, figure 4
P
350
mW
°C
D
Ambient temperature range
(operating)
T
- 25
- 40
+ 85
amb
Storage temperature range
Soldering temperature
T
+ 100
240
°C
°C
stg
see recommended solder profile
(see figure 3)
Average output current
I
(DC)
(RP)
130
600
+ 6
mA
mA
V
IRED
Repetitive pulse output current < 90 µs, t < 20 %
I
IRED
on
IRED anode voltage
V
- 0.5
- 0.5
- 0.5
2.5
IREDA
Transmitter data input voltage
Receiver data output voltage
V
V
V
+ 0.5
V
Txd
logic
logic
V
+ 0.5
V
Rxd
Virtual source size
Method: (1 - 1/e) encircled
d
2.8
mm
energy
Maximum Intensity for Class 1
Operation of IEC825-1 or
EN60825-1, edition Jan. 2001*)
unidirectional operation, worst
case IrDA FIR pulse pattern
Internally
limited to
class 1
IrDA specified maximum limit
500
mW/sr
Due to the internal measures the device is a "class1" device. It will not exceed the IrDA intensity limit of 500 mW/sr.
*)
With the amendment 2 of IEC 60825 - 1 this value
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Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Electrical Characteristics
Transceiver
T
= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.
amb
CC
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter
Supply voltage
Test Conditions
Symbol
Min
2.7
Typ.
Max
5.5
Unit
V
V
V
CC1
logic
1.5
5.5
V
1)
Dynamic supply current
T = - 25 °C to 85 °C
I
I
3.0
1.6
10
mA
mA
CC1
CC1
active, no signal E = 0 klx
e
T = - 25 °C to 85 °C
2.5
active, no signal E = 0 klx, SIR
e
only
T = - 25 °C to 85 °C idle
I
5
1
µA
logic
active, no load E = 0 klx
e
T = - 25 °C to 85 °C
I
mA
logic
2)
E = 1 klx receive mode,
e
2
E
= 100 mW/m
Eo
(9.6 kbit/s to 4.0 Mbit/s),
R = 10 kΩ to V = 5 V,
L
logic
C = 15 pF
L
Shutdown supply current
inactive, set to shutdown mode
I
I
1
µA
µA
SD
SD
T = 25 °C, E = 0 klx
e
inactive, set to shutdown mode
1.5
2)
T = 25 °C, E = 1 klx
e
shutdown mode, T = 85 °C,
not ambient light sensitive
I
5
µA
SD
Operating temperature range
Output voltage low
T
- 25
+ 85
0.8
°C
V
A
C
C
= 15 pF, V
= 5 V
= 5 V
V
0.5
load
load
logic
logic
OL
OH
Output voltage high
= 15 pF, V
V
V
- 0.5
V
logic
3)
Input voltage low (Txd, SCLK)
Input voltage high (Txd, SCLK)
V
0.15 x V
V
IL
IH
L
logic
CMOS level
CMOS level
3)
V
0.9 x V
V
logic
Input leakage current (Txd,
SCLK)
I
- 10
+ 10
5
µA
Input capacitance
C
pF
IN
1)
Receive mode only. In transmit mode, add the averaged programmed current of IRED current as I
Standard Illuminant A
CC2
2)
3)
The typical threshold level is between 0.5 x V
/2 (V
= 3 V) and 0.4 x V
(V
= 5.5 V).With that the device will work with less
logic
logic
logic
logic
tight levels than the specified min/ max values. However, it is recommended to use the specified min/max values to avoid increased oper-
ating/standby supply currents.
Document Number 82558
Rev. 1.6, 12-Aug-04
www.vishay.com
5
TFDU8108
Vishay Semiconductors
Optoelectronic Characteristics
Receiver
T
= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.
CC
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter
Test Conditions
Symbol
Min
Typ.
25
Max
40
Unit
2
2
2
2
Minimum detection threshold
irradiance, SIR mode
9.6 kbit/s to 115.2 kbit/s
λ = 850 nm to 900 nm
1.152 Mbit/s
λ = 850 nm to 900 nm
E
E
E
E
E
E
e
e
e
e
e
e
mW/m
Minimum detection threshold
irradiance, MIR mode
conditionally supported
mW/m
mW/m
mW/m
Minimum detection threshold
irradiance, FIR mode
4 Mbit/s
85
100
10
90
λ = 850 nm to 900 nm
16 Mbit/s
λ = 850 nm to 900 nm
λ = 850 nm to 900 nm
Minimum detection threshold
irradiance, VFIR mode
2
Maximum detection threshold
irradiance
5
4
kW/m
2
Logic LOW receiver input
irradiance
optical ambient noise
suppression up to this level for
mW/m
e.g. fluorescent light tolerance
®
equivalent to the IrDA
"Background Light and
Electromagnetic Field"
specification
Rise time of output signal
Fall time of output signal
10 % to 90 %, 15 pF
90 % to 10 %, 15 pF
t
15
15
3
ns
ns
µs
r (Rxd)
t
f (Rxd)
Rxd pulse width of output signal, input pulse length 20 µs,
50 % SIR mode
t
1.2
1.2
2
PW
9.6 kbit/s
input pulse length 1.41 µs,
t
3
µs
PW
115.2 kbit/s
2
Jitter, leading edge, SIR mode
350
ns
input irradiance = 100 mW/m ,
115.2 kbit/s
Rxd pulse width of output signal, input pulse length 125 ns,
t
t
115
230
125
135
270
20
ns
ns
ns
PW
PW
50 % FIR mode
4.0 Mbit/s
input pulse length 250 ns,
4.0 Mbit/s
2
Jitter, leading edge, FIR mode
input irradiance = 100 mW/m ,
4 Mbit/s
Rxd pulse width of output signal, input pulse length 16 Mbit/s,
t
34
42
5
50
ns
PW
50 %
VFIR
39.5 ns < P
< 43 ns
wopt
2
Jitter, leading edge
Latency
7
ns
input irradiance = 100 mW/m ,
16 Mbit/s, VFIR mode
t
100
µs
L
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6
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Transmitter
T
= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.
amb
CC
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter
Test Conditions
Symbol
Min
Typ.
Max
Unit
mA
IRED operating current
internally controlled,
programmable using the "serial
interface" programming
sequence, see Appendix
V
= 3.3 V, the maximum
I
8
15
30
60
110
220
500
CC1
D
current is limited internally. An
external resistor can be used to
reduce the power dissipation at
higher operating voltages, see
derating curve.
600
0.04
900
Max. output radiant intensity
Output radiant intensity
V
= 3.3 V, α = 0 °,
I
0.3
mW/sr/mA
mW/sr
CC1
e
15 ° Txd = High, R1 = 0 Ω
programmed to max. power
level
V
= 5.0 V, α = 0 °,
15 ° Txd = Low, programmed to
shutdown mode
I
CC1
e
Output radiant intensity, angle of
half intensity
α
24
40
°
Peak - emission wavelength
λ
880
10
nm
p
Spectral bandwidth
∆λ
, t
nm
ns
Optical rise time, fall time
t
40
15
ropt fopt
Optical overshoot
%
Document Number 82558
Rev. 1.6, 12-Aug-04
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7
TFDU8108
Vishay Semiconductors
Recommended Circuit Diagram
Recommended Application Circuit Com-
ponents
Operated with a low impedance power supply the
TFDU8108 needs no external components. However,
depending on the entire system design and board lay-
out, additional components may be required (see fig-
ure 1).
Component
Recommended Value
C1
C2
R1
4.7 µF, 16 V
0.1 µF, Ceramic, 16 V
Recommended for V
≥ 4 V
CC1
Depending on current limit
R2
4.7 Ω, 0.125 W
V
V
CC2
R1
CC1
IRED
Cathode
IRED
Anode
I/O and Software
R2
For operating the device from a Controller I/O a driver
software must be implemented.
Rxd
Rxd
Txd
Vcc
SCLK
C1
C2
Mode Switching
V
logic
GND
GND
The generic IrDA "Serial Interface programming"
needs no special settings for the device. Only the cur-
rent control table must be taken into account. For the
description see the Appendix and the IrDA "Serial
Interface specification for transceivers"
V
logic
SCLK
Txd
17089
Figure 1. Recommended Application Circuit
All external components (R, C) are optional
Vishay Semiconductors transceivers integrate a sen-
sitive receiver and a built-in power driver. The combi-
nation of both needs a careful circuit board layout.
The use of thin, long, resistive and inductive wiring
should be avoided. The inputs (Txd, SCLK) and the
output Rxd should be directly (DC) coupled to the I/O
circuit.
R1 is used for controlling the maximum current
through the IR emitter. This one is necessary when
operating over the full range of operating temperature
and VCC1 - voltages above 4 V. For increasing the
max. output power of the IRED, the value of the resis-
tor should be reduced. It should be dimensioned to
keep the IRED anode voltage below 4 V for using the
full temperature range. For device and eye protection
the pulse duration and current are internally limited.
R2, C1 and C2 are optional and dependent on the
quality of the supply voltage VCC1 and injected noise.
An unstable power supply with dropping voltage dur-
ing transmission may reduce sensitivity (and trans-
mission range) of the transceiver.
The placement of these parts is critical. It is strongly
recommended to position C2 close to the transceiver
power supply pins. An electrolytic capacitor should be
used for C1 while a ceramic capacitor is used for C2.
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8
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Recommended Solder Profile
Lead-Free, Recommended Solder Profile
Solder Profile for Sn/Pb soldering
This device is a lead-free transceiver and qualified for
lead-free processing. For lead-free solder paste like
Sn(3.0 - 4.0)Ag(0.5 - 0.9)Cu, there are two standard
reflow profiles: Ramp-Soak-Spike (RSS) and Ramp-
To-Spike (RTS). The Ramp-Soak-Spike profile was
developed primarily for reflow ovens heated by infra-
red radiation. With widespread use of forced convec-
tion reflow ovens the Ramp-To-Spike profile is used
increasingly. Shown below in figure 3 and figure 4 are
Vishay’s recommended profile for use with this trans-
ceiver type. For more details please refer to Applica-
tion note: SMD Assembly Instruction.
240
220
200
180
160
140
120
100
80
10 s max.
@ 230°C
2°C - 4°C/s
120 s - 180 s
2°C - 4°C/s
90 s max
60
40
20
0
0
50
100 150 200 250 300 350
Time ( s )
14874
Figure 2. Recommended Solder Profile
280
260
240
220
200
180
160
140
120
100
80
Tpeak = 260°C max.
T = 250°C for 10 s....40 s
T = 217°C for 70 s max
40 s max.
70 s max.
90 s...120 s
2°C...4°C/s
60
2°C...3°C/s
40
20
0
0
50
100
150
200
250
300
350
Time/s
Figure 3. Solder Profile, RSS Recommendation
Document Number 82558
Rev. 1.6, 12-Aug-04
www.vishay.com
9
TFDU8108
Vishay Semiconductors
280
260
240
220
200
180
160
140
120
100
80
Tpeak = 260°C max.
<4°C/s
1.3°C/s
Time above 217°C t 70 s
≤
≤
Time above 250°C t 40 s
Peak temperature Tpeak = 260°C
<2°C/s
60
40
20
0
0
50
100
150
200
250
300
Time/s
Figure 4. Solder Profile, RTS Recommendation
A ramp-up rate smaller than 0.9 °C/s is not recom-
mended. Ramp-up rates faster than 1.3 °C/s could
damage an optical part because the thermal conduc-
tivity is less than compared to a standard IC.
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10
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Current Derating Diagram
600
500
400
300
Current derating as a function of
the maximum forward current of
IRED. Maximum duty cycle: 25%.
200
100
0
–40 –20
0
20 40 60 80 100 120 140
14875
Temperature ( °C )
Figure 5. Current Derating Diagram
Document Number 82558
Rev. 1.6, 12-Aug-04
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11
TFDU8108
Vishay Semiconductors
Package Dimensions in mm
18473
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12
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Appendix A
Serial Interface Implementation
Basics of the IrDA Definitions
17092
Figure 6. Interface to Two Infrared Transceivers
The data lines are multiplexed with the transmitter When no infrared communication is in progress and
and receiver signals and separate clocks are used the serial bus is idle, the IRTX line is kept low and
since the transceivers respond to the same address. IRRX is kept high.
17093
Figure 7. Infrared Dongle with Differential Signaling
Document Number 82558
Rev. 1.6, 12-Aug-04
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13
TFDU8108
Vishay Semiconductors
the response phase of a read transaction. The
addressed slave will output the read data on the
IRRX/SRDAT line regardless of the setting of the
Receiver Output Enable bit in the Mode Selection reg-
ister 0. Non addressed slaves will tri-state the IRRX/
SRDAT line. When the transceiver is powered up, the
IRTX/SWDAT line should be kept low and SCLK
should be cycled at least 30 times by the infrared con-
troller before the first command is issued on the IRTX/
SWDAT line. This guarantees that the transceiver
interface circuitry will properly initialize and be ready
to receive commands from the controller. In case of a
multiple transceiver configuration, only one trans-
ceiver should have the receiver output enabled. A
series resistor (approx. 200 ohms) should be placed
on the receiver output from each transceiver to pre-
vent large currents in case a conflict occurs due to a
programming error.
Functional description
The serial interface is designed to interconnect two or
more devices. One of the devices is always in control
of the serial interface and is responsible for starting
every transaction. This device functions as the bus
master and is always the infrared controller. The infra-
red transceivers act as bus slaves and only respond
to transactions initiated by the master. A bus transac-
tion is made up of one or two phases. The first phase
is the Command Phase and is present in every trans-
action. The second phase is the Response Phase
and is present only in those transactions in which data
must be returned from the slave. If the operation
involves a data transfer from the slave, there will be a
Response Phase following the Command Phase in
which the slave will output the data.
The Response Phase, if present, must begin 4 clock
cycles after the last bit of the Command Phase, as
shown in figures 1 - 7 and 1 - 8, otherwise it is
assumed that there will be no response phase and the
master can terminate the transaction.
The SCLK line is always driven by the master and is
used to clock the data being written to or read from
the slave.
SCLK
IRTX/
SWDAT
This line is driven by a totem-pole output buffer. The
SCLK line is always stopped when the serial interface
is idle to minimize power consumption and to avoid
any interference with the analog circuitry inside the
slave. There are no gaps between the bytes in either
the Command or Response Phase. Data is always
transferred in Little Endian order (least significant bit
first). Input data is sampled on the rising edge of
SCLK. IRTX/SWDAT output data from the controller
is clocked by SCLK falling edge. IRRX/SRDAT output
data from the slave is clocked by SCLK rising edge.
Each byte of data in both Command and Response
Phases is preceded by one start bit. The data to be
written to the slave is carried on the IRTX/SWDAT
line. When the control interface is idle, this line carries
the infrared data signal used to drive the transmitter
LED. When the first low-to-high transition on SCLK is
detected at the beginning of the command sequence,
the slave will disable the transmitter LED. The infrared
controller then outputs the command string on the
IRTX/SWDAT line. On the last SCLK cycle of the
command sequence the slave re-enables the trans-
mitter LED and normal infrared transmission can
resume. No transition on SCLK must occur until the
next command sequence otherwise the slave will dis-
able the transmitter LED again. Read data is carried
on the IRRX/SRDAT line. The slave disables the
internal signal from the receiver photo diode during
IRRX/
SRDAT
TLED_DIS
(INTERNAL SIGNAL)
17175
Figure 8. Initial Reset Timing
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
(Note 1)
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)
17176
Figure 9. Special Command Waveform
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14
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
17177
17179
Figure 10. Write Data Waveform
Figure 12. Read Data Waveform
Note 1: If the APEN bit in control register 0 is set to 1, the internal
signal from the receiver photo diode is discon nected and the IRRX/
SRDAT line is pulsed low for one clock cycle at the end of a write
or special command.
17180
Figure 13. Read Data Waveform with Extended Index
Note 2: During a read transaction the infrared controller sets the
IRTX/SWDAT line high after sending the address and index byte
(or bytes). It will then set it low two clock cycles before the end of
the transaction. It is strongly recommended that optical transceiv-
ers monitor this line instead of counting clock cycles in order to
detect the end of the read trans action. This will always guarantee
correct operation in case two or more transceivers from different
manufacturers are sharing the serial interface.
17178
Figure 11. Write Data Waveform with Extended Index
Document Number 82558
Rev. 1.6, 12-Aug-04
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TFDU8108
Vishay Semiconductors
Switching Characteristics
*)
Maximum capacitive load = 20 pF
Parameters
Test Conditions
Symbol
tCKp
Min.
250
60
Max.
Unit
ns
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
R.E., SCLK to next R.E., SCLK
At 2.0 V for single-ended signals
At 0.8 V for single-ended signals
After F.E., SCLK
infinity
tCKh
ns
tCKl
80
ns
Output Data Valid
tDOtv
40
ns
(from infrared controller)
Output Data Hold
(from infrared controller)
After F.E., SCLK
After R.E., SCLK
After R.E., SCLK
tDOth
tDOrv
tDOrh
0
ns
ns
ns
Output Data Valid
(from optical transceiver)
40
40
60
Output Data Hold
(from optical transceiver)
Line Float Delay
Input Data Setup
Input Data Hold
*)
After R.E., SCLK
Before R.E., SCLK
After R.E., SCLK
tDOrf
tDIs
ns
ns
ns
10
5
tDIh
Capacitive load is different from "Serial interface - specification". For the bus protocol see "RECOMMENDED SERIAL INTERFACE FOR
TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA". In Appendix B the transceiver related data are given.
www.vishay.com
16
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Appendix B
IrDA Serial Interface Basics
The serial interface for transceiver control (SITC) is a
master/slave synchronous serial bus which uses the
Txd and Rxd as data lines and the SCLK as clock line
with a minimum period of 250 ns. The transceiver
works always as slave and jump into SITC mode on
the first rising edge of the clock line remaining there
until the command phase is finished. After power on it
is required an initial phase for ≥ 30 clock cycles at Txd
is continuous low before the transmitter can be pro-
grammed. If Txd assume high during the initial phase
then must start the initial phase again.
Application Guideline
In the following some guideline is given for handling
the TFDU8108 in an application ambient, especially
for testing. It is also a guideline for interfacing with a
controller. We recommend to use for first evaluation
the Vishay IRM1802 controller. For more information
see the special data sheet. Driver software is avail-
able on request. Contact irdc@vishay.com.
Serial Interface Capability of the Vishay
IrDA Transceivers
Abstract
The data transfer is organized by one byte preceded
by one start bit. The SITC allows the communication
between infrared controller and transceiver through
A serial interface allows an infrared controller to com- write and read transaction. The SITC consists of two
municate with one or more infrared transceivers. The store blocks with different functions. The store block
basic specification of IrDA) specified interface is called Extended Indexed Registers contain the vari-
described in "Serial Interface for Transceiver Control, ous supported functionality of the device and can be
v 1.0a", IrDA.
read only. The other Main Control Registers allow
write and read transaction and store the executable
configuration of the device.
This part of the document describes the capabilities of
the serial interface implemented in the Vishay IrDA
transceivers TFDU8108 and TFDU6108. The VFIR Any configuration is executed after the command
(16 Mbit/s) and FIR (4 Mbit/s) programmable versions phase is completed.
are using the same interface specification. (with spe-
cific identification and programming).
Power-on
After power on the transceiver is to stay by definition in the default mode shown in the table.
Function
Power Mode
RX
TFDU8108
sleep
disable (Z)
disable
TX_LED:
APEN
disable
Infrared Mode
Transmitter Power
SIR
max. SIR power level
Addressing
The transceiver is addressable with three address bits. There are individual and common addresses with the following values.
Description
Address value A [2:0]
Individual address
Mask programmable
010
111
Common (broadcast) address
enabled (see above). It is strongly recommended that
this functionality is enabled to be on the safe side for
correct data transmission during SITC mode.
Data Acknowledgement
Data acknowledgement generated by the slave is
available if the APEN bit is set to 1 in the common
control register. In IrDA default state this functionality
is disabled. In default state of the TFDU8108 it is
Document Number 82558
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17
TFDU8108
Vishay Semiconductors
Registers Data Depth
In general the whole data registers consist of a data
depth of eight bits. But sometimes it is unnecessary to
implement the full depth. In such a case the invisible
bits consider like a zero.
Used Index Commands
The table shows the valid index commands, its allowable modes, and the data depth to them.
Commands INDEX
[3:0]
Mode
Actions
Register Name
Data Bits
TFDU8108
default
0h
1h
W/R
W/R
W/R
X
Common control
Infrared mode
Txd power level
Not used
main-ctrl-0 register
main-ctrl-1 register
main-ctrl-2 register
[4:0]
[7:0]
[7:4]
00h
00h
70h
2h
Bh - 3h
Ch
X
Not used
Dh
W
Reset transceiver,
Only one byte!
R
X
Not used
Not used
Eh
Fh
W
R
Not used
Extended indexing
Note: The main_ctrl_1 register is written software dependent on the offset value stored in ext_ctrl_7 and ext_ctrl_8 registers.
The main_ctrl_1 register can be set to the following values, shown in the table.
Main-ctrl-0 register values
Value
Function
Default
sleep
bit 0
PM SL - Power Mode Select
0 > low power mode (sleep mode)
1 > normal operation power mode
bit 1
bit 2
RX OEN - Receiver Output Enable
0 > IRRX/SRDAT line disable (tri-stated)
1 > IRRX/SRDAT line enabled
disable
disable
TLED EN - Transmitter LED Enable
0 > disabled
1 > enabled
bit 3
bit 4
not used
not used
disable
1)
APEN
1)
APEN - Acknowledge Pulse Enable, (optional)
This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will
be pulsed low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast)
transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1.
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Document Number 82558
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TFDU8108
Vishay Semiconductors
Main-ctrl-1 register values
Value
00h
01h
02h
03h
Funtion
SIR (default)
MIR
FIR
®
Apple Talk (FIR functionality)
VFIR - 16
05h
08h
®
Sharp IR (SIR functionality)
Depending on the values of "ext_ctrl_7" and "ext_ctrl_8" it must be checked if the value for main_ctrl_1 is correct. If it cause an error then
the transceiver will load 00h into the main_ctrl_1 register and will not give an acknowledgement.
Main-ctrl-2 register values
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
x
bit 1
x
bit 0
x
Mode
Txd - IRED
[mA]
Remark
8xh-
Fxh
1
x
x
x
x
VFIR > 1 m,
FIR > 1 m
not for SIR!
550
(switch, ext.
R1!)
VFIR/FIR standard,
serial resistor is
necessary for
V
> 4 V
CC2
1)
0
0
0
1
1
1
1
1
0
1
0
1
x
x
x
x
SIR >1 m
FIR > 0.7 m
VFIR > 0.7 m
250
125
60
SIR, More Ext.
VFIR/FIR LP
7xh
6xh
SIR > 0.7 m
FIR > 0.45 m
VFIR > 0.45 m
Extended VFIR/FIR
Low Power
5xh
SIR > 0.5 m
FIR > 0.3 m
VFIR > 0.3 m
VFIR/FIR Low Power
4xh
3xh
0
0
1
0
0
1
0
1
(45)
30
SIR > 0.35 m
FIR > 0.2 m
VFIR > 0.2 m
SIR Low Power
e.g. Docking station
e.g. Docking station
2xh
1xh
0xh
0
0
0
0
0
0
1
0
0
0
1
0
SIR > 0.25 m
FIR > 0.15 m
VFIR > 0.2 m
15
8
SIR > 0.15 m
FIR > 0.1 m
VFIR > 0.1 m
x
x
x
x
0
1)
IrDA default setting
Document Number 82558
Rev. 1.6, 12-Aug-04
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19
TFDU8108
Vishay Semiconductors
Used Extended Indexed Registers
The table shows the valid extended indexed commands its allowable modes and the data depth to them.
Register
Address
E_INDEX [7:0]
Mode
Action
Register Name
Data Bits
Fixed Value
0:4h
00h
01h
R
R
Manufactured ID
Device ID
Ext_Ctrl_0
Ext_Ctrl_1
[7:0]
[7:0]
[7:6] <- 11
[5:3] <- xxx
[2:0] <- xxx
xxx: Version
number
24h
04h
05h
R
R
Receiver recovery time
Power on stabilization
Ext_Ctrl_4
Ext_Ctrl_5
[6:4, 2:0]
[6:4, 2:0]
Receiver stabilization
SCLK max. frequency
30h
06h
07h
08h
R
R
R
X
Common capabilities
Supported Infrared modes
Supported Infrared modes
Ext_Ctrl_6
Ext_Ctrl_7
Ext_Ctrl_8
[7:0]
[7:0]
0
03h
0Fh
01h
09h - FFh
Not used
except F0h
(See 1.1.7)
F0h
R
Chip specific register
Ext_Ctrl_240
[7:0]
Not disclosed
Invalid Commands Handling
There are some commands and register addresses, which cannot be decoded by the SITC. The slave ignores such invalid data for the
internal logic. Below the different types and the slave reaction to them are shown.
Description
Master Command
Index [3:0] & C = 0
Index [3:0] & C = 1
Slave Reaction on IRRX/SRDAT
no reaction
Invalid command in read mode
Invalid command in write mode
No acknowledgement generating
independent of the value of APEN
Valid command in invalid read mode
Valid command in invalid write mode
Index [3:0] & C = 0
Index [3:0] & C = 1
no reaction
No acknowledgement generating
independent of the value of APEN
Valid command in invalid write mode and
invalid data
Index [3:0] & C = 1
No acknowledgement generating
independent of the value of APEN
Broadcast address in read mode
A [2:0] = 111 & C = 0
no reaction
No reaction means that the slave does not start the respond phase.
Reset
There is no external reset pin at Vishay IrDA trans-
ceivers. In case of transition error there are two ways
to set the SITC in a defined state: The first one is
power off. The second one is that the transceiver
monitors the IRTX/SWDAT line in any state. If this line
is assumed low for ≥ 30 clock cycles then the trans-
ceiver must be set to the command start state and set
all registers to default implemented values.
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20
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Appendix C
SCLK
Serial Interface (SIF) Programming Guide
The SIF port of this module allow an IR controller to
communicate with it, get module ID and capability
information, implement receiver bandwidth mode
switching, LED power control, shutdown and some
other functions.
TX
Tsetup > 10 ns
Thold > 10 ns
125 ns < Tclk
s
18496
This interface requires three signals: a clock line
(SCLK) that is used for timing, and two unidirectional
lines multiplexed with the transmitter (Txd, write) and
receiver (Rxd, read) infrared signal lines.
The supported programming sequence formats are
listed below:
one-byte special commands
two-byte write commands
two-byte read commands
Protocol Specifications
The serial interface protocol is a command-based
communication standard and allows for the communi-
cation between controller and transceiver by way of
serial programming sequences on the clock (SCLK),
transmit (TX), and receive (RX) lines. The SCLK line
is used as a clocking signal and the transmit/receive
lines are used to write/read data information. The pro-
tocol requires all transceivers to implement the write
commands, but does not require the read-portion of
the protocol to be implemented (though all transceiv-
ers must at least follow the various commands, even
if they perform no internal action as a result). This
serial interface follows but does not support all read/
write commands or extended commands, supporting
only the special commands and basic write/read com-
mands.
three-byte read commands
The one-byte special command sequences are
reserved for time-critical actions, while the two-byte
write command is predominantly used to set basic
transceiver characteristics. More information can be
found in the IrDA document "Serial Interface for
Transceiver Control, v 1.0a" on IrDA.org web site.
Serial Interface Timing Specifications
In general, serial interface programming sequences
are similar to any clocked-data protocol:
Write commands to the transceiver take place on the
SCLK and TX lines and may make use of the RX line
for answer back purposes.
A command may be directed to a single transceiver
on the SCLK, TX and RX bus by specifying a unique
three-bit transceiver address, or a command may be
directed to all transceivers on the bus by way of a spe-
cial three-bit broadcast address code. The Vishay
VFIR transceiver TFDU8108 will respond to trans-
ceiver address 010 and the broadcast address 111
only, and follows but ignores all other transceiver
addresses. The transceiver address of Vishay FIR
module TFDU6108 is 001.
•
there is a range of acceptable clock rates, mea-
sured from rising edge to rising edge
• there is a minimum data setup time before clock ris-
ing edges
• there is a minimum data hold time after clock rising
edges
Recommended programming timing:
(4 kHz <) fclk < 8 MHz (4 kHz is a recommended
value, according to the Serial Interface Standard
quasi-static programming is possible)
TCLK > 125 ns (< 250 µs, see the remark for quasi-
static programming above)
All commands have a common \"header\" or series of
leading bits which take the form shown below.
Tsetup > 10 ns
Thold > 10 ns
last bit sent to
transceiver
first bit sent to
transceiver
The timing diagrams below show the setup and hold
time for Serial Interface programming sequences:
...
0
1 1/0 R0 R1 R2 R3 A0 A1 A2
1=Write
0=Read
Register
Transceiver
Address
Sync
Bits
Address
18497
or Code
Document Number 82558
Rev. 1.6, 12-Aug-04
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21
TFDU8108
Vishay Semiconductors
The bits shown are placed on the TX (DATA) line and One-byte Special Commands
clocked into the transceiver using the rising edge of One-byte special commands are used for time-critical
the SCLK signal. Only the data bits are shown as it is transceiver commands, such as full transceiver reset.
assumed that a clock is always present, and that the A total of six special commands are possible,
transceiver samples the data on the rising edge of although only one command is available on the
each clock pulse.
TFDU8108 and TFDU6108.
Note: as illustrated in the diagram above, the protocol
uses "Little Endian" ordering of bits, so that the LSB is
sent first, and the MSB is sent last for register
addresses, transceiver addresses, and read/write
data bytes. The notation that follows presents all
addresses and data in LSB-to-MSB order (bits 0, 1, 2,
3, ... 7) unless otherwise stated.
0
1
1
R0 R1 R2 R3 A0 A1 A2
0
0
Sync Write
Bits
Special
Command
Code
Transceiver
Address
Stop
Bits
18498
Command
Module Type
TFDU6108
TFDU8108
Programming Sequence
(Binary)
Programming Sequence
(Hex)
RESET
011 1011 100 00
3B
(Set all registers to default value)
011 1011 010 00
5B
Two-byte Write Commands
The basic two-byte write command is illustrated
Two-byte write commands are used for setting the below:
contents of transceiver registers which control trans-
ceiver such as shutdown/enable, receiver mode, LED
0
1
1
R0 R1 R2 R3 A0 A1 A2
1
D0..D7
0
0
power level, etc.
The register space requires four register address bits
(R0-3), although three codes are used for controlling
transceiver (see above), and the 1111 escape code is
for extended commands. The 3-bit transceiver
address (A0-3) is for selecting the destination, e.g.
010 to TFDU8108 and 001 to TFDU6108.
The second byte is data field (D0-7) for setting the
characteristics of the transceiver module, e.g. SIR
mode (00) or VFIR (05) when the register address is
0001.
Sync Write
Bits
Transceiver
Address
8-Data Stop
Bits Bits
Register
Address
18499
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22
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Some important serial interface programming
sequences are shown below:
Command
TFDU6108 Programming Sequence
TFDU8108 Programming Sequence
(Transceiver address: 010)
(Transceiver address: 001)
Common Ctrl (0000)
Normal (Enable all)
Shutdown
Receiver Mode (0001)
SIR
Value (hex)
0F
011 0000 100 1 11110000 00
011 0000 100 1 00000000 00
011 0000 010 1 11110000 00
011 0000 010 1 00000000 00
00
Value (hex)
00
011 1000 100 1 00000000 00
011 1000 100 1 10000000 00
011 1000 100 1 01000000 00
011 1000 100 1 11000000 00
011 1000 100 1 10100000 00
011 1000 100 1 00010000 00
011 1000 010 1 00000000 00
011 1000 010 1 10000000 00
011 1000 010 1 01000000 00
011 1000 010 1 11000000 00
011 1000 010 1 10100000 00
011 1000 010 1 00010000 00
MIR
01
FIR
02
Apple Talk
VFIR
03
05
Sharp-IR
LED Power (0010)
8 mA
08
Value (hex)
1X
2X
3X
5X
6X
7X
FX
011 0100 100 1 00001000 00
011 0100 100 1 00000100 00
011 0100 100 1 00001100 00
011 0100 100 1 00001010 00
011 0100 100 1 00000110 00
011 0100 100 1 00001110 00
011 0100 100 1 00001111 00
011 0100 010 1 00001000 00
011 0100 010 1 00000100 00
011 0100 010 1 00001100 00
011 0100 010 1 00001010 00
011 0100 010 1 00000110 00
011 0100 010 1 00001110 00
011 0100 010 1 00001111 00
15 mA
30 mA
60 mA
125 mA
250 mA
500 mA
Document Number 82558
Rev. 1.6, 12-Aug-04
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TFDU8108
Vishay Semiconductors
Reel Dimensions
W
1
Reel Hub
W
2
14017
Tape Width
A max.
N
W min.
W max.
W min.
W max.
1
2
3
3
mm
24
mm
330
mm
60
mm
mm
mm
mm
24.4
30.4
23.9
27.4
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24
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Tape Dimensions in mm
18269
Document Number 82558
Rev. 1.6, 12-Aug-04
www.vishay.com
25
TFDU8108
Vishay Semiconductors
18283
www.vishay.com
26
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and
operatingsystems with respect to their impact on the health and safety of our employees and the public, as
well as their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are
known as ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs
and forbid their use within the next ten years. Various national and international initiatives are pressing for an
earlier ban on these substances.
Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use
of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design
and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each
customer application by the customer. Should the buyer use Vishay Semiconductors products for any
unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all
claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal
damage, injury or death associated with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
Document Number 82558
Rev. 1.6, 12-Aug-04
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27
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