7P064FVF1100C20 [WEDC]
Flash Card, 32MX16, 200ns, CARD-68;
| 型号： | 7P064FVF1100C20 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Flash Card, 32MX16, 200ns, CARD-68 |
| 文件： | 总16页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FVF Series
White Electronic Designs
PCMCIA FLASH MEMORY CARD — FVF SERIES
FVF Value Series Flash Memory Card 4, 8, 16, 32, 48 and 64MB(Intel Strata Flash )
FEATURES
GENERAL DESCRIPTION
ꢀ
PCMCIA 2.1 (PC Card 97) compatible
The FVF Value Series Flash memory cards offer a low cost linear
Flash solid state storage solution for code and data storage,
high performance disk emulation, mobile PC and embedded
applications.
• Type I or Type II Form Factor
Low cost Linear Flash Card
Single Supply Operation
ꢀ
ꢀ
FVF series cards offer memory capacities from 4MB to 64MB, with
128kB block erase size.
• FVF0x - 5V
• FVF1x - 5V or 3.3V (Note 1)
Fast Read Performance
The WEDC Value series is based on Intel MLC, Strata Flash
memories. Cards are based on the two families of memory
components:
ꢀ
• 200ns Maximum Access Time
Based on MLC Strata Flash Components
Common Flash Interface (CFI) compliant
High Performance Random Writes
FVF0x built with: 28F640J5, 28F320J5
FVF1x built with: 28F128J3, 28F640J3, 28F320J3
ꢀ
ꢀ
ꢀ
These flash devices support the Common Flash Interface (CFI)
programming algorithm, a standard that allows system level
software to evaluate the flash configuration, electrical characteristic,
programming parameters and supported functions. CFI is intended
to support future upgrades with universal programming algorithms,
so there is no longer a need for continued programming software
modification and updates. Systems should be able to recognize and
support all devices to allow universal expansion/upgrade path.
• 6µs Typical per Byte Write Time, using
32Byte Write buffer
ꢀ
ꢀ
Automated Write and Erase Algorithms
High Write/Erase Endurance:
• 100,000 Write/Erase Cycles
Low Power Consumption
ꢀ
The symmetrically blocked architecture and single supply (5V
for FVF0x and universal 3.3V or 5V for FVF1x cards) operation
provides a cost effective, high performance, nonvolatile storage
solution. The PC Card form factor offers an industry standard pinout
and mechanical outline, allowing density upgrades without system
design changes.
• 150µA Standby Current
• 75mA Max Byte Write Current
The Value series is designed as a simple x16 linear array of Flash
devices. One Flash device provides the lower and upper bytes for
the 16 bit access. Other modes of operation are also supported
(See Functional Truth Table on page 5)
Note 1:
FVF1x supports wide, universal operating voltage: 3V to 5V.
That means the card will work in 3.3V systems as well as in 5V systems.
This feature may allow easy exchange of data between multiple and
different systems and provide easy upgrade / expansion path.
WEDC’s standard Value Series Flash Card is shipped with no
attribute memory or CIS (Card Information Structure) information.An
option for 2KB of attribute memory with CIS information is available.
The CIS for the WEDC Value series may also be stored in Block
0 (even bytes, D0 - D7 only) of the Flash memory. This option is
available by request only.
WEDC’s standard cards are shipped with WEDC’s Logo. Cards are
also available with blank housings (no Logo). The blank housings
are available in both a recessed (for label) and flat housing. Please
contact WEDC sales representative for further information on
Custom artwork.
October 2001
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
FVF BLOCK DIAGRAM
MANUFACTURER AND DEVICE ID CODES
Device
Manuf ID
89h
89h
89h
89h
89h
Device ID
18h
17h
16h
15h
14h
Int 28F128J3
Int 28F640J3
Int 28F320J3
Int 28F640J5
Int 28F320J5
Addresses
A1..A25
(note 1)
Addresses
A1..A25
CSn#
CE#
OE#
CS1#
CS0#
WE#
CE#
CE#
CE1#
CE2#
28F640J5
28F320J5
28F128J3
28F640J3
28F320J3
D15..8
Memory
High Byte
DATA Low
D15..8
D7..0
Memory
Low Byte
DATA Low
D7..0
PD#
R/B
BVD1
Vcc
BVD2
Attribute Memory
(optional)
RDY/BSY#
RST
Reset
Circuit
- pull down resistor Typ. 100kΩ
- pull up resistor Min. 10kΩ
VS1
VS2
open/GND
(note 2)
open
CD1
CD2
Notes:
1. A25..23 pulled down by 100k Ω resistors
2. Open for FVF0x; GND for FVF1x (3.3V operation)
October 2001
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
For information regarding modes of operation, commands, and programming
details for the memory components, please consult the Intel 28F128J3A,
28F640J5 data sheets.
Writing commands to the CUI enables reading of device
data, query, identifier codes, inspection and clearing of the
status register, and, when VPEN = VPENH, block erasure,
program, and lock-bit configuration.
device to be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory location.
It is written when the device is enabled and WE# is active.
The address and data needed to execute a command are
latched on the rising edge of WE# or the first edge of CE1#
or CE2# that disables the card. Standard microprocessor
write timings are used.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
Byte/Word Program command requires the command and
address of the location to be written. Set Block Lock-Bit
commands require the command and block within the
October 2001
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
PINOUT
Pin
1
2
3
4
5
6
7
8
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
I/O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
I/O
Function
Active
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
O
I/O
I/O
I/O
I/O
I
LOW
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
LOW
LOW
I
O
LOW
NC or GND (2)
9
OE#
A11
A9
A8
A13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
Reserved
I
I
I
I
I
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus Cycle
Reserved
Attrib Mem Select NC (optional)
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
LOW
LOW (1)
N.C.
N.C.
I
I
I
I
I
I
I
I
I
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
VS2
RST
O
I
O
N.C.
HIGH
Low
Wait#
RFU
REG#
BVD2
BVD1
DQ8
I
O
O
I/O
I/O
O
I
I
I/O
I/O
I/O
O
Data bit 1
Data bit 2
Write Potect
Ground
DQ9
Data bit 9
Data bit 10
Card Detect 2
Ground
DQ10
CD2#
GND
HIGH
O
LOW
GND
Notes:
1. RDY/BSY signal is an open drain output, with MIN 47k Ω pull-up resistor.
2. N.C. for FVF0x (5V only operation)
GND for FVF1x (3.3V or 5V operation)
October 2001
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
PACKAGE DIMENSIONS
Interconnect area
3.0mm MIN
10.0mm MIN
1.6mm
(0.400”)
0.05
1.0mm 0.05
(0.039”)
(0.063”)
Substrate area
54.0mm 0.10
(2.126”)
85.6mm 0.20
(3.370”)
1.0mm 0.05
(0.039”)
10.0mm MIN
(0.400”)
3.3mm T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
October 2001
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
CARD SIGNAL DESCRIPTION
Symbol
A0 - A25
Type
INPUT
Name and Function
ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is
used only in 8 bit configuration (CE1# active CE2# not active). A0 is disregarded in 16 bit operation (CE1# and CE2#
active). The system should not try to access memory beyond the card density because the card will return undefined
data. (The upper addresses are decoded).
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ0 - DQ7 constitute the lower
(even) byte and DQ8 - DQ15 the upper (odd) byte. DQ15 is the MSB.
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. (See below the
Functional Truth Table).
OUTPUT ENABLE: Active low signal enabling read data from the memory card.
WRITE ENABLE: Active low signal gating write data to the memory card.
READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that
the card is ready to accept accesses.
CARD DETECT 1 and 2: Provide card insertion detection. These signals are connected to ground internally on the
memory card. The host socket interface circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.
WRITE PROTECT: This signal is pulled low internally. This signifies write protect = “off “ for all cases.
PROGRAM/ERASE POWER SUPPLY: Not connected for 5V only card.
CARD POWER SUPPLY: (5.0V for FVF0x or 3V to 5V for FVF1x)
DQ0 - DQ15
CE1#, CE2#
INPUT /
OUTPUT
INPUT
OE#
WE#
RDY/BSY#
INPUT
INPUT
OUTPUT
CD1#, CD2#
OUTPUT
WP
VPP1, VPP2
VCC
GND
REG#
OUTPUT
N.C.
GROUND:
INPUT
INPUT
ATTRIBUTE MEMORY SELECT: connected only on cards built with optional attribute memory. (see Note 1)
RESET: Active high signal for placing card in Power-on default state.
RST
WAIT#
BVD1, BVD2
VS1, VS2
OUTPUT
OUTPUT
OUTPUT
WAIT: This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE: Notifies the host socket of the card’s VCC requirements. VS1 and VS2 are open to indicate a 5V;
VS1=GND and VS2 open indicate possibility to work in 3.3V systems.
RFU
N.C.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating
FUNCTIONAL TRUTH TABLE
READ function
Function Mode
Standby Mode
Common Memory
D15-D8
Attribute Memory
D15-D8
CE2# CE1# A0 OE# WE#
REG#
X
H (1)
H (1)
H (1)
H (1)
D7-D0
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
REG#
D7-D0
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
X
L
L
L
L
High-Z
High-Z
High-Z
Not Valid
Not Valid
Byte Access (8 bits) (3)
Word Access (16 bits) (3)
Odd-Byte Only Access
L
WRITE function
Standby Mode
Byte Access (8 bits) (3)
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
X
X
X
X
X
L
L
L
L
X
X
X
X
X
X
H (1)
H (1)
H (1)
H (1)
Even-Byte
Odd-Byte
Even-Byte
X
Even-Byte
X
Even-Byte
X
Word Access (16 bits) (3)
Odd-Byte Only Access (2)
Notes:
Odd-Byte
Odd-Byte
L
1. For standard cards without Attribute memory this signal is not connected: X – don’t care
2. Operation in Shaded row not supported: Accessing memory in this mode may alter data in lower byte For
proper operation signals CE1# and CE2# should be connected together (for 16 bit operation) or signal
CE2# should be always in High state (for 8bit operation)
3. Switching between byte access mode (8 bit) and word access mode (16 bit) requires a 1ms setup time.
October 2001
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Notes: Stress greater than those listed under “Absolute Maximum ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation
at these or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Temperature TA (ambient)
Commercial
0°C to +70 °C
Storage Temerature
Voltage on any pin relative to VSS
-55°C to +110 °C
-0.5V to VCC+0.5V
FVF0x Series
DC CHARACTERISTICS
VCC supply voltage 5V
Symbol
Parameter
Notes
Typ(1)
Max
Units
Test Conditions
ICCR
VCC Read Current
8 bit mode
16 bit mode
20
35
35
65
mA
VCC = VCC MAX
tcycle = 200ns
ICCW
ICCE
VCC Program Current
VCC Erase Current
VCC Sleep Current
1 device active
1 device active
Per device
40
40
80
70
80
mA
mA
µA
ICCSL
125
VCC = 5.25V
Control Signals = VCC
Reset = VIH (active)
ICCS
VCC Standby Current
Per device CMOS
inputs
150
µA
VCC = 5.25V
Control Signals = VCC
Reset = VIL (not active)
CMOS Test Conditions: VIL = VSS 0.2V, VIH = VCC 0.2V
Notes:
1. Typical: VCC = 5V, T = +25°C.
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
ILI
Input Leakage Current
1, 2
20
µA
VCC = VCC MAX
VIN =VCC or VSS
ILO
Output Leakage Current
1
20
µA
VCC = VCC MAX
VOUT =VCC or VSS
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
1
1
1
1
0
0.8
VCC+0.5
0.4
V
V
V
V
V
VIH
2.0
VOL
VOH
VLKO
IOL = 2mA
2.4
VCC
IOH = -2.0mA
VCC Erase/Program
Lock Voltage
3.25
Notes:
1. Values are the same for byte and word wide modes for all card densities.
2. Exceptions: Leakage currents on CE1#, CE2#, OE#, REG# and WE# will be < 500 µA when VIN = GND due to internal pull-up resistors. Leakage currents on RST will be <150µA
when VIN=VCC due to internal pull-down resistor.
October 2001
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
FVF1x Series
DC CHARACTERISTICS
VCC supply voltage 3V - 5V
Symbol
Parameter
Notes
Typ(1)
Max
Units
Test Conditions
ICCR
VCC Read Current
16 bit mode
VCC = 3.3V
VCC = 5.0V
35
45
55
65
mA
VCC = VCC MAX
tcycle = 200ns
ICCW
ICCE
VCC Program Current
VCC Erase Current
VCC Sleep Current
VCC = 3.3V
VCC = 5.0V
35
45
60
70
mA
mA
µA
VCC = 3.3V
VCC = 5.0V
35
45
70
80
ICCSL
Per device
80
125
VCC = 3.3V
Control Signals = VCC
Reset = VIH (active)
ICCS
VCC Standby Current
Per device TTL inputs
150
µA
VCC = 3.3V
Control Signals = VCC
Reset = VIL (not active)
CMOS Test Conditions: VIL = VSS 0.2V, VIH = VCC 0.2V
VCC supply voltage 3V - 5V
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
ILI
Input Leakage Current
1, 2
20
µA
VCC = VCC MAX
VIN =VCC or VSS
ILO
Output Leakage Current
1
20
µA
VCC = VCC MAX
VOUT =VCC or VSS
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
1
1
1
1
0
0.8
VCC+0.5
0.4
V
V
V
V
V
VIH
2.0
VOL
VOH
VLKO
IOL = 2mA
2.4
2.0
3.2
IOH = -2.0mA
VCC Erase/Program
Lockout Voltage
Notes:
1. Values are the same for byte and word wide modes for all card densities.
2. Exceptions: Leakage currents on CE1#, CE2#, OE#, REG# and WE# will be < 500 µA when VIN = GND due to internal pull-up resistors. Leakage currents on RST will be <150µA
when VIN=VCC due to internal pull-down resistor.
October 2001
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
AC CHARACTERISTICS
Read Timing Parameters
200ns
250ns
SYM (PCMCIA)
tRC
ta(A)
ta(CE)
ta(OE)
tsu(A)
tsu(CE)
th(A)
th(CE)
tv(A)
tdis(CE)
tdis(OE)
Parameter
Read Cycle Time
Address Access Time
Min
200
Max
Min
250
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
200
100
20
0
20
20
0
250
250
125
20
0
20
20
0
100
100
Card Enable Access Time
Output Enable Access Time
Address Setup Time
Card Enable Setup Time
Address Hold Time
Card Enable Hold Time
Output Hold from Address Change
Output Disable Time from CE#
Output Disable Time from OE#
Output Enable Time from CE#
Output Enable Time from OE#
90
90
t
en(CE)
5
5
5
5
ten(CE)
trec(RST)
Power Down recovery to Output
Delay, VCC = 5V
500
500
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.
Read Timing Diagram
tc(R)
ta(A)
th(A)
A[25::0], REG#
CE1#, CE2#
tv(A)
ta(CE)
tsu(CE)
NOTE 1
NOTE 1
th(CE)
ta(OE)
tsu(A)
tdis(CE)
OE#
tdis(OE)
ten(OE)
D[15::0]
DATA VALID
Note: Signal may be high or low in this area.
October 2001
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
AC CHARACTERISTICS
Write Timing Parameters
200ns
250ns
SYM (PCMCIA)
tCW
tw(WE)
Parameter
Write Cycle Time
Write Pulse Width
Address Setup Time
Address Setup Time for WE#
Card Enable Setup Time for WE#
Data Setup Time for WE#
Data Hold Time
Min
200
120
20
140
140
60
Max
Min
250
150
30
180
180
80
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(A)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
trec(WE)
tdis(WE)
tdis(OE)
ten(WE)
ten(OE)
tsu(OE-WE)
th(OE-WE)
tsu(CE)
30
30
30
30
Write Recover Time
Output Disable Time from WE#
Output Disable Time from OE#
Output Enable Time from WE#
Output Enable Time from OE#
Output Enable Setup from WE#
Output Enable Hold from WE#
Card Enable Setup Time from OE#
Card Enable Hold Time
90
90
100
100
5
5
10
10
0
5
5
10
10
0
th(CE)
20
20
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.
Write Timing Diagram
tc(W)
A [25::0], REG#
tsu(A-WEH)
trec(WE)
tsu(CE-WEH)
th(CE)
tsu(CE)
CE1#, CE2#
NOTE 1
NOTE 1
OE#
th(OE-WE)
th(D)
tw(WE)
tsu(A)
WE#
tsu(OE-WE)
NOTE 2
tsu(D-WEH)
D[15::0](Din)
DATA INPUT
tdis(WE)
tdis(OE)
ten(OE)
ten(WE)
NOTE 2
D[15::0](Dout)
Note:
1. Signal may be high or low in this area.
2. When the data I/O pins are in the output state, no signals shall be
applied to the data pins (D15 -D0) by the host system.
October 2001
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
DATA WRITE AND ERASE PERFORMANCE (1, 2, 3 ,4)
FVF0x: VCC = 5V 5ꢀ, FVF1x: VCC = 3V – 5V
Parameter
Notes
Min
Typ(1)
Max
Units
Write Buffer Byte program time
(time to prog. 32Bytes/16Words)
- J5 device
- J3 device
218
200
654
TBD
µs
Byte Program time
- J5 device
- J3 device
210
180
630
µs
sec
sec
-Using Word/Byte prog command
TBD
Block Program Time
128kB written using Write to Buffer
- J5 device
- J3 device
0.8
0.8
2.4
TBD
Block Erase Time
- J5 device
- J3 device
1
0.7
5
TBD
Notes:
1. Typical: Nominal voltages and TA = 25°C.
2. Excludes system overhead.
3. Valid for all speed options.
4. To maximize system performance, RDY/BSY# signal or component status register should be polled.
October 2001
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
PRODUCT MARKING
WED 7P016FVF0100C20 C995 9915
EDI
Date code
Lot code / trace number
Part number
Company Name
Note:
Some products are currently marked with our pre-merger company name/
acronym (EDI). During our transition period, some products will also be marked
with our new company name/acronym (WED). Starting October 2001 all
PCMCIA products will be marked only with the WED prefix.
PRODUCT NUMBERING
7 P 016 FVF01 00 C 20
Card access time
20
25
200ns
250ns
Temperature range
C
I
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
Packaging option
00 Standard, type 1
Card family and version
– See Card Family and Version Info. for
details (next page)
Card capacity
016 16MB
PC card
P
R
Standard PCMCIA
Ruggedized PCMCIA
Card technology
7
8
FLASH
SRAM
October 2001
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
ORDERING INFORMATION
7P XXX FVF YY SS T ZZ
where
XXX: 004
008
4MB (built with 28F320)
8MB
016
032
048
064
16MB
32MB
48MB
64MB
YY:
SS:
01
02
J5 based (28F640J5, 28F320J5)
J5 based with attribute memory – not available
11
12
J3 based (28F128J3, 28F640J3, 28F320J3
J3 with attribute memory – not available
00
01
02
WEDC Silkscreen
Blank Housing, Type I
Blank Housing, Type I Recessed
T:
C
Commercial
ZZ:
20
25
200ns
250ns
PART NUMBER TABLE – COMMON OPTIONS
Intel Strata Flash Based Cards
WEDC Part Number
7P004FVF0100C20
7P008FVF0100C20
7P064FVF0100C20
7P016FVF1100C20
7P064FVF1100C20
Density
4MB
Speed
200ns
200ns
200ns
200ns
200ns
Flash Component
28F320J5
Attribute Memory
NO
NO
NO
NO
NO
8MB
28F6400J5
28F640J5
28F128J3
64MB
16MB
64MB
28F128J3
Notes:
1. Other options, including density, architecture and speed are available, please contact your WEDC sales representative with your request.
October 2001
Rev. 1
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
CARD INFORMATION STRUCTURE (CIS)
The CIS is an information describing the PCMCIA card’s
functionality and structure. This information can be used
by host system to determine programming requirements,
needed resources to access the card, etc.
active, it enables Attribute memory and allows access to
CIS data.
Cards without Attribute memory do not contain any CIS
data: they are shipped “blank” with FFhex data. For client’s
request, data can be programmed to common memory
(see below for CIS data).
This information is stored in the form of binary data in
separate memory (Attribute memory), or in the first block of
main (common) memory. Data is stored only on the lower
data byte only (D7..0). Upper byte (D15..8) is disregarded
and its value is undefined. Cards built with separate
Attribute memory have signal REG# connected: when
For detail information about CIS structure please refer to
PCMCIA standard (Metaformat Specification).
October 2001
Rev. 1
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
CIS DATA – (EXAMPLE/REFERENCE)
Address
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
1AH
1CH
1EH
20H
22H
Value
01H
03H
52H
FEH
FFH
18H
03H
89H
18H
FFH
1EH
07H
02H
11H
01H
01H
01H
01H
Description
CISTPL_DEVICE
TPL_LINK
Address
4CH
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
6AH
6CH
6EH
70H
72H
74H
76H
78H
7AH
7CH
7EH
80H
82H
84H
86H
88H
8AH
8CH
8EH
90H
92H
Value
20H
53H
45H
52H
49H
45H
53H
00H
49H
4EH
54H
45H
4CH
20H
53H
54H
52H
41H
54H
41H
20H
46H
4CH
41H
53H
48H
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
Description
SPACE
S
E
R
I
E
S
FLASH = 200ns (device writable)
CARD SIZE: 64MB (note 1)
END OF DEVICE
CISTPL_JEDEC_C
TPL_LINK
Manufacturer ID - INTEL
Device ID - 28F0128J3A (note 2)
END OF DEVICE
END TEXT
I
N
T
E
CISTPL_DEVICEGEO
TPL_LINK
DGTPL_BUS (2 Bytes)
DGTPL_EBS (128kB)
DGTPL_RBS
L
SPACE
S
T
R
A
T
A
SPACE
F
L
A
S
DGTPL_WBS
DGTPL_PART
FLASH DEVICE
NON-INTERLEAVED
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
36H
38H
3AH
3CH
3EH
40H
42H
44H
46H
48H
FFH
15H
7FH
04H
01H
57H
48H
49H
54H
45H
20H
45H
44H
43H
20H
46H
56H
46H
END OF TUPLE
CISTPL_VERS1
TPL_LINK
TPLLV1_MAJOR
TPLLV1_MINOR
W
H
I
T
H
END TEXT
END string
END OF TUPLE
E
SPACE
E
D
C
END TEXT
F
V
F
30H
0
31H
1
4AH
X
Notes:
Card Capacity
8MB
Value
1Eh
3Eh
5Eh
7Eh
BEh
FEh
Device
Device ID
18h
17h
16h
15h
1. Value depends on card capacity: refer to the
capacity table on the right
Int 28F128J3
Int 28F640J3
Int 28F320J3
Int 28F640J5
Int 28F320J5
2. Value depends on component type used: refer to
the device ID table on the right
16MB
24MB
32MB
48MB
14h
64MB
October 2001
Rev. 1
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FVF Series
White Electronic Designs
Document Title
PCMCIA FLASH MEMORY CARD — FVF SERIES
FVF Value Series Flash Memory Card 4, 8, 16, 32, 48 and 64MB(Intel Strata Flash )
Revision History
Rev #
History
Release Date Status
Rev 0
Initial release
October 2000
Rev 1
Final release
October 2001
October 2001
Rev. 1
16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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