EDI8F32128V10MMC [WEDC]
SRAM Module, 128KX32, 10ns, CMOS, SIMM-64;
| 型号： | EDI8F32128V10MMC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | SRAM Module, 128KX32, 10ns, CMOS, SIMM-64 静态存储器 内存集成电路 |
| 文件： | 总6页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8F32128V
128K x 32 Static RAM CMOS, High Speed Module
DESCRIPTION
FEATURES
128K x 32 bit CMOS Static RAM
Access Times: 10 and 12ns
Individual Byte Selects
The EDI8F32128V is a high speed 4 megabit Static RAM module
organized as 128K words by 32 bits. This module is constructed
from four 128K x 8 Static RAMs in SOJ packages on an epoxy
laminate (FR4) board.
Fully Static, No Clocks
Four chip enables (EØ-E3) are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes
or any combination of multiple bytes through proper use of
enables.
TTL Compatible I/O
High Density Package
JEDEC Standard Pinouts
64 Pad SIMM, No. 38
The EDI8F32128V is offered in 64 pin ZIP and 64 Pad SIMM
packages, which enable four megabits of memory to be placed in
less than 1.3 square inches of board space.
64 Pin ZIP, No. 39
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous circuitry requires no clocks
or refreshing for operation and provides equal access and cycle
times for ease of use.
Common Data Inputs and Outputs
Single +3.3V (±10%) Supply Operation
Two pins, PD1 and PD2, are used to identify module memory
density in applications where alternate modules can be inter-
changed.
FIG. 1
PIN CONFIGURATIONS AND BLOCK DIAGRAM
PIN NAMES
AØ-A16
EØ-E3
W
Address Inputs
Chip Enables
A
0-16
17
1
3
5
7
9
VSS
PD2
DQ8
DQ9
DQ10
PD1
DQ0
DQ1
DQ2
2
4
6
8
W
G
Write Enable
DQ3 10
VCC 12
A7 14
A8 16
A9 18
DQ4 20
DQ5 22
DQ6 24
DQ7 26
28
A14 30
E0 32
11 DQ11
13 A0
15 A1
G
Output Enable
Common Data Input/Output
Power (+3.3V±10%)
Ground
128K x 8
128K x 8
128K x 8
DQ0-7
8
8
8
8
DQØ-DQ31
VCC
17 A2
19 DQ12
21 DQ13
23 DQ14
25 DQ15
27 VSS
29 A15
31 E1
E0
VSS
W
NC
No Connection
DQ8-15
DQ16-23
DQ24-31
33 E3
35 NC
E2 34
A16 36
E1
E2
E3
37
G
VSS 38
DQ16 40
DQ17 42
DQ18 44
DQ19 46
A10 48
A11 50
A12 52
A13 54
DQ20 56
DQ21 58
DQ22 60
DQ23 62
VSS 64
39 DQ24
41 DQ25
43 DQ26
45 DQ27
47 A3
49 A4
51 A5
53 VCC
55 A6
57 DQ28
59 DQ29
61 DQ30
63 DQ31
128K x 8
8F32128V Pin Conf
PD1 = Open
PD2 = Open
8F32128V Blk Dia
Aug, 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
1
EDI8F32128V
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Sym
VCC
VSS
VIH
Min
3.0
0
2.2
-0.3
Typ
3.3
0
--
--
Max
3.6
0
Vcc +0.3
0.8
Units
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Storage Temperature
Power Dissipation
-0.5V to 4.6V
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
0°C to +70°C
-55°C to +125°C
2.5 Watts
VIL
Output Current.
20 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
3ns
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
1.5V
1TTL, CL = 30pF
Note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF.
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
ICC1
Conditions
Min
Max
12-25ns
480
Units
mA
Operating Power
W, E = VIL, II/O = 0mA,
Supply Current
Standby (TTL) Power
Supply Current
Full Standby Power
Supply Current CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Min Cycle
E ³VIH, VIN £ VIL or
VIN ³ VIH
ICC2
ICC3
120
40
mA
E ³ VCC - 0.2V
mA
VIN ³VCC - 0.2V or VIN £ 0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
ILI
ILO
VOH
VOL
±20
±20
--
µA
µA
V
2.4
--
IOL = 8.0mA
0.4
V
*Typical: TA = 25°C, VCC = 5.0V
CAPACITANCE
(F=1.0MHZ, VIN=VCC OR VSS)
TRUTH TABLE
Parameter
Address Lines
Data Lines
Chip Enable Line
Write Line
Sym
CI
CD/Q
CC
Max
45
20
20
45
Unit
E
H
L
W
X
H
L
G
X
L
Mode
Standby
Read
Write
Output
Deselect
Output
HIGH Z
DOUT
DIN
Power
ICC2/ICC3
ICC1
pF
pF
pF
pF
L
X
ICC1
CN
L
H
H
HIGH Z
ICC1
These parameters are sampled, not 100% tested.
Aug. 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
2
EDI8F32128V
AC CHARACTERISTICS READ CYCLE
Symbol
JEDEC
10ns
Min Max
10
10
10
3
12ns
Min Max
12
12
12
3
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Alt.
TRC
TAA
Units
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV
TAVQV
TELQV
TELQX
TEHQZ
TAVQX
TGLQV
TGLQX
TGHQZ
TACS
TCLZ
TCHZ
TOH
TOE
5
6
3
3
5
5
TOLZ
TOHZ
0
0
5
6
ns
Note 1: Parameter guaranteed, but not tested.
FIG. 2
READ CYCLE 1 - W HIGH, G, E LOW
TAVAV
A
ADDRESS 1
ADDRESS 2
TAVQX
TAVQV
Q
DATA 2
DATA 1
8F32128V Rd Cyc1
FIG. 3
READ CYCLE 2 - W HIGH
TAVAV
A
TAVQV
E
TELQV
TELQX
TEHQZ
TGHQZ
G
Q
TGLQV
TGLQX
8F32128V Rd Cyc2
Aug, 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
3
EDI8F32128V
AC CHARACTERISTICS WRITE CYCLE
Symbol
JEDEC
10ns
Min Max
12ns
Min Max
Parameter
Alt.
Units
Write Cycle Time
TAVAV
TWC
10
12
ns
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TELWH
TWLEH
TAVWL
TAVEL
TAVWH
TAVEH
TWLWH
TELEH
TCW
TCW
TAS
TAS
TAW
TAW
TWP
TWP
7
7
0
0
7
7
7
7
8
8
0
0
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
Write Recovery Time
Data Hold Time
TWHAX
TEHAX
TWHDX
TEHDX
TWR
TWR
TDH
TDH
0
0
0
0
0
0
0
0
ns
ns
ns
ns
Write to Output in High Z (1)
Data to Write Time
TWLQZ
TDVWH
TDVEH
TWHZ
TDW
TDW
0
5
5
5
0
6
6
6
ns
ns
ns
Output Active from End of Write (1)
TWHQX
TWLZ
3
3
ns
Note 1: Parameter guaranteed, but not tested.
FIG. 4
WRITE CYCLE 1 - W CONTROLLED
TAVAV
TELWH
A
E
TWHAX
TAVWH
TWLWH
W
TAVWL
TDVWH
HIGH Z
TWHDX
DATA VALID
D
TWHQX
TWLQZ
Q
8F32128C Write Cyc1
Aug. 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
4
EDI8F32128V
FIG. 5
WRITE CYCLE 2 - E CONTROLLED
TAVAV
A
TAVEL
TELEH
E
TAVEH
TEHAX
TEHDX
TWLEH
W
D
TDVEH
DATA VALID
HIGH Z
Q
8F32128V Write Cyc2
Aug, 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
5
EDI8F32128V
PACKAGE NO. 38
64 LEAD SIMM
038-8F32128V Pkg
PACKAGE NO. 39
64 PIN ZIP PLASTIC
039-8F32128V Pkg
ORDERING INFORMATION
Part Number
Speed
(ns)
10
12
20
25
Package
No.
38
EDI8F32128V10MMC
EDI8F32128V12MMC
EDI8F32128V10MZC
EDI8F32128V12MZC
38
39
39
Note: For Gold SIMM, change EDI8F to EDI8G.
Aug. 2001 Rev. 0
ECO # 14560
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
6
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