EDI8F32256C-MM [ETC]
SRAM Modules ; SRAM模块\n
| 型号： | EDI8F32256C-MM |
| 厂家： | 
ETC |
| 描述： | SRAM Modules
|
| 文件： | 总8页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8F32256C
256Kx32 SRAM Module
Features
256Kx32 Static RAM
CMOS, High Speed Module
256Kx32 bit CMOS Static
Random Access Memory
• Access Times
The EDI8F32256C is a high speed 8 megabit Static RAM
module organized as 256K words by 32 bits. This module is
constructedfromeight256Kx4Static RAMs inSOJ packages
on an epoxy laminate (FR4) board.
BiCMOS: 10 and 12ns
CMOS: 15, 20, 25, and 35ns
• Individual Byte Selects
• Fully Static, No Clocks
• TTL Compatible I/O
Four chip enables (EØ-E3) are used to independently enable
the four bytes. Reading or writing can be executed on
individual bytes or any combination of multiple bytes through
proper use of selects.
High Density Package with JEDEC Standard Pinouts
• 64 Pin ZIP, No. 85
The EDI8F32256C is offered in 64 pin ZIP/SIMM package
which enables eight megabits of memory to be placed in less
than 1.4 square inches of board space.
• 64 Lead Angled SIMM, No. 32
• 64 Lead SIMM, No. 333
• 64 ZIP Low Profile, No. 188
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous circuitry requires no
clocks or refreshing for operation and provides equal access
and cycle times for ease of use.
• Common Data Inputs and Outputs
Single +5V (±10%) Supply Operation
The ZIP and SIMM modules contain two pins, PD1 and PD2,
which are used to identify module memory density in applica-
tions where alternate modules can be interchanged.
Pin Configurations and Block Diagram
Pin Names
AØ-A17
EØ-E3
W,
Address Inputs
Chip Enables
Write Enables
Output Enable
Common Data Input/Output
Power(+5V±10%)
1
3
5
7
9
VSS
PD2
DQ8
DQ9
DQ10
PD1
DQØ
DQ1
DQ2
DQ3 10
VCC 12
A7 14
A8 16
A9 18
DQ4 20
DQ5 22
DQ6 24
DQ7 26
2
4
6
8
G
11 DQ11
13 AØ
15 A1
DQØ-DQ31
VCC
17 A2
19 DQ12
21 DQ13
23 DQ14
25 DQ15
27 VSS
29 A15
31 E1
VSS
Ground
W
G
W
28
DQØ-DQ3
DQ4-DQ7
A14 30
EØ 32
4
4
4
4
64 Pin
PD1 - VSS
PD2 - VSS
EØ
E1
E2
E3
33 E3
35 A17
37
39 DQ24
41 DQ25
43 DQ26
45 DQ27
47 A3
49 A4
51 A5
53 VCC
55 A6
57 DQ28
59 DQ29
61 DQ30
63 DQ31
E2 34
A16 36
G
DQ8-DQ11
DQ16-DQ19
DQ24-DQ27
DQ12-DQ15
DQ20-DQ23
DQ28-DQ31
VSS 38
DQ16 40
DQ17 42
DQ18 44
DQ19 46
A10 48
A11 50
A12 52
A13 54
DQ20 56
DQ21 58
DQ22 60
DQ23 62
VSS 64
4
4
4
4
Electronic Designs, Inc.
• One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 •
http://www.electronic-designs.com
1
EDI8F32256C Rev. 12 9/98 ECO #10816
Absolute Maximum Ratings*
Recommended DC Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage VIH 2.2
Input Low Voltage VIL -0.3
Sym Min Typ Max Units
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial.
Industrial
Storage Temperature, Plastic
Power Dissipation
-0.5V to 7.0V
VCC 4.5
VSS
5.0
0
5.5
0
V
V
0
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
8.0 Watt
-- VCC+0.3V V
-- 0.8
V
Output Current.
20 mA
AC Test Conditions
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Input Pulse Levels
VSS to 3.0V
5ns
1.5V
1TTL, CL = 30pF
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC Electrical Characteristics
Parameter
Sym
Conditions
Min Max Max Max Max Units
10-12 15ns 20 25-35 ns
1360 1280 1440 1280 mA
480 240 200 200 mA
Operating Power Supply Current
ICC1
W, E = VIL, II/O = 0mA, Min Cycle
E • VIH, VIN - VIL or VIN • VIH
E • VCC-0.2V
VIN • VCC-0.2V or VIN - 0.2V
VIN = 0V to VCC
Standby (TTL) Power Supply Current ICC2
Full Standby Power Supply Current ICC3
CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
80 80 40
40 mA
ILI
ILO
VOH
VOL
--
--
±80 ±80 ±80 ±80 µA
±20 ±20 ±20 ±20 µA
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
2.4
—
—
—
—
—
V
V
0.4 0.4 0.4 0.4
*Typical: TA = 25°C, VCC = 5.0V
Capacitance
Truth Table
(f=1.0MHz, VIN=VCC or VSS)
E
H
L
L
L
W
X
H
L
G
X
L
X
H
Mode
Standby
Read
Output
Power
ICC3
ICC1
ICC1
ICC1
HIGH Z
DOUT
DIN
Parameter
Address Lines
Data Lines
Chip Enable Line
Write Control Line
Sym
CI
CD/Q
CC
Max
60
20
20
60
Unit
pF
pF
pF
pF
Write
H
Output Deselect HIGH Z
CN
These parameters are sampled, not 100% tested.
EDI8F32256C
256Kx32 SRAM Module
2
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
AC Characteristics Read Cycle
Symbol
JEDEC Alt.
10ns*
Min Max
10
10
10
3
12ns*
Min Max
12
12
12
3
15ns
Min Max
15
15
15
3
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Units
ns
ns
ns
ns
ns
ns
ns
TAVAV TRC
TAVQV TAA
TELQV TACS
TELQX TCLZ
TEHQZ TCHZ
TAVQX TOH
TGLQV TOE
5
6
8
3
3
3
5
5
8
Output Enable to Output in Low Z (1) TGLQX TOLZ
Output Disable to Output in High Z (1) TGHQZ TOHZ
0
0
0
ns
ns
4
4
5
Note 1: Parameter guaranteed, but not tested.
*BICMOS
Read Cycle 1 - W High, G, E Low
TAVAV
ADDRESS 1
TAVQV
A
Q
ADDRESS 2
TAVQX
DATA 1
DATA 2
Read Cycle 2 - W High
TAVAV
A
TAVQV
E
TELQV
TELQX
TEHQZ
TGHQZ
G
Q
TGLQV
TGLQX
3
EDI8F32256C Rev. 12 9/98 ECO #10816
AC Characteristics Read Cycle
Symbol
JEDEC Alt.
20ns
Min Max
25ns
Min Max
35ns
Min Max
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Units
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV TRC
TAVQV TAA
TELQV TACS
TELQX TCLZ
TEHQZ TCHZ
TAVQX TOH
TGLQV TOE
20
20
20
3
10
3
25
25
25
3
12
3
35
35
35
3
15
3
13
0
15
0
20
0
Output Enable to Output in Low Z (1) TGLQX TOLZ
Output Disable to Output in High Z(1) TGHQZ TOHZ
8
10
12
ns
Note 1: Parameter guaranteed, but not tested.
Read Cycle 1 - W High, G, E Low
TAVAV
ADDRESS 1
TAVQV
A
Q
ADDRESS 2
TAVQX
DATA 1
DATA 2
Read Cycle 2 - W High
TAVAV
A
E
TAVQV
TELQV
TELQX
TEHQZ
G
Q
TGLQV
TGLQX
TGHQZ
EDI8F32256C
256Kx32 SRAM Module
4
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
AC Characteristics Write Cycle
Symbol
JEDEC Alt.
TAVAV TWC
TELWH TCW
TWLEH TCW
TAVWL TAS
10ns*
Min Max
12ns*
Min Max
15ns
Min Max
Parameter
Write Cycle Time
Chip Enable to End of Write
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
7
7
0
0
7
7
7
7
0
0
3
3
12
8
8
0
0
8
8
8
8
0
0
3
3
15
12
10
0
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TAVEL
TAS
0
TAVWH TAW
TAVEH TAW
TWLWH TWP
TELEH TWP
TWHAX TWR
TEHAX TWR
TWHDX TDH
TEHDX TDH
TWLQZ TWHZ
TDVWH TDW
TDVEH TDW
TWHQX TWLZ
10
10
10
10
0
0
3
3
0
7
7
3
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
0
5
5
3
5
0
6
6
3
6
9
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
*BICMOS
AC Characteristics Write Cycle
Symbol
20ns
25ns
35ns
Parameter
Write Cycle Time
Chip Enable to End of Write
JEDEC
Alt.
Min Max
Min Max
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV TWC
TELWH TCW
TWLEH TCW
TAVWL TAS
20
15
15
0
25
20
20
0
35
30
30
0
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TAVEL
TAS
0
0
0
TAVWH TAW
TAVEH TAW
TWLWH TWP
TELEH TWP
TWHAX TWR
TEHAX TWR
TWHDX TDH
TEHDX TDH
TWLQZ TWHZ
TDVWH TDW
TDVEH TDW
TWHQX TWLZ
15
15
15
15
0
0
3
3
20
20
20
20
0
0
3
3
30
30
30
30
0
0
3
3
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
0
12
12
3
10
0
15
15
3
12
0
20
20
3
15
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
5
EDI8F32256C Rev. 12 9/98 ECO #10816
Write Cycle 1 - W Controlled
TAVAV
TELWH
A
E
TWHAX
TAVWH
TWLWH
W
TAVWL
TWHDX
TWHQX
TDVWH
D
Q
DATA VALID
TWLQZ
HIGH Z
Write Cycle 2 - E Controlled
TAVAV
A
TAVEL
TELEH
TWLEH
E
W
TEHAX
TAVEH
TDVEH
DATA VALID
TEHDX
D
Q
HIGH Z
EDI8F32256C
256Kx32 SRAM Module
6
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
Ordering Information
Part Number.
Speed
(ns)
Package
No.
Part Number
Speed
(ns)
Package
No.
BICMOS
BICMOS
EDI8F32256B10MZC
EDI8F32256B12MZC
CMOS
10
12
85
85
EDI8G32256B10MNC
EDI8G32256B12MNC
CMOS
10
12
32
32
EDI8F32256C15MZC
EDI8F32256C20MZC
EDI8F32256C25MZC
EDI8F32256C35MZC
15
20
25
35
85
85
85
85
EDI8F32256C15MNC
EDI8F32256C20MNC
EDI8F32256C25MNC
EDI8F32256C35MNC
BICMOS
15
20
25
35
32
32
32
32
EDI8G32256B10MMC
EDI8G32256B12MMC
CMOS
10
12
333
333
Part Number.
Speed
(ns)
Package
No.
CMOS
EDI8F32256C15MMC
EDI8F32256C20MMC
EDI8F32256C25MMC
EDI8F32256C35MMC
15
20
25
35
333
333
333
333
EDI8F32257C20MZC
EDI8F32257C25MZC
20
25
188
188
NOTE: 1. For Gold SIMM change form EDI8F to EDI8G.
2. The BICMOS 10 & 12ns SIMMs available with Gold Contacts only.
Package Description
Package No. 32
64 Lead Angled SIMM
3.855 MAX.
3.584
.360
MAX.
.680
MAX.
.400
.250
P1
.250
.050
1.845
.125
MIN.
.225
MIN.
3.350
1.792
R.062. (2x)
Package No. 85
64 Pin ZIP
3.665
MAX.
.360
MAX.
.050
.580
MAX.
.050
.250
TYP.
.100
TYP.
.022
.018
.050
TYP.
.165
.135
.100
TYP.
.175
.125
7
EDI8F32256C Rev. 12 9/98 ECO #10816
Package No. 333
64 Lead SIMM
3.855 MAX.
3.584
.125
MIN.
.615
MAX.
#
.400
.250
.250
3.350
.050 TYP.
.062 R.
.360
MAX.
.062 R.
1.845
1.792
Package No. 188
64 ZIP Low Profile
3.665 MAX.
.360
MAX.
.050
.470
MAX.
.050
.175
.125
.170
.130
.021
.017
.100 TYP.
.050
TYP.
.100
TYP.
Electronic Designs, Inc.
• One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 •
http://www.electronic-designs.com
ElectronicDesignsInc. reservestherighttochangespecificationswithoutnotice. CAGENo. 66301
8
EDI8F32256C Rev. 12 9/98 ECO #10816
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