EDI8L21664V15BI [WEDC]
SRAM Module, 128KX16, 15ns, CMOS, PBGA74, 15 X 15 MM, MO-151, BGA-74;
| 型号： | EDI8L21664V15BI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | SRAM Module, 128KX16, 15ns, CMOS, PBGA74, 15 X 15 MM, MO-151, BGA-74 静态存储器 内存集成电路 |
| 文件： | 总6页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8L21664V
TMS320C54x External SRAM Memory Solution
FEATURES
DESCRIPTION
n DSP Memory Solution
The EDI8L21664VxxBC is a 3.3V, 2x64Kx16 SRAM constructed
with two 64Kx16 die mounted on a multi-layer laminate substrate.
The device is packaged in a 74 lead, 15mm by 15mm, BGA.
Texas Instruments TMS320C54x
n 3.3V Operating Supply Voltage
Operating with a 3.3V power supply and with access times as fast
as 10ns, the device allows the user to develop a fast external
memory for Texas Instuments' TMS320C54x DSP.
n Access Times of 10, 12 and 15ns
n Single Write Control and Output Enable Lines
n One Chip Enable Line per Memory Bank
n 50% Space Savings vs. Monolithic TSOPs
n Upgrade Path Available in Same Footprint
n Multiple VCC and VSS Pins
The device consists of two separate banks of 64Kx16 of memory.
Each bank has a separate Chip Enable pin and higher order
address select pin. Bank 'A' is controlled using CE1\ and A15A.
Bank 'B' is controlled using CE2\ and A15B. The two banks have
common I/Os (DQ0-15) and control lines (WE\ and G\).
n Reduced Inductance and Capacitance
n 74 pin BGA, JEDEC MO-151
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
VSS VCC VCC DQ15 DQ14 VCC DQ13 DQ11 DQ9 DQ8 N/C A
VSS VCC VCC VSS VSS VCC DQ12 DQ10 DQ4 VCC VCC B
VSS VSS
VSS VSS
VSS VSS
A15A CE1\
VCC
VSS VCC C
VSS VCC D
VSS VCC E
DQ3 DQ7 F
DQ5 DQ0 G
DQ6 DQ1 H
N/C
WE\
VSS CE2\
VSS A14
VSS A12
A15B A13
VCC
VSS
VSS
DQ2 N\C
J
K
L
K
L
VCC A10
VCC A11
A8
A9
A6
A7
A4
VSS A5
A2
A0
A3
G\
A1
1
2
3
4
5
6
7
8
9
10
11
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
1
EDI8L21664V
BLOCK DIAGRAM
A0-A14
G\
WE\
CE1\
A15 A
64K x 16
SRAM
DQ0-DQ15
CE2\
A15 B
64K x 16
SRAM
PIN DESCRIPTIONS
Pin
Symbol
A0-A14
A15A
A15B
WE\
CE1\
CE2\
G\
Type
Input
Input
Input
Input
Input
Input
Input
Description
Addresses
Addresses: A15 on Bank 'A' of memory
Addresses: A15 on Bank 'B' of memory
Write Enable: This active LOW input allows a full 16-bit WRITE to occur.
Chip Enable: This active LOW input is used to enable the 'A' Bank of the device.
Chip Enable: This active LOW input is used to enable the 'B' Bank of the device.
Output Enable: This active LOW asynchronous input enables the data output drivers.
Various
Various
Various
DQ0-15
Vcc
Vss
Input/Output Data Inputs/Outputs
Supply
Ground
Core power supply: +3.3V -5%/+10%
Ground
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
2
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Voltage on Vcc Supply Relative to Vss -0.5V to 4.6V
Description
Sym
VIH
VIL
Min
2.2
-0.3
3.0
Max
Vcc+0.5
0.8
Units
VIN
-0.5V to Vcc+0.5V
-55°C to +125°C
+125°C
Input High Voltage
Input Low Voltage
Supply Voltage
V
V
V
Storage Temperature
Junction Temperature
Power Dissipation
Vcc
3.6
3 Watts
Short Circuit Output Current (per I/O)
50 mA
*Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
1.5ns
1.5V
See Figure 1
Input Rise and Fall Times (Max)
Input and Output Timing Levels
Output Load
CAPACITANCE
(f=1.0MHz, VIN=VCC or VSS)
Figure 1 - Output Load Equivalent
Parameter
Address Lines
Data Lines
Sym
CA
CD/Q
CC
Max
8
17
15
Unit
pF
pF
Output
Z0 = 50Ω
Control Lines
pF
50Ω
Vt = 1.25V
DC ELECTRICAL CHARACTERISTICS
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Power Supply
Current: Operating
Sym
ICC1
Conditions
Device Selected; all inputs £VIL or ³VIH;
cycle time ³tKC MIN;
Min
Max
380
360
260
60
Units
mA
-10ns
-12ns
-15ns
VCC=MAX; outputs open
CMOS Standby
TTL Standby
ISB2 Device deselected; VCC=MAX; all inputs £VSS +0.2
or ³ VCC -0.2; all inputs static; CLK frequency = 0
ISB3
mA
mA
Device deselected; all inputs £VIL or ³VIH;
all inputs static; VCC=MAX; CLK frequency = 0
0V£VIN£VCC
120
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
ILO
VOH
VOL
-5
--5
2.4
5
5
µA
µA
V
Output(s) disabled, 0V£VOUT£VCC
IOH = -4.0mA
IOL = 4.0mA
0.4
V
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
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EDI8L21664V
AC ELECTRICAL CHARACTERISTICS
Symbol
10ns
12ns
15ns
Read Cycle
Min Max Min Max Min
Max Units
Read Cycle Time
Address Access Time
Chip Enable Access
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable access time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Write Cycle
tAVAV
tAVQV
tELQV
tAVQX
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
10
12
15
ns
10
10
12
12
15
15
ns
ns
ns
ns
ns
ns
ns
ns
3
3
4
4
4
4
5
5
6
6
7
7
0
0
0
5
6
7
Write Cycle Time
Chip Enable to End of Write
tAVAV
tELWH
10
8
12
8
15
9
ns
ns
Address valid to End of Write,
with G\ HIGH
tAVGHWH
tAVWL
tAVWH
tWLWH
tWLGHWH
tDVWH
tWHDX
tWHQX
tWLQZ
8
0
0
10
8
6
8
0
0
10
8
6
9
0
0
11
9
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold from End of Write
Write Pulse Width
Write Pulse Width, with G\ HIGH
Data Setup Time
Data Hold Time
0
3
0
4
0
5
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
5
6
7
READ CYCLE 1 - W HIGH, G, E LOW
TAVAV
A
ADDRESS 1
ADDRESS 2
TAVQX
TAVQV
Q
DATA 2
DATA 1
READ CYCLE 2 - W HIGH
TAVAV
A
E
TAVQV
TELQV
TEHQZ
TGHQZ
TELQX
G
Q
TGLQV
TGLQX
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
WRITE CYCLE 1 - W CONTROLLED
TAVAV
TELWH
A
E
TWHAX
TWHDX
TAVWH
TWLWH
W
TAVWL
TDVWH
HIGH Z
DATA VALID
D
Q
TWHQX
TWLQZ
WRITE CYCLE 2 - E CONTROLLED
TAVAV
A
TAVEL
TELEH
E
TAVEH
TEHAX
TEHDX
TWLEH
W
TDVEH
D
Q
DATA VALID
HIGH Z
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
5
EDI8L21664V
ORDERING INFORMATION
COMMERCIAL TEMPERATURE RANGE (0°C TO +70°C)
INDUSTRIAL TEMPERATURE RANGE (-40°C TO +85°C)
Part Number
Speed
(ns)
10
12
15
Package
No.
Part Number
Speed
(ns)
15
Package
No.
EDI8L21664V10BC
EDI8L21664V12BC
EDI8L21664V15BC
EDI8L21664V15BI
PACKAGE DESCRIPTION
74 PIN BGA JEDEC MO-151
15.0 max.
3.0 max.
1.27
15.0
max.
0.50/.070
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
6
Dec. 2002 Rev. 1
ECO #15721
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