EDI9LC644AV1512BC [WEDC]
Memory IC,;
| 型号： | EDI9LC644AV1512BC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Memory IC, |
| 文件： | 总26页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI9LC644V
EDI9LC644AV
128Kx32 SSRAM/1Mx32 SDRAM
External Memory Solution for Texas Instruments TMS320C6000 DSP
FEATURES
DESCRIPTION
■ Clock speeds:
The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline
SRAM and a 1Mx32 Synchronous DRAM array constructed with
one 128K x 32 SBSRAM and two 1Mx16 SDRAM die mounted on
a multilayer laminate substrate. The device is packaged in a 153
lead, 14mm by 22mm, BGA.
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
■ DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
■ Packaging:
The EDI9LC644VxxBC provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150, and 133 MHz, allowing the user to develop a fast
external memory for the SSRAM interface port .
• 153 pin BGA, JEDEC MO-163
■ 3.3V Operating supply voltage
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the
SDRAM interface port .
■ Direct control interface to both the SSRAM and SDRAM ports
on the “C6x”
■ Common address and databus
■ 65% space savings vs. monolithic solution
■ Reduced system inductance and capacitance
FIG. 1 PIN CONFIGURATION
BOTTOM VIEW
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
A0-16
Address Bus
Data Bus
A
B
C
D
E
F
DQ19
DQ18
VCCQ
DQ17
DQ16
VCCQ
NC
DQ23
DQ22
VCCQ
DQ21
DQ20
VCCQ
NC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
NC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
A2
DQ24
DQ25
VCCQ
DQ26
DQ27
VCCQ
A4
DQ28
DQ29
VCCQ
DQ30
DQ31
VCCQ
A5
A
B
C
D
E
F
DQ0-31
SSCLK
SDCE
SSRAM Clock
SDWE SDA10
SSADC SSRAM Address Status Control
VSS
VSS
VSS
VSS
SSWE
SSOE
SSRAM Write Enable
SSRAM Output Enable
SDRAM Clock
SDCLK VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
VSS
SDCLK
SDRAS
G
H
J
NC SDRAS SDCAS
G
H
J
SDRAM Row Address Strobe
NC
NC
A8
A9
VSS
VSS
VSS
VSS
VSS
A1
A3
A10
SDCAS SDRAM Column Address Strobe
SDWE SDRAM Write Enable
SDA10 SDRAM Address 10/auto precharge
A6
A7
A0
A11
A12
K NC / A17 NC / A18 NC / A19 VSS
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
7
A13
A14
K
L
M
N
P
L
NC
VCCQ
DQ12
DQ13
VCCQ
DQ14
DQ15
1
NC
VCCQ
DQ11
DQ10
VCCQ
DQ9
DQ8
2
NC
VCC
VCC
VCC
VCC
VCC
VCC
3
BWE2 BWE3
BWE0 BWE1
A15
A16
BWE0-3
SSRAM Byte Write Enables
SDRAM SDQM 0 - 3
M
N
P
VCCQ
DQ4
DQ5
VCCQ
DQ6
DQ7
8
VCCQ
DQ0
DQ1
VCCQ
DQ2
DQ3
9
VSS
VSS
VSS
VSS
SSCE
SDCE
VCC
Chip Enable SSRAM Device
Chip Enable SDRAM Device
Power Supply pins, 3.3V
SSCLK VSS
R
T
VSS
VSS
NC
NC
6
R
T
U
SSADC SSWE
SSOE SSCE
VCCQ
Data Bus Power Supply pins,
3.3V (2.5V future)
U
4
5
VSS
NC
Ground
No Connect
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
October 1999 Rev. 3
EDI9LC644V
EDI9LC644AV
FIG. 2 BLOCK DIAGRAM
A0-16
A
A
0
1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
DQ0-7
5
DQ1-8
DQ9-16
DQ17-24
DQ25-32
6
DQ8-15
7
8
DQ16-23
9
10
11
12
13
14
15
16
DQ24-31
BWE
SSWE
BW1
BW2
BW3
BW4
BWE
BWE
BWE
BWE
0
1
2
3
CE
OE
2
SSCE
SSOE
ADSC
CLK
SSADC
SSCLK
DQ0-31
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
DQ0-7
DQ0-7
DQ8-15
A11
BA
DQ8-15
SDA10
A10/AP
LDQM
UDQM
CS
RAS
CAS
WE
SDCE
SDRAS
SDCAS
SDWE
CLK
SDCLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
BA
DQ16-23
DQ24-31
DQ0-7
A11
DQ8-15
A10/AP
LDQM
UDQM
CS
RAS
CAS
WE
CLK
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
EDI9LC644V
EDI9LC644AV
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol
Type
Signal
Polarity
Function
SSCLK
Input
Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS
SSOE
SSWE
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
to be executed by the SSRAM.
Input
Pulse
Active Low
SSCE
SDCLK
SDCE
Input
Input
Input
Pulse
Pulse
Pulse
Active Low SSCE disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
SDRAS
SDCAS
SDWE
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation
to be executed by the SDRAM.
Input
Input
Pulse
Level
Active Low
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled at the
rising clock edge.
A0-16,
SDA10
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the
—
rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the
end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A11 defines the bank
to be precharged (low = bank A, high = bank B). If SDA10 is low, autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s) to
precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of A11. If
SDA10 is low, then A11 is used to define which bank to precharge.
Input
Output
DQ0-31
Level
Pulse
—
Data Input/Output are multiplexed on the same pins.
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0
is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
BWE0-3
Input
Vcc, Vss
VCCQ
Supply
Supply
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(0°C ≤ TA ≤ 70°C; VCC = 3.3V -5% / +10% unless otherwise noted)
Voltage on Vcc Relative to Vss
Vin (DQx)
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
+175°C
Parameter
Symbol
VCC
Min
3.135
2.0
Max
3.6
Units
V
Storage Temperature (BGA)
Junction Temperature
Short Circuit Output Current
Supply Voltage (1)
Input High Voltage (1,2)
Input Low Voltage (1,2)
VIH
VCC +0.3
0.8
V
VIL
-0.3
-10
V
100 mA
Input Leakage Current
ILI
10
µA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
0 ≤ VIN ≤ Vcc
Output Leakage (Output Disabled)
ILo
-10
10
µA
0 ≤ VIN ≤ Vcc
Output High (IOH = -4mA) (1)
Output Low (IOL = 8mA) (1)
VOH
VOL
2.4
—
—
V
V
0.4
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tKC/2
Underershoot: VIL ≥ -2.0V for t ≤ tKC/2
DC ELECTRICAL CHARACTERISTICS
Description
Conditions
Symbol
Frequency
133MHz
150MHz
166MHz
200MHz
133MHz
150MHz
166MHz
200MHz
83MHz
Typ
400
450
500
TBD
300
350
400
TBD
220
235
255
Max
Units
550
580
625
TBD
450
480
525
TBD
240
250
280
Power Supply Current:
Operating (1,2,3)
SSRAM Active / DRAM Auto Refresh
Icc1
mA
mA
Power Supply Current
Operating (1,2,3)
SSRAM Active / DRAM Idle
SDRAM Active / SSRAM Idle
Icc2
Power Supply Current
Operating (1,2,3)
Icc3
ISB1
100MHz
125MHz
mA
mA
SSCE and SDCE ≤ Vcc -0.2V,
All other inputs at Vss +0.2 ≤ VIN or
VIN ≤ VCC -0.2V, Clk frequency = 0
20.0
40.0
CMOS Standby
TTL Standby
SSCE and SDCE ≤ VIH min
All other inputs at VIL max ≤ VIN or
VIN ≤ VCC -0.2V, Clk frequency = 0
ISB2
Icc5
30.0
190
55.0
250
mA
mA
Auto Refresh
NOTES:
1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE ≥ VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
BGA CAPACITANCE
Description
Conditions
Symbol
CI
Typ
5
Max
Units
Address Input Capacitance (1)
Input/Output Capacitance (DQ) (1)
Control Input Capacitance (1)
Clock Input Capacitance (1)
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
8
10
8
pF
pF
pF
pF
CO
8
CA
5
CCK
4
6
NOTE:
1. This parameter is sampled.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
EDI9LC644V
EDI9LC644AV
SSRAM AC CHARACTERISTICS (EDI9LC644V)
Symbol
200MHz
Max
166MHz
Max
150MHz
Max
133MHz
Max
Parameter
Clock Cycle Time
Min
5
Min
6
Min
7
Min
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX
tKQLZ
tKQHZ
tOELQV
tOELZ
tOEHZ
tS
Clock HIGH Time
1.6
1.6
2.4
2.4
2.6
2.6
2.8
2.8
Clock LOW Time
Clock to output valid
2.5
3.5
3.8
4.0
Clock to output invalid
1.5
0
1.5
0
1.5
0
1.5
0
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
1.5
3
1.5
3.5
3.5
1.5
3.8
3.8
1.5
4.0
4.0
2.5
0
0
0
0
3.0
3.5
3.5
3.8
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
tH
SSRAM AC CHARACTERISTICS (EDI9LC644AV)
Symbol
200MHz
Max
166MHz
Max
150MHz
133MHz
Parameter
Clock Cycle Time
Min
5
Min
6
Min
Max
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX
tKQLZ
tKQHZ
tOELQV
tOELZ
tOEHZ
tS
7
8
Clock HIGH Time
1.6
1.6
2.4
2.4
2.6
2.6
2.8
2.8
Clock LOW Time
Clock to output valid
2.5
3.5
3.8
4.0
Clock to output invalid
1.5
0
1.5
0
1.5
0
1.5
0
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
1.5
3
1.5
3.5
3.5
1.5
3.8
3.8
1.5
4.0
4.0
2.5
0
0
0
0
3.0
3.5
3.5
3.8
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
tH
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
SSRAM OPERATION TRUTH TABLE
Operation
Address Used
None
SSCE
H
SSADS
SSWE
X
SSOE
X
DQ
High-Z
D
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
NOTE:
L
L
External
External
External
Current
Current
Current
Current
Current
Current
L
L
X
L
L
H
L
Q
L
L
H
H
High-Z
Q
X
H
H
H
H
H
H
H
L
X
H
H
High-Z
Q
H
H
L
H
H
H
High-Z
D
X
L
X
H
L
X
D
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH
though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM PARTIAL TRUTH TABLE
Function
SSWE BWE0 BWE1 BWE2 BWE3
READ
H
L
L
X
L
L
X
H
L
X
H
L
X
H
L
WRITE one Byte (DQ0-7)
WRITE all Bytes
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
6
EDI9LC644V
EDI9LC644AV
FIG. 3 SSRAM READ TIMING
tKHKL
tKHKH
tKLKH
SSCLK
tH
tS
SSADS
tS
SSCE
ADDR
tH
tS
A1
A5
A2
A3
A4
tH
SSOE
SSWE
tOEHQZ
tOELQV
tKHQX
Q(A1)
tKHQV
tKQLZ
Q(A2)
Q(A3)
Q(A4)
Q(A5)
DQ
FIG. 4 SSRAM WRITE TIMING
tKHKL
tKHKH
tKLKH
SSCLK
tH
tS
SSADS
SSCE
tH
tH
tS
A4
A1
A2
A3
A5
ADDR
SSOE
SSWE
tH
KHGWX
tS
tH
tH
tS
D(A2)
D(A3)
D(A5)
D(A1)
D(A4)
DQ
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
SDRAM AC CHARACTERISTICS
Symbol
125MHz
100MHz
83MHz
Parameter
Min
8
Max
1000
1000
6
Min
10
Max
1000
1000
7
Min
12
Max
1000
1000
8
Units
CL = 3
CL = 2
tCC
tCC
Clock Cycle Time (1)
ns
10
12
15
Clock to valid Output delay (1,2)
Output Data Hold Time (2)
Clock HIGH Pulse Width (3)
Clock LOW Pulse Width (3)
Input Setup Time (3)
tSAC
tOH
ns
ns
3
3
3
2
1
2
3
3
3
2
1
2
3
3
3
2
1
2
tCH
ns
tCL
ns
tSS
ns
Input Hold Time (3)
tSH
ns
CLK to Output Low-Z (2)
CLK to Output High-Z
tSLZ
tSHZ
tRRD
tRCD
tRP
ns
7
7
8
ns
Row Active to Row Active Delay (4)
RAS\ to CAS\ Delay (4)
20
20
20
50
70
70
1
20
20
20
50
80
80
1
24
24
24
60
90
90
1
ns
ns
Row Precharge Time (4)
Row Active Time (4)
ns
tRAS
tRC
10,000
10,000
10,000
ns
Row Cycle Time - Operation (4)
Row Cycle Time - Auto Refresh (4,8)
ns
tRFC
tCDL
tRDL
tBDL
tCCD
ns
Last Data in to New Column Address Delay (5)
Last Data in to Row Precharge (5)
CLK
CLK
CLK
CLK
1
1
1
Last Data in to Burst Stop (5)
1
1
1
Column Address to Column Address Delay (6)
Number of Valid Output Data (7)
1.5
2
1.5
2
1.5
2
ea
1
2
1
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
EDI9LC644V
EDI9LC644AV
CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM
(Unit = number of clock)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
Latency
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
3
3
2
9
7
6
6
5
4
3
2
2
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHz SDRAM
(Unit = number of clock)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
Latency
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
100MHz (12.0ns)
83MHz (12.0ns)
3
2
7
6
5
5
2
2
2
2
2
2
1
1
1
1
1
1
REFRESH CYCLE PARAMETERS
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
ms
Refresh Period (1,2)
tREF
—
64
—
64
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
SDRAM COMMAND TRUTH TABLE
SDCE
SDRAS
SDCAS
SDWE
BWE
A11
SDA10
A9-0
Notes
Function
Mode Register Set
Auto Refresh (CBR)
L
L
L
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
H
L
L
H
L
L
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
X
BA
X
X
Single Bank
Precharge all Banks
L
H
H
H
L
L
2
Precharge
L
H
Bank Activate
Write
L
BA
BA
BA
BA
BA
X
Row Address
2
2
2
2
2
3
H
H
H
H
H
H
X
X
X
L
H
L
Write with Auto Precharge
Read
L
L
Read with Auto Precharge
Burst Termination
No Operation
L
H
X
X
X
X
X
H
H
X
X
X
X
Device Deselect
X
Data Write/Output Disable
Data Mask/Output Disable
NOTES:
X
4
4
H
X
1. All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE0-3 at the positive rising edge of the clock.
2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
9
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
SDRAM CURRENT STATE TRUTH TABLE
Command
A11
Current State
Action
Notes
SDCE SDRAS SDCAS SDWE
SDA10-A0
OP Code
Description
(BA)
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Mode Register Set
Auto or Self Refresh
Precharge
Set the Mode Register
Start Auto
1
1
X
X
X
L
H
H
L
X
No Operation
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Activate the specified bank and row
ILLEGAL
Idle
H
H
H
H
X
L
Column
2
1
1
L
H
L
Column
ILLEGAL
H
H
X
L
X
X
X
No Operation
H
X
L
X
No Operation
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Precharge
3
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
1
Row Active
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
4,5
4,5
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Read
H
H
H
H
X
L
Column
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Write
H
H
H
H
X
L
Column
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Read with
Auto Precharge
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
ILLEGAL
H
X
X
Continue the Burst
Continue the Burst
X
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
10
EDI9LC644V
EDI9LC644AV
SDRAM CURRENT STATE TRUTH TABLE (cont.)
Command
A11
Current State
Action
Notes
SDCE SDRAS SDCAS SDWE
SDA10-A0
OP Code
Description
(BA)
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Write with
Auto Precharge
H
H
H
H
X
L
Column
ILLEGAL
ILLEGAL
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
H
X
L
X
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
No Operation; Bank(s) idle after tRP
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
2
2
Precharging
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
ILLEGAL
20
H
H
X
L
X
X
X
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
ILLEGAL
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Row Activating
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
No Operation; Row active after tRCD
No Operation; Row active after tRCD
No Operation; Row active after tRCD
ILLEGAL
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
6
6
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Write Recovering
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row active after tDPL
No Operation; Row active after tDPL
No Operation; Row active after tDPL
ILLEGAL
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
2
Write Recovering
with Auto
H
H
H
H
X
Column
ILLEGAL
2,6
2,6
Precharge
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
H
X
X
X
11
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
SDRAM CURRENT STATE TRUTH TABLE (cont.)
Command
A11
Current State
Action
Notes
SDCE SDRAS SDCAS
SDWE
SDA10-A0
OP Code
Description
(BA)
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
X
X
X
ILLEGAL
ILLEGAL
L
H
H
L
X
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Refreshing
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Mode Register
Accessing
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
ILLEGAL
H
X
X
No Operation; Idle after two clock cycles
X
Device Deselect No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current
State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS to CAS Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
12
EDI9LC644V
EDI9LC644AV
FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3,
BURST LENGTH = 1
0
1
2
t
3
4
5
6
t
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
t
CH
t
CL
CC
t
RCD
RAS
SDCE
t
SS
tSH
t
RCD
tRP
t
SS
tSH
SDRAS
t
CCD
t
SS
tSH
SDCAS
ADDR
t
SS
t
SH
t
SS
tSH
Ra
Ca
Cb
Cc
Rb
Note 2, 3
BS
Note 2, 3
BS
Note 2, 3 Note 4
BS BS
Note 2
BS
A
11 (BA)
SDA10
DQ
BS
Ra
Note 3
RAC
Note 3
Db
Note 3 Note 4
Rb
t
t
SS
SS
SS
tSH
t
SAC
Qa
Qc
t
SLZ
t
OH
t
t
t
SH
SH
SDWE
t
BWE
Row Active
Read
Write
Read
Precharge
Row Active
DON'T CARE
13
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 6 SDRAM POWER UP SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
t
RP
t
RFC
t
RFC
ADDR
Key
RAa
A
11 (BA)
SDA10
DQ
RAa
HIGH-Z
SDWE
BWE
High level is necessary
Precharge
(All Banks)
Auto Refresh
Mode Register Set
Auto Refresh
Row Active
(A-Bank)
DON'T CARE
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
14
EDI9LC644V
EDI9LC644AV
FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
Note 1
t
RC
t
RCD
SDRAS
SDCAS
ADDR
Ra
Ca0
Rb
Cb0
A11 (BA)
SDA10
CL = 2
Ra
Rb
t
SHZ
Note 4
t
RAC
Note 3
t
RDL
t
OH
t
SAC
Qa0
Qa1
Qa2
Qa3
Qa2
Db0
Db0
Db1
Db2
Db3
t
SHZ Note 4
DQ
t
RAC
t
RDL
t
OH
Note 3
t
SAC
CL = 3
Qa0
Qa1
Qa3
Db1
Db2
Db3
SDWE
BWE
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ)
after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
15
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
t
RCD
SDRAS
Note 2
SDCAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
A
11 (BA)
SDA10
CL = 2
Ra
t
RDL
Qa0
Qa1
Qb0
Qa1
Qb1
Qb2
Dc0
Dc0
Dc1
Dd0
Dd1
DQ
t
CDL
CL = 3
Qa0
Qb0
Qb1
Dc1
Dd0
Dd1
SDWE
BWE
Note 1
Note 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
16
EDI9LC644V
EDI9LC644AV
FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
Note 1
SDRAS
Note 2
SDCAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A
11 (BA)
SDA10
CL = 2
RAa
RBb
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
DQ
CL = 3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
SDWE
BWE
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
DON'T CARE
NOTES:
1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
17
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
Note 2
SDCAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
A
11 (BA)
SDA10
DQ
RAa
RBb
t
CDL
tRDL
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
SDWE
BWE
Note 1
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
DON'T CARE
NOTES:
1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
18
EDI9LC644V
EDI9LC644AV
FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
RBb
CBb
CAa
RAc
CAc
A
11 (BA)
SDA10
CL = 2
RAa
RBb
RAc
t
CDL
Note 1
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
DQ
CL = 3
QAa0 QAa1 QAa2 QAa3
SDWE
BWE
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
DON'T CARE
NOTES:
1. tCDL should be met to complete write.
19
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
Ra
Rb
Ca
Cb
A
11 (BA)
SDA10
Ra
Rb
CL = 2
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa1
Qa2
Qa3
Db1
Db2
Db3
SDWE
BWE
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
DON'T CARE
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
20
EDI9LC644V
EDI9LC644AV
FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @
BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa
CAb
A
11 (BA)
SDA10
CL = 2
RAa
Note 2
1
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1 QAa2 QAa3 QAa4
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL = 3
SDWE
BWE
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
21
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @
BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa
CAb
A
11 (BA)
SDA10
DQ
RAa
t
BDL
t
RDL
Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
SDWE
BWE
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL.
BWE at write interrupt by precharge command is needed to prevent invalid write.
BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
3. Burst stop is valid at every burst length.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
22
EDI9LC644V
EDI9LC644AV
FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
Note 2
RAa
CAa
RBb
CAb
RAc
CAd
CBc
A
11 (BA)
SDA10
CL = 2
RAa
RBb
RAc
DAa0
DAa0
QAb0 QAb1
DBc0
DBc0
QAd0 QAd1
DQ
CL = 3
QAb0 QAb1
QAd0 QAd1
SDWE
BWE
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(Both Banks)
Write
Read with
Write with
Auto Precharge
(B-Bank)
(A-Bank) Auto Precharge
(A-Bank)
DON'T CARE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle,
so in the case of BRSW write command, the next cycle starts the precharge.
23
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 16
SDRAM MODE REGISTER SET CYCLE
SDRAM AUTO REFRESH CYCLE
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
SDCLK
HIGH
SDCE
Note 2
t
RFC
SDRAS
Note 1
Note 3
SDCAS
ADDR
Key
Ra
DQ
HI-Z
HI-Z
SDWE
BWE
MRS
New
Command
Auto Refresh
New Command
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS activation.
7. Please refer to Mode Register Set table.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
24
EDI9LC644V
EDI9LC644AV
PACKAGE DESCRIPTION: 153 LEAD BGA (17 x 9 BALL ARRAY)
JEDEC MO-163
3.50 (0.138)
MAX
14.00 (0.551)
BSC
A
B
PIN 1 INDEX
C
D
E
F
G
H
J
22.00 (0.866)
BSC
K
L
M
N
P
R
T
U
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number
SSRAM Access SDRAM Access
Part Number
SSRAM Access SDRAM Access
EDI9LC644V2012BC
200MHz
200MHz
166MHz
166MHz
150MHz
150MHz
133MHz
133MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
EDI9LC644AV2012BC
200MHz
200MHz
166MHz
166MHz
150MHz
150MHz
133MHz
133MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
EDI9LC644V2010BC
EDI9LC644V1612BC
EDI9LC644V1610BC
EDI9LC644V1512BC
EDI9LC644V1510BC
EDI9LC644V1312BC
EDI9LC644V1310BC
EDI9LC644AV2010BC
EDI9LC644AV1612BC
EDI9LC644AV1610BC
EDI9LC644AV1512BC
EDI9LC644AV1510BC
EDI9LC644AV1312BC
EDI9LC644AV1310BC
25
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 17
INTERFACING THE TEXAS INSTRUMENTS TMS320C6x
WITH THE ED9LC644V (128Kx32 SSRAM/1Mx32 SDRAM)
Address Bus
EA2-21
EDI9LC644V
128K x 32 SSRAM
1M x 32 SDRAM
EA
EA
2
3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0-7
DQ8-15
Texas Instruments
TMS320C6x
DSP
DQ16-23
DQ24-31
SSWE\
SSCE\
SSOE\
SSADC\
SSCLK
SSWE\
CE
SSOE\
SSADS\
SSCLK
2\
SSRAM
Control
BWE
BWE
BWE
BWE
0\
1\
2\
3
\
BE
BE
BE
BE
0\
1\
2\
3
\
Shared
Controls
SDA10
SDA10
CE
SDRAS\
SDCAS\
SDWE\
SDCLK
SDCE\
SDRAS\
0\
SDRAM
SDCAS\ Control
SDWE\
SDCLK
Data Bus
ED0-31
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
26
相关型号：
©2020 ICPDF网 联系我们和版权申明