W3E64M72S-333SBI [WEDC]
DDR DRAM, 64MX72, 0.7ns, CMOS, PBGA219, 25 X 32 MM, PLASTIC, BGA-219;
| 型号： | W3E64M72S-333SBI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM, 64MX72, 0.7ns, CMOS, PBGA219, 25 X 32 MM, PLASTIC, BGA-219 存储 内存集成电路 动态存储器 双倍数据速率 |
| 文件： | 总19页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3E64M72S-XBX
White Electronic Designs
ADVANCED*
64Mx72 DDR SDRAM
BENEFITS
FEATURES
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66% Space Savings vs. TSOP
Reduced part count
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Data rate = 200, 250, 266 and 333Mbs
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Package:
55% I/O reduction vs TSOP
• 219 Plastic Ball Grid Array (PBGA), 25 x 32mm
2.5V 0.2V core power supply
Reduced trace lengths for lower parasitic
capacitance
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2.5V I/O (SSTL_2 compatible)
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Suitable for hi-reliability applications
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Laminate interposer for optimum TCE match
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
GENERAL DESCRIPTION
The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
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Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
The 512MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. Asingle read or write
access for the 512MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
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DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
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DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
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Programmable IOL/IOH option
Auto precharge option
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
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Organized as 64M x 72
Weight: W3E64M72S-XBX - 4.5 grams typical
The 512MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
* This product is under development, is not qualified or characterized and is subject
to change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3E64M72S-XBX
White Electronic Designs
ADVANCED
DENSITY COMPARISONS
ACTUAL SIZE
25
White Electronic Designs
W3E64M72S-XBX
32
Area = 800mm2
I/O Count = 219 Balls
SAVINGS – Area: 66% – I/O Count: 55%
Discrete Approach
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
22.3
Area: 9 x 265mm2 = 2,385mm2
I/O Count: 9 x 54 pins = 486 pins
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with theACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register definition,
command descriptions and device operation.
An auto refresh mode is provided, along with a power-
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
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W3E64M72S-XBX
White Electronic Designs
ADVANCED
FIGURE 1 – PIN CONFIGURATION
Top View
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DQ0
DQ14
DQ12
DQ10
DQ8
VCC
DQ15
DQ13
DQ11
DQ9
VSS
VSS
A9
A10
A11
A8
VCCQ
VCC
VSS
VCCQ
DQ16
DQ18
DQ20
DQ22
DQML1
WE1#
CS1#
VSS
DQ17
DQ19
DQ21
DQ23
VSS
DQ31
DQ29
DQ27
DQ26
NC
VSS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
VCC
A
B
C
D
E
F
DQ1
DQ3
DQ2
VSS
VSS
A0
A7
A6
A1
VCC
DQ4
VCC
VCC
A2
A5
A4
A3
VSS
DQ6
DQ5
VCCQ
VCCQ
A12
DNU
BA0
DNU
BA1
DNU
VSS
VSS
DQ7
DQML0
WE0#
RAS0#
VSS
DQMH0 DQSH3 DQSL0 DQSH0
DQSL1 DQSH1
VREF
CAS0#
CS0#
VSS
VCC
CLK0
CKE0
VCCQ
VCCQ
CS3#
DQSL3
CLK0#
VSS
RAS1#
CAS1#
VCC
VSS
DQMH1
CLK1#
VCCQ
VCC
VSS
G
H
J
VCC
Vss
VSS
VSS
VCC
VSS
VCC
VSS
VSS
VCCQ
VCC
CLK3#
NC
CKE3
CLK3
DQMH3
DQ58
DQ59
DQ61
DQ63
VCC
DQSL4
CLK2#
DQSL2
CS4#
CKE2
CLK2
DQMH2
DQ41
DQ43
DQ45
DQ47
VSS
RAS2#
WE2#
DQML2
DQ37
DQ36
DQ34
DQ32
CS2#
CAS2#
DQ39
DQ38
DQ35
DQ33
VCC
K
L
VCC
CAS3# RAS3#
VSS
DQ56
DQ57
DQ60
DQ62
VSS
VCC
WE3#
DQ54
DQ52
DQ50
DQ48
DQML3
NC
CKE4
CLK4#
VSS
NC
NC
NC
NC
NC
CLK4
NC
CAS4#
DQ71
DQ69
DQ67
DQ65
WE4#
DQ70
DQ68
DQ66
DQ64
RAS4#
VSS
M
N
P
R
T
DQ55
DQ53
DQ51
DQ49
DQML4 DQSH2
DQ40
DQ42
DQ44
DQ46
VSS
NC
VCC
VSS
VSS
VCC
VSS
VSS
VCC
VCC
NC
VCCQ
VCCQ
NC
NOTE: DNU = Do Not Use.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3E64M72S-XBX
White Electronic Designs
ADVANCED
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE0
RAS0
CAS0
#
#
#
WE# RAS# CAS#
0-12
WE# RAS# CAS#
A
0-12
A
A0-12
DQ
DQ
0
DQ8
DQ
0
0
0
0
0
DQ
0
0
0
0
BA0-1
BA0-1
CK
CK#
CKE
CS#
DQML
DQS
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
CK0
CK0
CKE
CK0
CK0
CKE
IC0
IC5
#
0
#
0
CS
0
#
CS
0
#
DQML
DQSL
0
DQMH
DQSH
0
7
DQ15
DQ
7
DQ7
0
0
WE
RAS
CAS
1
#
#
#
1
1
WE# RAS# CAS#
0-12
WE# RAS# CAS#
A0-12
A
DQ
DQ16
DQ23
DQ
DQ24
DQ31
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
CK1
CK1
CKE
CK1
CK1
CKE
IC1
IC6
#
#
1
1
CS
1
#
CS
1
#
DQML
DQSL
1
DQMH
DQSH
1
DQ
7
DQ7
1
1
WE
RAS
CAS
2
2
2
#
#
#
WE# RAS# CAS#
0-12
WE# RAS# CAS#
A0-12
A
DQ
DQ32
DQ39
DQ
DQ40
DQ47
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
CK2
CK2
CKE
CK2
CK2
CKE
IC2
IC7
#
#
2
2
CS
2
#
CS
2
#
DQML
DQSL
2
DQMH
DQSH
2
DQ
7
DQ7
2
2
WE
RAS
CAS
3
3
3
#
#
#
WE# RAS# CAS#
0-12
WE# RAS# CAS#
A0-12
A
DQ
DQ48
DQ55
DQ
DQ56
DQ63
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
CK3
CK3
CKE
CK3
CK3
CKE
IC3
IC8
#
#
3
3
CS
3
#
CS
3
#
DQML
DQSL
3
DQMH
DQSH
3
DQ
7
DQ7
3
3
WE
RAS
CAS
4
4
4
#
#
#
WE# RAS# CAS#
0-12
A
DQ
DQ64
DQ71
BA0-1
CK
CK#
CKE
CS#
DQM
DQS
CK4
CK4
CKE
IC4
#
4
CS
4
#
DQML
DQSL
4
DQ
7
4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3E64M72S-XBX
White Electronic Designs
ADVANCED
INITIALIZATION
REGISTER DEFINITION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after VCC is
applied. After CKE passes through VIH, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.)Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; byA2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
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June 2005
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ADVANCED
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLLshould always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2,
2.5, or 3 clocks.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz)
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
SPEED
-200
-250
-266
-333*
CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3
≤ 75
≤ 100
≤ 100
≤ 100
≤ 100
≤ 125
≤ 133
—
—
—
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
≤ 133/≤ 166
≤ 166
* For 333Mbs operation of Industrial and commercial temperatures CL = 2.5, at Military
temperature CL = 3.
OPERATING MODE
OUTPUT DRIVE STRENGTH
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bitsA0-A6 set to the desired values. ADLL reset
is initiated by issuing a MODE REGISTER SET command
with bitsA7 andA9-A12 each set to zero, bitA8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
The normal full drive strength for all outputs are specified
to be SSTL2, Class II.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLLis enabled automatically.)Any time the DLLis enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
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ADVANCED
COMMANDS
WRITE
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-9, 11 selects the starting column location. The
value on input A10 determines whether or not AUTO
PRECHARGE is used. IfAUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Input
data appearing on the DQ is written to the memory array
subject to the DQM input logic level appearing coincident
with the data. If a given DQM signal is registered LOW,
the corresponding data will be written to memory; if the
DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed
to that byte/column location.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM.
The SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
PRECHARGE
LOAD MODE REGISTER
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputsA0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-9, 11
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
ifAUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by usingA10 to enableAUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
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ADVANCED
FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
BA
1
BA
0
A
12
A
11
Address Bus
Burst
Starting Column
Address
Length
Type = Sequential Type = Interleaved
Mode Register (Mx)
14
0*
13
0*
12 11 10
9
8
7
6
5
4
3
2
1
0
A0
0
1
Operating Mode
CAS Latency BT
Burst Length
2
4
0-1
1-0
0-1
1-0
*
M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
Reserved
2
A1
0
A0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
4
0
1
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
1
1
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Burst Type
M3
0
1
Sequential
Interleaved
CAS Latency
M6 M5 M4
8
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Reserved
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0
selects the starting column within the block.
M11
0
M10
0
M9
0
M8
0
M7
0
M6-M0
Valid
Operating Mode
M12
0
Normal Operation
2. For a burst length of four, A2-Ai select four-data-element block; A0-1
select the starting column within the block.
0
0
0
1
0
0
Valid
Normal Operation/Reset DLL
-
-
-
All other states reserved
-
-
-
-
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
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ADVANCED
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
FIGURE 4 – CAS LATENCY
T0
T1
T2
T2n
T3
T3n
CLK#
CLK
A
10
A9
A8
A7
A6
A
5
A4
A3
A
2
A
1
A0
BA1
BA0
A12
A
11
Address Bus
COMMAND
READ
NOP
NOP
NOP
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
1
1
CL = 2
0
1
DS DLL
Operating Mode
DQS
DQ
E0
0
DLL
Enable
Disable
T0
T1
T2
T2n
T3
T3n
1
CLK#
CLK
E1
0
Drive Strength
Normal
COMMAND
READ
NOP
NOP
NOP
1
Reserved
CL = 2.5
DQS
DQ
E2
0
E1, E0
Valid
-
Operating Mode
Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
-
Reserved
DATA
DON'T CARE
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
TRANSITIONING DATA
during anAUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125µs (maximum).
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH and
is automatically enabled upon exiting SELF REFRESH (A
DLL reset and 200 clock cycles must then occur before a
READ command can be issued). Input signals except CKE
are “Don’t Care” during SELF REFRESH. VREF voltage is
also required for the full duration of SELF REFRESH.
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR
,
because time is required for the completion of any internal
refresh in progress.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
theAUTO REFRESH period. TheAUTO REFRESH period
begins when theAUTO REFRESH command is registered
and ends tRFC later.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
SELF REFRESH*
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
* Self refresh available in commercial and industrial temperatures only.
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TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
DESELECT (NOP) (9)
NO OPERATION (NOP) (9)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
CS#
H
L
L
L
L
L
L
L
RAS#
CAS#
WE#
X
H
H
H
L
L
L
H
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
X
H
L
H
H
H
L
X
H
H
L
L
H
H
L
L
L
L
L
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
DM
L
H
DQs
Valid
X
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-9, 11 provide column address; A10 HIGH enables the auto precharge feature
(non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1
provide bank address.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
V
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Operating Temperature TA (Com)
Storage Temperature, Plastic
-1 to 3.6
-0.5V to VCCQ +0.5V
-55 to +125
-40 to +85
V
°C
°C
°C
°C
°C
-0 to +70
-55 to +125
125
Maximum Junction Temperature
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter
Symbol
CI1
Max
TBD
TBD
TBD
TBD
Unit
pF
Input Capacitance: CK/CK#
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
CA
pF
CI2
pF
CIO
pF
BGA THERMAL RESISTANCE
Description
Junction to Ambient (No Airflow)
Junction to Ball
Symbol
Theta JA
Theta JB
Theta JC
Max
TBD
TBD
TBD
Units
°C/W
°C/W
°C/W
Notes
1
1
1
Junction to Case (Top)
Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.wedc.com in the application notes section for modeling conditions.
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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage (36, 41)
I/O Supply Voltage (36, 41, 44)
Input Leakage Current: Any one input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ
Output Levels: Full drive option (37, 39)
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT
Symbol
VCC
VCCQ
II
II
IOZ
Min
2.3
2.3
-2
-18
-5
Max
2.7
2.7
2
18
5
Units
V
V
µA
µA
µA
IOH
-12
-
mA
)
IOL
VREF
VTT
12
-
mA
V
V
)
I/O Reference Voltage (6,44)
I/O Termination Voltage (7, 44)
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Symbol
VIH
VIL
Min
VREF +0.500
—
Max
—
VREF -0.500
Units
V
V
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ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46)
VCC, VCCQ = +2.5V 0.2V; -55°C ≤ TA ≤ +125°C
MAX
Symbol 333Mbs 250Mbs/ 200Mbs Units
266Mbs
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22,
47)
ICC0
1,035
mA
1,170
1,170
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 47)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK
(MIN); CKE = LOW; (23, 32, 49)
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW (23, 32, 49)
ICC1
ICC2P
ICC2F
ICC3P
ICC3N
1,305
45
mA
mA
mA
mA
mA
1,440
45
1,440
45
360
270
405
405
315
450
405
315
450
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 47)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle (22)
ICC4R
ICC4W
1,305
1,215
mA
mA
1,485
1,755
1,485
1,440
AUTO REFRESH CURRENT
tREFC = tRC (MIN) (49)
tREFC = 7.8125µs (27, 49)
Standard (11)
ICC5
ICC5A
ICC6
2,520
90
mA
mA
mA
mA
2,610
90
2,610
90
SELF REFRESH CURRENT: CKE 0.2V
45
45
45
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK
tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 48)
=
ICC7
3,510
3,645
3,645
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ADVANCED
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
Notes 1-5, 14-17, 33
333 Mbs CL3/CL2.5
(53)
266 Mbs CL2.5
266 Mbs CL2.5
200 CL2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Parameter
Symbol
tAC
tCH
tCL
tCK (3)
Min
-0.70
0.45
0.45
6
Max
+0.70
0.55
0.55
13
Min
-0.75
0.45
0.45
Max
+0.75
0.55
Min
-0.8
0.45
0.45
Max
+0.8
0.55
0.55
Min
-0.8
0.45
0.45
Max
+0.8
0.55
0.55
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
Access window of DQs from CK/CK#
CK high-level width (30)
CK low-level width (30)
Clock cycle time
0.55
CL = 3 (45, 51)
CL = 2.5 (45, 51)
CL = 2 (45, 51)
t
CK (2.5)
tCK (2)
tDH
7.5
10
13
13
7.5
10
0.5
13
13
8
10
13
13
10
13
0.6
0.6
2
-0.8
0.35
0.35
13
15
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CK/CK#
DQS input high pulse width
0.45
0.45
1.75
-0.6
0.35
0.35
0.6
0.6
2
-0.8
0.35
0.35
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
1.75
-0.75
0.35
0.35
+0.6
+0.75
+0.8
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period (34)
Data-out high-impedance window from CK/CK# (18, 42)
Data-out low-impedance window from CK/CK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
0.45
1.25
0.5
1.25
0.6
1.25
0.6
1.25
0.75
0.2
0.2
0.75
0.2
0.2
0.75
0.2
0.2
0.75
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
+0.70
+0.75
+0.8
+0.8
-0.70
0.75
0.75
0.8
0.8
12
-0.75
0.90
0.90
1
1
15
-0.8
1.1
1.1
1.1
1.1
-0.8
1.1
1.1
1.1
1.1
tIH
F
tIS
F
tIH
S
tIS
S
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
16
tHP-tQHS
16
tHP-tQHS
tHP-tQHS
tHP-tQHS
0.55
70,000
0.75
120,000
1
1
42
15
60
72
15
40
20
65
75
20
40
20
70
80
20
120,000
40
20
70
80
20
120,000
15
20
20
20
0.9
0.4
12
0.25
0
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
Internal WRITE to READ command delay
tWTR
1
1
1
1
tCK
Data valid output window (25)
na
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
µs
µs
µs
µs
ns
REFRESH to REFRESH command interval (23) (Commercial & Industrial only)
REFRESH to REFRESH command interval (23) (Military temperature only)*
Average periodic refresh interval (23) (Commercial & Industrial only)
Average periodic refresh interval (23) (Military temperature only)*
Terminating voltage delay to VDD
tREFC
tREFC
tREFI
tREFI
tVTD
70.3
35
7.8
3.9
70.3
35
7.8
3.9
70.3
35
7.8
3.9
70.3
35.15
7.8
3.9
0
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
200
75
200
80
200
80
200
ns
tCK
* Self refresh available in commercial and industrial temperatures only.
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NOTES:
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK# and CK# cross; the input reference level for signals other than CK/CK#
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including
SELF REFRESH mode, VREF must be powered within specified range. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
50Ω
indicated in Note 3, is VTT
.
Output
VTT
(VOUT
)
18. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
19. The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIHDC(MIN) then it must not transition low (below
VIHDC) prior to tDQSH(MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
6.
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may
not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV
for DC error and an additional 25mV for AC noise. This measurement is to be
taken at the nearest VREF by-pass capacitor.
progress, DQS could be HIGH during this time, depending on tDQSS
.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute
7.
8.
V
TT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF
ID is the magnitude of the difference between the input level on CK and the input
level on CK#.
value for tRAS
.
.
23. The refresh period 64ms. (32ms for Military grade) This equates to an average
refresh rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
V
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device
and must track variations in the DC level of the same.
10.
I
CC is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. CC specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
25. The valid data window is derived by achieving other specifications - tHP (tCK/2),
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional
I
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-
DQ15 of each chip.
13. This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz
14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew
rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per
each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that
is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
FIGURE A FULL DRIVE PULL-DOWN
FIGURE B FULL DRIVE PULL-UP
CHARACTERISTICS
CHARACTERISTICS
0
160
-20
Maximum
140
Minimum
-40
120
-60
-80
Nominal low
Nominal high
Nominal high
100
-100
-120
-140
-160
-180
-200
80
Nominal low
60
Minimum
40
20
0
Maximum
0.0
0.5
1.0
CCQ
1.5
- VOUT (V)
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
V
VOUT (V)
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27. This limit is actually a nominal value and does not result in a fail value. CKE is
38. NA
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,
during standby).
39. The voltage levels used are derived from a minimum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus
will provide significantly different voltage values.
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
40.
VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate.
VCC and VCCQ must track each other.
41.
42.
t
HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
tRPST end point and tRPRE begin point are not referenced to a specific voltage level
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
43.
30. CK and CK# input slew rate must be ≤ 1V/ns (≤2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0
volts, provided a minimum of 42 ohms of series resistance is used between the VTT
supply and the input pin.
32.
VCC must not vary more than 4% if CKE is not active while any bank is active.
33. The clock is allowed up to 150ps of ꢀitter. Each timing parameter is allowed to
vary by the same amount.
45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. Random addressing changing: 50% of data changing at every transfer.
48. Random addressing changing: 100% of data changing at every transfer.
49. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
34.
t
HP min is the lesser of tCL minimum and tCH minimum actually applied to the device
CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
RAS(MIN) can be satisfied prior to the internal precharge command being issued.
t
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive. The average cannot be below the 2.5V minimum.
50.
ICC2N specifies the DQ, DQS, and DQM to be driven to a valid high or low logic
level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs
to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.
51. Whenever the operating frequency is altered, not including ꢀitter, the DLL is
required to be reset followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V 100mV.
53. For 333Mbs operation of Industrial and commercial temperatures CL = 2.5, at
Military temperature CL = 3.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
Rev. 0
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W3E64M72S-XBX
White Electronic Designs
ADVANCED
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
32.1 (1.264) MAX
1
2 3 4 5 6 7 8 9 10 111213141516
T
R
P
N
M
L
K
J
H
G
F
19.05 (0.750)
NOM
25.1 (0.988)
MAX
E
D
C
B
A
0.61
(0.024)
NOM
1.27 (0.050)
NOM
219 x Ø 0.762 (0.030) NOM
19.05 (0.750) NOM
2.96 (0.116)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
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W3E64M72S-XBX
White Electronic Designs
ADVANCED
ORDERING INFORMATION
W 3E 64M72 S - XXX B X
WHITE ELECTRONIC DESIGNS CORP.
DDR SDRAM
CONFIGURATION, 64M x 72
2.5V Power Supply
DATA RATE (Mbs)
200 = 200Mbs
250 = 250Mbs
266 = 266Mbs
333 = 333Mbs
PACKAGE:
ES = Non Qualified Product(1)
B = 219 Plastic Ball Grid Array (PBGA)
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
I
= Industrial
C = Commercial 0°C to +70°C
Note 1: W3E64M72S-ESB is the only available product until completion of qualification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
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W3E64M72S-XBX
White Electronic Designs
ADVANCED
Document Title
64M x 72 DDR SDRAM 219 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
June 2005
Advanced
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June 2005
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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