W3EG2256M72ASSR-JD3 [WEDC]
4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL; 4GB - 2x256Mx72 DDR SDRAM ECC挂号，W / PLL
| 型号： | W3EG2256M72ASSR-JD3 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 文件： | 总14页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY*
4GB – 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL
FEATURES
DESCRIPTION
ꢀ
Double-data-rate architecture
The W3EG2256M72ASSR is a 2x256Mx72 Double
Data Rate SDRAM memory module based on 1Gb DDR
SDRAM components. The module consists of eighteen
512Mx4 stacks, in 66 pin TSOP packages mounted on
a 184 pin FR4 substrate.
ꢀ
DDR200, and DDR266:
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Serial presence detect
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Dual Rank
Power supply: VCC = 2.5V 0.2V
JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2-2-2
2-3-3
2.5-3-3
2-2-2
November, 04
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0-A13
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
BA0-BA1
DQ0-DQ63
CB0-CB7
1
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQS8
A0
93
94
VSS
DQ4
DQ5
VCCQ
DQS9
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQS17
A10
2
3
CB2
95
DQS0-DQS17 Data Strobe Input/Output
4
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
VSS
96
CB6
CK0
CK0#
Clock Input
Clock Input
5
CB3
BA1
97
VCCQ
CB7
6
98
CKE0, CKE1 Clock Enable input
7
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
99
VSS
CS0#, CS1#
RAS#
CAS#
WE#
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply
Power Supply for DQS
Ground
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQS14
VSS
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
NC
NC
VCC
VCCQ
DQ12
DQ13
DQS10
VCC
VCCQ
BA0
VSS
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
VREF
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
VCCSPD
SDA
NC
VSS
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VCC
DQ22
A8
SCL
SA0-SA2
VCCID
NC
RESET#
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
DQS5
DQ42
DQ43
VCC
Reset Enable
DQ46
DQ47
NC
NC
DQ48
DQ49
VSS
VCCQ
DQ52
DQ53
A13
NC
NC
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
DQ23
VSS
DQS15
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
A6
DQ28
DQ29
VCCQ
DQS12
A3
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
DQ30
VSS
DQ31
CB4
CB5
VCCQ
CK0
CK0#
DQS16
DQ62
DQ63
VCCQ
SA0
VSS
A1
CB0
CB1
VCC
NC
SDA
SCL
SA1
SA2
VCCSPD
November, 04
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
VSS
RCS1#
RCS0#
DQS0
DQS9
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ0
DQ1
DQ2
DQ3
I/O 3
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS1
DQS2
DQS10
DQS11
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ8
DQ9
DQ10
DQ11
I/O 3
DQ12
DQ13
DQ14
DQ15
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ16
DQ17
DQ18
DQ19
I/O 3
I/O 3
DQ20
DQ21
DQ22
DQ23
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS3
DQS12
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ24
DQ25
DQ26
I/O 3
I/O 3
DQ28
DQ29
DQ30
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ27
DQ31
DQS4
DQS5
DQS6
DQS13
DQS14
DQS15
DQS CS# DM
DQS
CS# DM
CS# DM
CS# DM
DQS CS# DM
DQS CS# DM
DQ32
DQ33
DQ34
I/O 3
I/O 3
DQ36
DQ37
DQ38
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ35
DQ39
DQS
CS# DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
I/O 3
I/O 2
I/O 1
I/O 0
DQ44
DQ45
DQ46
DQ47
DQS
CS# DM
DQS
DQS CS# DM
DQS CS# DM
DQ48
DQ49
DQ50
I/O 3
I/O 3
DQ52
DQ53
DQ54
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ51
DQ55
DQS7
DQS8
DQS16
DQS17
DQS
CS# DM
DQS
CS# DM
DQS CS# DM
DQS CS# DM
DQ56
DQ57
DQ58
I/O 3
I/O 3
DQ60
DQ61
DQ62
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ59
DQ63
DQS
CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
CB0
CB1
CB2
I/O 3
I/O 3
CB4
CB5
CB6
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
CB3
CB7
SERIAL PD
SPD
VCCSPD
VCC/VCCQ
VREF
CK0
SDRAM
SDA
SCL
WP
PLL
A1
A2
A0
DDR SDRAM
SA1 SA2
SA0
CK0#
REGISTER
DDR SDRAM
DDR SDRAM
R
E
G
I
S
T
E
R
CS0#
RCS0#
VSS
CS1#
BA0,BA1
A0-A13
RAS#
RCS1#
RBA0,RBA1
RA0-RA13
RRAS#
BA0,BA1: DDR SDRAMs
A0-A13: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
RCAS#
CAS#
NOTES:
RCKE0
CKE0
RCKE1
CKE1
1. DQ-to-I/O wiring is shown as
recommended but may be changed.
RWE#
WE#
RESET#
Note: All resistor values are 22 ohms
unless otherwise specified.
PCK
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
PCK#
November, 04
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
V
V
°C
W
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-0.5 - 3.6
-1.0 - 3.6
-55 - +150
27
Power Dissipation
PD
Short Circuit Current
I0S
50
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V 0.2V
Parameter
Supply Voltage
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
VCCQ
VREF
VTT
VIH
VIL
2.3
1.15
1.15
2.7
1.35
1.35
V
V
V
V
V
V
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VREF + 0.15
-0.3
VTT + 0.76
—
VCCQ + 0.3
VREF - 0.15
—
VOH
VOL
VTT - 0.76
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V 0.2V
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max
6.25
6.25
6.25
5.5
6.25
13
6.25
13
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A13)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
13
November, 04
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V.
Includes DDR SDRAM components only
Rank 2
Standby
State
Rank 1
Symbol Conditions
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
Parameter
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC = tRC
4680
4230
mA
IDD3N
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and
control inputs changing once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
5310
4860
mA
IDD3N
Precharge Power-
IDD2P All device banks idle; Power-down mode; tCK
=
360
360
rnA
mA
IDD2P
IDD2F
Down Standby Current
tCK (MIN); CKE = (low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
2340
2160
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
1260
1800
1080
1620
mA
mA
IDD3P
IDD3N
Active Standby Current
IDD3N CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle.
Operating Current
Operating Current
IDD4R Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
5760
5940
5220
5400
mA
rnA
IDD3N
IDD4W Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
IDD3N
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC (MIN)
7920
324
7560
324
mA
mA
mA
IDD3N
IDD6
CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
11250
10350
IDD3N
November, 04
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V.
Includes PLL and register power
Rank 2
Standby
State
Rank 1
Symbol Conditions
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
Parameter
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC = tRC
5265
4815
mA
IDD3N
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and
control inputs changing once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
5895
5445
mA
IDD3N
Precharge Power-
IDD2P All device banks idle; Power-down mode; tCK
=
360
360
rnA
mA
IDD2P
IDD2F
Down Standby Current
tCK (MIN); CKE = (low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
2650
2470
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
1260
2110
1080
1930
mA
mA
IDD3P
IDD3N
Active Standby Current
IDD3N CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle.
Operating Current
Operating Current
IDD4R Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
6345
6525
5805
5985
mA
rnA
IDD3N
IDD4W Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
IDD3N
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC (MIN)
8540
599
8180
599
mA
mA
mA
IDD3N
IDD6
CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
11835
10935
IDD3N
November, 04
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRCD = 2*tCK, tRAg = 5*tCK
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL
= 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November, 04
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC Characteristics
262
263/265
202
Parameter
Symbol
Min
-0.7
0.45
0.45
6
Max
+0.7
0.55
0.55
13
Min
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
tAC
-0.75
0.45
0.45
7.5
tCH
tCL
16
16
Clock cycle time
CL=2.5 tCK (2.5)
22
CL=2
tCK (2)
tDH
7.5
13
7.5/10
0.5
13
10
13
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.45
0.45
1.75
-0.6
0.35
0.35
0.6
0.6
2
14,17
14,17
17
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
1.75
-0.75
0.35
0.35
+0.60
+0.75
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.5
0.5
0.5
13,14
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
0.2
tCH, tCL
+0.70
tCH, tCL
+0.75
tCH, tCL
+0.8
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
tLZ
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
-0.8
1.1
1.1
1.1
1.1
2.2
16
tIHf
tISf
6
tIHs
6
tISs
1
6
tIPW
tMRD
tQH
2.2
15
15
tHP-tQHS
tHP-tQHS
tHP-tQHS
13,14
15
tQHS
tRAS
tRAP
tRC
0.75
0.75
1
ACTIVE to PRECHARGE command
45
15
120,000
45
20
120,000
45
20
120,000
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
60
65
70
tRFC
120
120
120
21
November, 04
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC Characteristics
262
263/265
202
Parameter
Symbol
tRCD
Min
15
Max
Min
20
Max
Min
20
Max
Units
ns
Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRP
15
20
20
ns
tRPRE
tRPST
tRRD
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
tCK
ns
19
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
0.25
0
tCK
ns
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
tCK
ns
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
1
1
1
tCK
ns
NA
tQH-tDQSQ
70.3
tQH-tDQSQ
70.3
7.8
tQH-tDQSQ
70.3
7.8
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
μs
7.8
μs
tVTD
0
0
0
ns
tXSNR
tXSRD
75
75
75
ns
200
200
200
tCK
November, 04
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
Notes
11. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in progress on the
bus. If a previous WRITE was in progress, DQS could be high during
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at normal reference / supply voltage levels, but the related specifications
and device operations are guaranteed for the full voltage range specified.
this time, depending on tDQSS
.
3. Outputs are measured with equivalent load:
12. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh cycles is not allowed.
V
TT
50Ω
RReeffeerreennccee
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates directly proportional with the clock duty cycle and a practical
data valid window can be derived. The clock is allowed a maximum
duty cycled variation of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. The data valid window derating
curves are provided below for duty cycles ranging between 50/50
and 45/55.
Outtppuutt
Poiint
(VOUT
)
30pF
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC) and VIH(AC).
14. Referenced to each output group: x4 = DQS with DQ0-DQ3.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
5. The AC and DC input level specifications are defined in the SSTL_2
standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
6. For slew rates less than 1V/ns and greater than or equal to 0.5V/ns.
If the slew rate is less than 0.5V/ns, timing must be derated: tIS has
an additional 50ps per each 100mV/ns reduction in slew rate from
the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain. For 266, slew
rates must be greater than or equal to 0.5V/ns.
18. tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition.
t
LZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.
7. Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
8. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
9. The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition LOW
(below VIHDC) prior to tDQSH (MIN).
22. Whenever the operating frequency is altered, not including jitter, the
DLL is required to be reset. This is followed by 200 clock cycles (before
READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
November, 04
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
2
tRP
2
Height*
W3EG2256M72ASSR262JD3xG
W3EG2256M72ASSR263JD3xG
W3EG2256M72ASSR265JD3xG
W3EG2256M72ASSR202JD3xG
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2
2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
3
3
2.5
2
3
3
2
2
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
6.35
(0.250 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
30.48
(1.20 MAX)
17.78
(0.700)
1.27
(0.050 TYP.)
2.31
(0.091)
(2x)
10.0
(0.394)
3.99
(0.157)
(MIN)
6.35
(0.250)
49.53
(1.950)
1.27
0.10
(0.050)
( 0.004)
64.77
(2.550)
3.00
(0.118)
(4x)
6.36
(0.250)
1.78
(0.070)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November, 04
Rev. 3
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR AJD3
Part Number
Speed
CAS Latency
tRCD
2
tRP
2
Height*
W3EG2256M72ASSR262AJD3xG
W3EG2256M72ASSR263AJD3xG
W3EG2256M72ASSR265AJD3xG
W3EG2256M72ASSR202AJD3xG
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2
2
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
3
3
2.5
2
3
3
2
2
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AJD3
133.48
(5.255" MAX.)
131.34
(5.171")
6.35
(0.250 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
28.70
(1.13 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
1.27
(0.050 TYP.)
10.0
(0.394)
3.99
(0.157)
(MIN)
6.35
(0.250)
49.53
(1.950)
1.27
0.10
(0.050)
0.004)
64.77
(2.550)
3.00
(0.118)
(4x)
6.35
(0.250)
(
1.78
(0.070)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November, 04
Rev. 3
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
PART NUMBERING GUIDE
W 3 E G 2 256M 72 A S S R xxx JD3 x G
WEDC
MEMORY
DDR
GOLD
RANKS
DEPTH (Dual Rank)
BUS WIDTH
x4
Stack TSOP
2.5V
REGISTERED
SPEED (MHz)
PACKAGE or AJD3
COMPONENT VENDOR
RoHS COMPLIANT
November, 04
Rev. 3
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG2256M72ASSR-JD3
-AJD3
White Electronic Designs
PRELIMINARY
Document Title
4GB – 2x256Mx72, DDR SDRAM Registered ECC, w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
5-2-03
Advanced
Rev 1
1.1 Package dimension change, status
1.2 Updated CAP and IDD specs
3-15-04
Preliminary
1.3 Removed "ED" from part number
1.4 Moved from Advanced to Preliminary
1.5 Added document title page
Rev 2
Rev 3
2.1 Changed data sheet part number (W3EG72512S-JD3) to
new part numbering system.
11-04
11-04
Preliminary
Preliminary
2.2 Added part numbering guide
3.1 Added Lead-Free and RoHS note
3.2 Added vendor code options
M = Micron
S = Samsung
November, 04
Rev. 3
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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