W78M32V90BC [WEDC]
8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package; 8Mx32闪光3.3V页模式同步读/写操作的多芯片封装
| 型号： | W78M32V90BC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| 文件： | 总54页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78M32V-XBX
White Electronic Designs
8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write
Operation Multi-Chip Package
FEATURES
ꢀ
Access Times of 70, 90, 100, 120ns
ꢀ
ꢀ
ꢀ
ꢀ
Unlock Bypass Program command
ꢀ
Packaging
• Reduces overall programming time when issuing
multiple program command sequences
• 159 PBGA, 13x22mm – 1.27mm pitch
1,000,000 Erase/Program Cycles per sector
Page Mode
Ready/Busy# output (RY/BY#)
ꢀ
ꢀ
• Hardware method for detecting program or erase
cycle completion
• Page size is 8 words: Fast page read access from
random locations within the page.
Hardware reset pin (RESET#)
• Hardware method of resetting the internal state
machine to the read mode
ꢀ
Sector Architecture
• Bank A (16Mb): 4Kw x 8 and 32 Kw x 31
• Bank B (48Mb): 32Kw x 96
WP#/ACC input pin
• Write protect (WP#) function allows protection of
two outermost boot sector, regardless of sector
protect status
• Bank C (48Mb): 32Kw x 96
• Bank D (16Mb): 4Kw x 8 and 3Kw x 31
Both top and bottom boot blocks
Zero Power Operation
ꢀ
ꢀ
ꢀ
ꢀ
• Acceleration (ACC) function accelerates program
timing
ꢀ
ꢀ
Persistent Sector Protection
Organized as 8Mx32, user configurable as 2x8Mx16
• A command sector protection method of locking
combinations of individual sectors and sector
groups to prevent program or erase operation
within that sector
Commercial, Industrial and Military Temperature
Ranges
ꢀ
ꢀ
3.3 Volt for read, erase and write operations
Simultaneous read/write operations:
Password Sector Protection or Cancellation
• Data can be continuously read from one bank
while executing erase/program functions in
another bank
• A sector protection method to lock combinations
of individual sectors and sector groups to prevent
program or erase operations within that sector
using a user-defined 64-bit password.
• Zero latency between read and write operations
Erase Suspend/Resume
ꢀ
ꢀ
• Suspends erase operations to allow read or
programming in other sectors of same bank
* This product is subject to change without notice.
Data Polling and Toggle Bits
• Provides a software method of detecting the status
of program or erase cycles
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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FIG 1: PIN CONFIGURATION
FOR W78M32V-XBX (TOP VIEW)
PIN DESCRIPTION
1
2
GND
GND
3
4
5
VCC
VIO
6
VIO
NC
7
GND
DNU
NC
8
9 10
DQ0-31
A0-22
WE#1-2
CS#1-2
OE#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Hardware Reset
GND
GND
GND
GND
VCC
A
B
C
D
E
F
VIO
DQ25 WE2#
NC
VCC
NC
VIO
VCC
DQ17 DQ27 DQ29 DQ31
DQ24 DQ19 DQ21 DQ23
DQ16 DQ26 DQ28 DQ30
NC
NC
VCC
RESET#
WP#/ACC
Hardware Write
Protection/Acceleration
VIO
NC
NC
NC
NC
VIO
RY/BY#
VCC
Ready/Busy Output
Power Supply
I/O Power Supply
Ground
VCC
NC
NC
NC
NC
VCC
GND
GND
GND
GND
GND
GND
VIO
GND
GND
GND
GND
GND
GND
VIO
CS2#
OE#
A2
DQ18 DQ20 DQ22
NC
NC
NC
NC
VIO
GND
DNU
NC
A0
A22
A11
VCC
GND
VCC
GND
DNU*
NC
A12
VIO
A16
A7
A21
A10
RESET#
A20
A15
A13
A8
G
H
J
Do Not Use
Not Connected
WP#/ACC
A3
A6
A17
NC
A9
GND
A14
DQ9
DQ1
DQ8
DQ0
CS1#
VCC
A1
RY/BY#
A4
A5
A18
WE1#
DQ6
K
L
BLOCK DIAGRAM
NC
NC
NC
DQ4
DQ11
DQ3
DQ10
DQ2
GND
A19
DQ15
DQ7
DQ14
GND
GND
WE1#
WE2#
CS1#
CS2#
NC
NC
M
N
P
R
T
RY/BY#
RESET#
OE#
A0-22
VCC
NC
NC
NC
NC
DQ13
DQ5
VCC
8M X 16
8M X 16
VIO
NC
NC
NC
NC
VIO
VCC
VCC
GND
NC
NC
NC
DQ12
GND
VCC
WP#/ACC
DQ0-15
DQ16-31
VIO
GND
GND
VIO
VIO
*Ball L5 is reserved for A23 on future upgrades
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April 2006
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W78M32V-XBX
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GENERAL DESCRIPTION
JEDEC 42.4 single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
The W78M32V-XBX is a 256Mb, 3.3 volt-only Page Mode
and Simultaneous Read/Write Flash memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls. Simultaneous Read/Write Operation with Zero
Latency.
Device programming occurs by executing the program
command sequence. The Unlock Bypass mode facilitates
faster programming times by requiring only two write cycles
to program data instead of four. Device erasure occurs by
executing the erase command sequence.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space
into 4 banks, which can be considered to be four separate
memory arrays as far as certain operations are concerned.
The device can improve overall system performance by
allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations
operating at any one time). This releases the system from
waiting for the completion of a program or erase operation,
greatly improving system performance.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling)
and DQ6 (toggle) status bits.After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectors.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection
feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved
in-system or via programming equipment.
Bank
Sectors
A
B
C
D
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If
a read is needed from the SecSi Sector area (One Time
Program area) after an erase suspend, then the user must
use the proper command sequence to enter and exit this
region.
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Standard Flash Memory
Features
The device requires a 3.3 volt power supply for both read and
write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the
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April 2006
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DEVICE BUS OPERATIONS
command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device. Table 1 lists the device
bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is a latch used to store the commands, along with
the address and data information needed to execute the
TABLE 1. DEVICE BUS OPERATION3
Operation
CS#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A22-A0)
DQ15-DQ0
L
L
L
H
X
H
L
H
H
X
X
AIN
AIN
X
DOUT
DIN
Read
Write
Standby
VIO
0.3 V
X
VIO
0.3 V
X (Note 2)
High-Z
L
X
X
H
X
X
H
X
X
H
X
X
X
X
X
High-Z
High-Z
DIN
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage
L
VID
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In,
DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section.
2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
3. For each chip
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable
REQUIREMENTS FOR READING
ARRAY DATA
addresses to valid output data. The chip enable access
To read array data from the outputs, the system must drive
time (tCS) is the delay from the stable addresses and stable
the OE# and appropriate CS# pins to VIL. CS# is the power
CS# to valid data at the output inputs. The output enable
control. OE# is the output control and gates array data to
access time is the delay from the falling edge of the OE#
the output pins. WE# should remain at VIH.
to valid data at the output inputs (assuming the addresses
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until
the command register contents are altered.
have been stable for at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. Address bits A22–A3 select an 8
word page, and address bits A2–A0 select a specific word
within that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
Refer to theAC Characteristics table for timing specifications
and to Figure 11 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
The random or initial page access is tACC or tCS and
subsequent page read accesses (as long as the locations
specified by the microprocessor falls within that page) is
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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equivalent to tPACC. When CS# is deasserted (CS#=VIH),
the reassertion of CS# for subsequent access has access
time of tACC or tCS. Here again, CS# selects the device and
OE# is the output control and should be used to gate data
to the output inputs if the device is selected. Fast page
mode accesses are obtained by keeping A22–A3 constant
and changing A2–A0 to select the specific word within that
page.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word,
instead of four. The “Word Program Command Sequence”
section has details on programming data to the device using
both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 4 indicates the address space
that each sector occupies. A “bank address” is the address
bits required to uniquely select a bank. Similarly, a “sector
address” refers to the address bits required to uniquely
select a sector. The “Command Definitions” section has
details on erasing a sector or the entire chip, or suspending/
resuming the erase operation.
TABLE 2. PAGE SELECT
Word
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics section contains timing specification tables
and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through
theACC function. This function is primarily intended to allow
faster manufacturing throughput at the factory.
SIMULTANEOUS OPERATION
In addition to the conventional features (read, program,
erase-suspend read, and erase-suspend program), the
device is capable of reading data from one bank of memory
while a program or erase operation is in progress in another
bank of memory (simultaneous operation). The bank can be
selected by bank addresses (A22–A20) with zero latency.
If the system asserts VHH on this pin, the device automatically
enters the mentioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing VHH from the WP#/ACC pin returns the
device to normal operation. Note that VHH must not be
asserted on WP#/ACC for operations other than accelerated
programming, or device damage may result. In addition,
the WP#/ACC pin should be raised to VCC when not in
use. That is, the WP#/ACC pin should not be left floating
or unconnected; inconsistent behavior of the device may
result.
The simultaneous operation can execute multi-function
mode in the same bank.
TABLE 3. BANK SELECT
Bank
A22-A20
000
001, 010, 011
100, 101, 110
111
Bank A
Bank B
Bank C
Bank D
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ63–DQ0. Standard
read cycle timings apply in this mode. Refer to theAutoselect
Mode and Autoselect Command Sequence sections for
more information.
WRITING COMMANDS/COMMAND
SEQUENCES
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CS# to VIL, and
OE# to VIH.
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not within VSS 0.3 V, the standby current will be greater.
STANDBY MODE
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE#
input. The device enters the CMOS standby mode when the
CS# and RESET# pins are both held at VIO 0.3 V. If CS#
and RESET# are held at VIH, but not within VIO 0.3 V, the
device will be in the standby mode, but the standby current
will be greater. The device requires standard access time
(tCS) for read access when the device is in either of these
standby modes, before it is ready to read data.
If RESET# is asserted during a program or erase operation,
the RY/BY# pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time of tREADY (during
Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete.
If RESET# is asserted when a program or erase operation
is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the RESET#
pin returns to VIH.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
Refer to theAC Characteristic tables for RESET# parameters
and to Figure 14 for the timing diagram.
I
CC3 in the DC Characteristics table represents the CMOS
standby current specification.
OUTPUT DISABLE MODE
When the OE# input is at VIH, output from the device is
disabled. The output pins (except for RY/BY#) are placed
in the highest Impedance state.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 150 ns. The
automatic sleep mode is independent of the CS#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. Note that during automatic sleep mode,
OE# must be at VIH before the device reduces current
to the stated sleep mode specification. ICC5 in the DC
Characteristics table represents the automatic sleep mode
current specification.
RESET#: HARDWARE RESET PIN
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
driven low for at least a period of tRP, the device immediately
terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS 0.3 V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL but
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
Sector Address (A22-A12)
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
00000001XXX
00000010XXX
00000011XXX
00000100XXX
00000101XXX
00000110XXX
00000111XXX
00001000XXX
00001001XXX
00001010XXX
00001011XXX
00001100XXX
00001101XXX
00001110XXX
00001111XXX
00010000XXX
00010001XXX
00010010XXX
00010011XXX
00010100XXX
00010101XXX
00010110XXX
00010111XXX
00011000XXX
00011001XXX
00011010XXX
00011011XXX
00011100XXX
00011101XXX
00011110XXX
00011111XXX
Sector Size (Kwords)
Address Range (x16)
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
4
4
4
4
4
4
4
4
SA8
SA9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
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April 2006
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
Sector Address (A22-A12)
00100000XXX
00100001XXX
00100010XXX
00100011XXX
00100100XXX
00100101XXX
00100110XXX
00100111XXX
00101000XXX
00101001XXX
00101010XXX
00101011XXX
00101100XXX
00101101XXX
00101110XXX
00101111XXX
00110000XXX
00110001XXX
00110010XXX
00110011XXX
00110100XXX
00110101XXX
00110110XXX
00110111XXX
00111000XXX
00111001XXX
00111010XXX
00111011XXX
00111100XXX
00111101XXX
00111110XXX
00111111XXX
01000000XXX
01000001XXX
01000010XXX
01000011XXX
01000100XXX
01000101XXX
01000110XXX
01000111XXX
Sector Size (Kwords)
Address Range (x16)
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
Sector Address (A22-A12)
01001000XXX
01001001XXX
01001010XXX
01001011XXX
01001100XXX
01001101XXX
01001110XXX
01001111XXX
01010000XXX
01010001XXX
01010010XXX
01010011XXX
01010100XXX
01010101XXX
01010110XXX
01010111XXX
01011000XXX
01011001XXX
01011010XXX
01011011XXX
01011100XXX
01011101XXX
01011110XXX
01011111XXX
01100000XXX
01100001XXX
01100010XXX
01100011XXX
01100100XXX
01100101XXX
01100110XXX
01100111XXX
01101000XXX
01101001XXX
01101010XXX
01101011XXX
01101100XXX
01101101XXX
01101110XXX
01101111XXX
Sector Size (Kwords)
Address Range (x16)
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–287FFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2F7FFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
Sector Address (A22-A12)
01110000XXX
01110001XXX
01110010XXX
01110011XXX
01110100XXX
01110101XXX
01110110XXX
01110111XXX
01111000XXX
01111001XXX
01111010XXX
01111011XXX
01111100XXX
01111101XXX
01111110XXX
01111111XXX
10000000XXX
10000001XXX
10000010XXX
10000011XXX
10000100XXX
10000101XXX
10000110XXX
10000111XXX
10001000XXX
10001001XXX
10001010XXX
10001011XXX
10001100XXX
10001101XXX
10001110XXX
10001111XXX
10010000XXX
10010001XXX
10010010XXX
10010011XXX
10010100XXX
10010101XXX
10010110XXX
10010111XXX
Sector Size (Kwords)
Address Range (x16)
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
400000h–407FFFh
408000h–40FFFFh
410000h–417FFFh
418000h–41FFFFh
420000h–427FFFh
428000h–42FFFFh
430000h–437FFFh
438000h–43FFFFh
440000h–447FFFh
448000h–44FFFFh
450000h–457FFFh
458000h–45FFFFh
460000h–467FFFh
468000h–46FFFFh
470000h–477FFFh
478000h–47FFFFh
480000h–487FFFh
488000h–48FFFFh
490000h–497FFFh
498000h–49FFFFh
4A0000h–4A7FFFh
4A8000h–4AFFFFh
4B0000h–4B7FFFh
4B8000h–4BFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
Sector Address (A22-A12)
10011000XXX
10011001XXX
10011010XXX
10011011XXX
10011100XXX
10011101XXX
10011110XXX
10011111XXX
10100000XXX
10100001XXX
10100010XXX
10100011XXX
10100100XXX
10100101XXX
10100110XXX
10101000XXX
10101001XXX
10101010XXX
10101011XXX
10101100XXX
10101101XXX
10101110XXX
10101111XXX
10110000XXX
10110001XXX
10110010XXX
10110011XXX
10110100XXX
10110101XXX
10110110XXX
10110111XXX
10111000XXX
10111001XXX
10111010XXX
10111011XXX
10111100XXX
10111101XXX
10111110XXX
10111111XXX
Sector Size (Kwords)
Address Range (x16)
4C0000h–4C7FFFh
4C8000h–4CFFFFh
4D0000h–4D7FFFh
4D8000h–4DFFFFh
4E0000h–4E7FFFh
4E8000h–4EFFFFh
4F0000h–4F7FFFh
4F8000h–4FFFFFh
500000h–507FFFh
508000h–50FFFFh
510000h–517FFFh
518000h–51FFFFh
520000h–527FFFh
528000h–52FFFFh
538000h–53FFFFh
540000h–547FFFh
548000h–54FFFFh
550000h–557FFFh
558000h–15FFFFh
560000h–567FFFh
568000h–56FFFFh
570000h–577FFFh
578000h–57FFFFh
580000h–587FFFh
588000h–58FFFFh
590000h–597FFFh
598000h–59FFFFh
5A0000h–5A7FFFh
5A8000h–5AFFFFh
5B0000h–5B7FFFh
5B8000h–5BFFFFh
5C0000h–5C7FFFh
5C8000h–5CFFFFh
5D0000h–5D7FFFh
5D8000h–5DFFFFh
5E0000h–5E7FFFh
5E8000h–5EFFFFh
5F0000h–5F7FFFh
5F8000h–5FFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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TABLE 4. SECTOR ARCHITECTURE
Bank
Sector
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
Sector Address (A22-A12)
11000000XXX
11000001XXX
11000010XXX
11000011XXX
11000100XXX
11000101XXX
11000110XXX
11000111XXX
11001001XXX
11001010XXX
11001011XXX
11001100XXX
11001101XXX
11001110XXX
11001111XXX
11010000XXX
11010001XXX
11010010XXX
11010011XXX
11010100XXX
11010101XXX
11010110XXX
11010111XXX
11011000XXX
11011001XXX
11011010XXX
11011011XXX
11011100XXX
11011101XXX
11011110XXX
11011111XXX
Sector Size (Kwords)
Address Range (x16)
600000h–607FFFh
608000h–60FFFFh
610000h–617FFFh
618000h–61FFFFh
620000h–627FFFh
628000h–62FFFFh
630000h–637FFFh
638000h–63FFFFh
648000h–64FFFFh
650000h–657FFFh
658000h–65FFFFh
660000h–667FFFh
668000h–66FFFFh
670000h–677FFFh
678000h–67FFFFh
680000h–687FFFh
688000h–68FFFFh
690000h–697FFFh
698000h–69FFFFh
6A0000h–6A7FFFh
6A8000h–6AFFFFh
6B0000h–6B7FFFh
6B8000h–6BFFFFh
6C0000h–6C7FFFh
6C8000h–6CFFFFh
6D0000h–6D7FFFh
6D8000h–6DFFFFh
6E0000h–6E7FFFh
6E8000h–6EFFFFh
6F0000h–6F7FFFh
6F8000h–6FFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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TABLE 4. SECTOR ARCHITECTURE
Sector
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
Sector Address (A22-A12)
11100000XXX
11100001XXX
11100010XXX
11100011XXX
11100100XXX
11100101XXX
11100110XXX
11100111XXX
11101000XXX
11101001XXX
11101010XXX
11101011XXX
11101100XXX
11101101XXX
11101110XXX
11101111XXX
11110000XXX
11110001XXX
11110010XXX
11110011XXX
11110100XXX
11110101XXX
11110110XXX
11110111XXX
11111000XXX
11111001XXX
11111010XXX
11111011XXX
11111100XXX
11111101XXX
11111110XXX
11111111000
Sector Size (Kwords)
Address Range (x16)
700000h-707FFFh
708000h-70FFFFh
710000h-717FFFh
718000h-71FFFFh
720000h-727FFFh
728000h-72FFFFh
730000h-737FFFh
738000h-73FFFFh
740000h-747FFFh
748000h-74FFFFh
750000h-757FFFh
758000h-75FFFFh
760000h-767FFFh
768000h-76FFFFh
770000h-777FFFh
778000h-77FFFFh
780000h-787FFFh
788000h-78FFFFh
790000h-797FFFh
798000h-79FFFFh
7A0000h-7A7FFFh
7A8000h-7AFFFFh
7B0000h-7B7FFFh
7B8000h-7BFFFFh
7O0000h-7C7FFFh
7C8000h-7CFFFFh
7D0000h-7D7FFFh
7D8000h-7DFFFFh
7E0000h-7E7FFFh
7E8000h-7EFFFFh
7F0000h-7F7FFFh
7F8000h-7F8FFFh
7F9000h-7F9FFFh
7FA000h-7FAFFFh
7FB000h-7FBFFFh
7FO000h-7FCFFFh
7FD000h-7FDFFFh
7FE000h-7FEFFFh
7FF000h-7FFFFFh
Bank
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
11111111001
11111111010
11111111011
11111111100
11111111101
11111111110
11111111111
4
4
4
4
4
4
4
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TABLE 5. SecSiTM SECTOR ADDRESSES
sector protection, the sector address must appear on
the appropriate highest order address bits (see Table
4). Table 6 shows the remaining address bits that are
don’t care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0. However, the
autoselect codes can also be accessed in-system through
the command register, for instances when the device is
erased or programmed in a system without access to high
voltage on theA9 pin. The command sequence is illustrated
in Table 13. Note that if a Bank Address (BA) on address
bits A22–A20 is asserted during the third write cycle of the
autoselect command, the host system can read autoselect
data that bank and then immediately read array data from
the other bank, without exiting the autoselect mode.
Sector Size
128 words
64 words
Address Range
000000h–00007Fh
000000h-00003Fh
000040h-00007Fh
Device
Factory-Locked Area
Customer-Lockable Area
64 words
AUTOSELECT MODE
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on DQ7–DQ0 for each chip. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through
the command register.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 13. This method does not require
VID. Refer to the Autoselect Command Sequence section
for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
must be as shown in Table 6. In addition, when verifying
TABLE 6. AUTOSELECT CODES (HIGH VOLTAGE METHOD)
Description
CS# OE# WE#
A22
to
A12
A10
A9 A8 A7 A6
A5
to
A4
A3 A2
A1
A0
DQ15
to
DQ0 (each chip)
Manufacturer ID:
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
L
L
L
L
X
L
L
L
L
L
L
L
L
H
0004h
227Eh
Read
Cycle 1
Read
L
L
L
L
H
H
L
H
H
L
H
H
H
H
L
H
L
2220
Cycle 2
Read
Cycle 3
Sector Protection
Verification
SecSi Indicator Bit
(DQ7, DQ6)
2200h
L
L
H
H
SA
X
X
X
VID
VID
X
X
L
L
L
L
0001h (protected),
0000h (unprotected)
X
X
L
L
H
00C0h (factory and
user locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system
via command sequences
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TABLE 7. BOOT SECTOR/SECTOR
BLOCK ADDRESSES FOR PROTECTION/
UNPROTECTION
Sector
A22-A12
Sector/
Sector Block Size
SA131-SA134
SA135-SA138
SA139-SA142
SA143-SA146
SA147-SA150
SA151-SA154
SA155-SA158
SA159-SA162
SA163-SA166
SA167-SA170
SA171-SA174
SA175-SA178
SA179-SA182
SA183-SA186
SA187-SA190
SA191-SA194
SA195-SA198
SA199-SA202
SA203-SA206
SA207-SA210
SA211-SA214
SA215-SA218
SA219-SA222
SA223-SA226
SA227-SA230
SA231-SA234
SA235-SA238
SA239-SA242
SA243-SA246
SA247-SA250
SA251-SA254
SA255-SA258
SA259-SA261
011111XXXXX
100000XXXXX
100001XXXXX
100010XXXXX
100011XXXXX
100100XXXXX
100101XXXXX
100110XXXXX
100111XXXXX
101000XXXXX
101001XXXXX
101010XXXXX
101011XXXXX
101100XXXXX
101101XXXXX
101110XXXXX
101111XXXXX
110000XXXXX
110001XXXXX
110010XXXXX
110011XXXXX
110100XXXXX
110101XXXXX
110110XXXXX
110111XXXXX
111000XXXXX
111001XXXXX
111010XXXXX
111011XXXXX
111100XXXXX
111101XXXXX
111110XXXXX
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
96 (3x32) Kwords
Sector
A22-A12
Sector/
Sector Block Size
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
SA8-SA10
00000001XXX
00000010XXX
00000011XXX
96 (3x32) Kwords
SA11-SA14
SA15-SA18
SA19-SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55-SA58
SA59-SA62
SA63-SA66
SA67-SA70
SA71-SA74
SA75-SA78
SA79-SA82
SA83-SA86
SA87-SA90
SA91-SA94
SA95-SA98
SA99-SA102
SA103-SA106
SA107-SA110
SA111-SA114
SA115-SA118
SA119-SA122
SA123-SA126
SA127-SA130
000001XXXXX
000010XXXXX
000011XXXXX
000100XXXXX
000101XXXXX
000110XXXXX
000111XXXXX
001000XXXXX
001001XXXXX
001010XXXXX
001011XXXXX
001100XXXXX
001101XXXXX
001110XXXXX
001111XXXXX
010000XXXXX
010001XXXXX
010010XXXXX
010011XXXXX
010100XXXXX
010101XXXXX
010110XXXXX
010111XXXXX
011000XXXXX
011001XXXXX
011010XXXXX
011011XXXXX
011100XXXXX
011101XXXXX
011110XXXXX
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
11111100XXX
11111101XXX
11111110XXX
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
11111111000
11111111001
11111111010
11111111011
11111111100
11111111101
11111111110
11111111111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
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protection states:
Persistently Locked—The sector is protected and
cannot be changed.
SECTOR PROTECTION
ꢀ
The device features several levels of sector protection,
which can disable both the program and erase operations
in certain sectors or sector groups:
ꢀ
Dynamically Locked—The sector is protected and
can be changed by a simple command.
Persistent Sector Protection
ꢀ
Unlocked—The sector is unprotected and can be
A command sector protection method that replaces the old
12 V controlled protection method.
changed by a simple command.
To achieve these states, three types of “bits” are used:
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned
to a maximum four sectors (see the sector address tables
for specific sector protection groupings). All 4 Kword boot-
block sectors have individual sector Persistent Protection
Bits (PPBs) for greater flexibility. Each PPB is individually
modifiable through the PPB Write Command.
The device erases all PPBs in parallel. If any PPB requires
erasure, the device must be instructed to preprogram all
of the sector PPBs prior to PPB erasure. Otherwise, a
previously erased sector PPBs can potentially be over-
erased. The flash device does not have a built-in means
of preventing sector PPBs over-erasure.
Password Sector Protection
A highly sophisticated protection method that requires
a password before changes to certain sectors or sector
groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase
operations in sectors 0, 1, 268, and 269.
The WP# Hardware Protection feature is always available,
independent of the software managed protection method
chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector
Protection mode. The user must then choose if the
Persistent or Password Protection method is most desirable.
There are two one-time programmable non-volatile bits
that define which sector protection method will be used.
If the Persistent Sector Protection method is desired,
programming the Persistent Sector Protection Mode
Locking Bit permanently sets the device to the Persistent
Sector Protection mode. If the Password Sector Protection
method is desired, programming the Password Mode
Locking Bit permanently sets the device to the Password
Sector Protection mode. It is not possible to switch between
the two protection modes once a locking bit has been set.
One of the two modes must be selected when the device
is first programmed. This prevents a program or virus from
later setting the Password Mode Locking Bit, which would
cause an unexpected shift from the default Persistent Sector
Protection Mode into the Password Protection Mode.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global
volatile bit. When set to “1”, the PPBs cannot be changed.
When cleared (“0”), the PPBs are changeable. There is
only one PPB Lock bit per device. The PPB Lock is cleared
after power-up or hardware reset. There is no command
sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After
power-up or hardware reset, the contents of all DYBs is
“0”. Each DYB is individually modifiable through the DYB
Write Command.
When the parts are first shipped, the PPBs are cleared, the
DYBs are cleared, and PPB Lock is defaulted to power up in
the cleared state – meaning the PPBs are changeable.
The device is shipped with all sectors unprotected.
When the device is first powered on the DYBs power up
cleared (sectors not protected). The Protection State for
each sector is determined by the logical OR of the PPB and
the DYB related to that sector. For the sectors that have the
PPBs cleared, the DYBs control whether or not the sector
is protected or unprotected. By issuing the DYB Write
It is possible to determine whether a sector is protected or
unprotected. See Autoselect Mode for details.
PERSISTENT SECTOR PROTECTION
The Persistent Sector Protection method replaces the 12
V controlled protection method in previous WEDC flash
devices. This new method provides three different sector
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command sequences, the DYBs will be set or cleared, thus
placing each sector in the protected or unprotected state.
These are the so-called Dynamic Locked or Unlocked
states. They are called dynamic states because it is very
easy to switch back and forth between the protected and
unprotected conditions. This allows software to easily protect
sectors against inadvertent changes yet does not prevent
the easy removal of protection when changes are needed.
The DYBs maybe set or cleared as often as needed.
bit set command early in the boot code, and protect the boot
code by holding WP#/ACC = VIL.
TABLE 8. SECTOR PROTECTION SCHEMES
DYB
PPB
PPB
LOCK
SECTOR STATE
0
0
0
0
0
Unprotected - PPB and DYB are
changeable
Unprotected - PPB not changeable,
DYB is changeable
The PPBs allow for a more static, and difficult to change,
level of protection. The PPBs retain their state across power
cycles because they are non-volatile. Individual PPBs are set
with a command but must all be cleared as a group through
a complex sequence of program and erasing commands.
The PPBs are also limited to 100 erase cycles.
1
0
1
1
0
1
1
1
0
1
1
0
1
0
0
0
1
1
1
Protected - PPB and DYB are
changeable
Protected - PPB not changeable,
DYB is changeable
The PPB Lock bit adds an additional level of protection.
Once all PPBs are programmed to the desired settings, the
PPB Lock may be set to “1”. Setting the PPB Lock disables
all program and erase commands to the non-volatile PPBs.
In effect, the PPB Lock Bit locks the PPBs into their current
state. The only way to clear the PPB Lock is to go through
a power cycle. System boot code can determine if any
changes to the PPB are needed; for example, to allow new
system code to be downloaded. If no changes are needed
then the boot code can set the PPB Lock to disable any
further changes to the PPBs during system operation.
Table 8 contains all possible combinations of the DYB, PPB,
and PPB lock relating to the status of the sector
In summary, if the PPB is set, and the PPB lock is set, the
sector is protected and the protection can not be removed
until the next power cycle clears the PPB lock. If the PPB is
cleared, the sector can be dynamically locked or unlocked.
The DYB then controls whether or not the sector is protected
or unprotected.
The WP#/ACC write protect pin adds a final level of
hardware protection to sectors 0, 1, 268, and 269. When
this pin is low it is not possible to change the contents of
these sectors. These sectors generally hold system boot
code. The WP#/ACC pin can prevent any changes to the
boot code that could override the choices made while setting
up sector protection during system initialization.
If the user attempts to program or erase a protected sector,
the device ignores the command and returns to read mode.
A program command to a protected sector enables status
polling for approximately 1 µs beforethe device returns to
read mode without having modified the contents of the
protected sector. An erase command to a protected sector
enables status polling for approximately 50 µs after which
the device returns to read mode without having erased the
protected sector.
It is possible to have sectors that have been persistently
locked, and sectors that are left in the dynamic state. The
sectors in the dynamic state are all unprotected. If there
is a need to protect some of them, a simple DYB Write
command sequence is all that is necessary. The DYB write
command for the dynamic sectors switch the DYBs to signify
protected and unprotected, respectively. If there is a need to
change the status of the persistently locked sectors, a few
more steps are required. First, the PPB Lock bit must be
disabled by either putting the device through a power-cycle,
or hardware reset. The PPBs can then be changed to reflect
the desired settings. Setting the PPB lock bit once again will
lock the PPBs, and the device operates normally again.
The programming of the DYB, PPB, and PPB lock for a
given sect or can be ver i f ied by writing a DYB/PPB/PPB
lock verify command to the device.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector
Protection mode locking bit exists to guarantee that the
device remain in software sector protection. Once set,
the Persistent Sector Protection locking bit prevents
programming of the password protection mode locking bit.
This guarantees that a hacker could not place the device
in password protection mode.
The best protection is achieved by executing the PPB lock
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Both of these objectives are important, and if not carefully
considered, may lead to unrecoverable errors. The user
must be sure that the Password Protection method is
desired when setting the Password Mode Locking Bit. More
importantly, the user must be sure that the password is
correct when the Password Mode Locking Bit is set. Due to
the fact that read operations are disabled, there is no means
to verify what the password is afterwards. If the password
is lost after setting the Password Mode Locking Bit, there
will be no way to clear the PPB Lock bit.
PASSWORD PROTECTION MODE
The Password Sector Protection Mode method allows an
even higher level of security than the Persistent Sector
Protection Mode. There are two main differences between
the Persistent Sector Protection and the Password Sector
Protection Mode:
ꢀ
When the device is first powered on, or comes out
of a reset cycle, the PPB Lock bit set to the locked
state, rather than cleared to the unlocked state.
ꢀ
The only means to clear the PPB Lock bit is by
writing a unique 64-bit Password to the device.
The Password Mode Locking Bit, once set, prevents reading
the 64-bit password on the DQ bus and further password
programming. The Password Mode Locking Bit is not
erasable. Once Password Mode Locking Bit is programmed,
the Persistent Sector Protection Locking Bit is disabled
from programming, guaranteeing that no changes to the
protection scheme are allowed.
The Password Sector Protection method is otherwise
identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in this
method.
Once the Password Mode Locking Bit is set, the password
is permanently set with no means to read, program, or erase
it. The password is used to clear the PPB Lock bit. The
Password Unlock command must be written to the flash,
along with a password. The flash device internally compares
the given password with the pre-programmed password.
If they match, the PPB Lock bit is cleared, and the PPBs
can be altered. If they do not match, the flash device does
nothing. There is a built-in 2 µs delay for each “password
check.” This delay is intended to thwart any efforts to run
a program that tries all possible combinations in order to
crack the password.
64-bit Password
The 64-bit Password is located in its own memory space and
is accessible through the use of the Password Program and
Verify commands (see “Password Verify Command”). The
password function works in conjunction with the Password
Mode Locking Bit, which when set, prevents the Password
Verify command from reading the contents of the password
on the pins of the device.
WRITE PROTECT (WP#)
The Write Protect feature provides a hardware method of
protecting sectors 0, 1, 268, and 269 without using VID.
This function is provided by the WP# pin and overrides
the previously discussed High Voltage Sector Protection
method.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme,
the customer must first program the password. The
password may be correlated to the unique Electronic
Serial Number (ESN) of the particular flash device. Each
ESN is different for every flash device; therefore each
password should be different for every flash device. While
programming in the password region, the customer may
perform Password Verify operations.
If the system asserts VIL on the WP#/ACC pin, the device
disables program and erase functions in the two outermost
4 Kword sectors on both ends of the flash array independent
of whether it was previously protected or unprotected.
If the system asserts VIH on the WP#/ACC pin, the device
reverts to whether sectors 0, 1, 268, and 269 were last set
to be protected or unprotected. That is, sector protection
or unprotection for these sectors depends on whether
they were last protected or unprotected using the method
described in High Voltage Sector Protection.
Once the desired password is programmed in, the customer
must then set the Password Mode Locking Bit. This
operation achieves two objectives:
1. Permanently sets the device to operate using the
Password Protection Mode. It is not possible to reverse
this function.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
2. Disables all further commands to the password region.
All program, and read operations are ignored.
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Persistent Protection Bit Lock
HIGH VOLTAGE SECTOR PROTECTION
The Persistent Protection Bit (PPB) Lock is a volatile bit that
reflects the state of the Password Mode Locking Bit after
power-up reset. If the Password Mode Lock Bit is also set
after a hardware reset (RESET# asserted) or a power-up
reset, the ONLY means for clearing the PPB Lock Bit in
Password Protection Mode is to issue the Password Unlock
command. Successful execution of the Password Unlock
command clears the PPB Lock Bit, allowing for sector PPBs
modifications.Asserting RESET#, taking the device through
a power-on reset, or issuing the PPB Lock Bit Set command
sets the PPB Lock Bit to a “1” when the Password Mode
Lock Bit is not set.
Sector protection and unprotection may also be implemented
using programming equipment. The procedure requires
high voltage (VID) to be placed on the RESET# pin. Refer
to Figure 2 for details on this procedure. Note that for sector
unprotect, all unprotected sectors must first be protected
prior to the first sector write cycle.
If the Password Mode Locking Bit is not set, including
Persistent Protection Mode, the PPB Lock Bit is cleared
after power-up or hardware reset. The PPB Lock Bit is set
by issuing the PPB Lock Bit Set command. Once set the only
means for clearing the PPB Lock Bit is by issuing a hardware
or power-up reset. The Password Unlock command is
ignored in Persistent Protection Mode.
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FIGURE 2. IN-SYSTEM SECTOR PROTECTION/SECTOR UNPROTECTION ALGORITHMS
START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = V ID
RESET# = V ID
Wait 4 µs
Wait 4 µs
unprotect address
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A7-A0 =
Yes
Set up first sector
address
00000010
Sector Unprotect:
Write 60h to sector
address with
A7-A0 =
Wait 100 µs
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
01000010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 1.2 ms
00000010
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
Read from
sector address
with A7-A0 =
00000010
Increment
PLSCNT
No
00000010
No
PLSCNT
= 25?
Read from
sector address
with A7-A0 =
00000010
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
Remove V ID
from RESET#
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Write reset
command
No
Yes
Remove V ID
from RESET#
Remove V ID
from RESET#
No
Last sector
verified?
Sector Protect
complete
Write reset
command
Yes
Write reset
command
Remove V ID
from RESET#
Device failed
Sector Protect
complete
Sector Unprotect
complete
Write reset
command
Sector Protect
Algorithm
Device failed
Sector Unprotect
complete
Sector Unprotect
Algorithm
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SecSi sector is divided into 64 factory-lockable words that
can be programmed and locked by the user. The SecSi
sector is located at addresses 000000h-00007Fh in both
Persistent Protection mode and Password Protection mode.
It uses indicator bits (DQ6, DQ7) to indicate the factory-
locked and user-locked status of the part.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to
VID. During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET# pin, all the previously
protected sectors are protected again. Figure 3 shows the
algorithm, and Figure 24 shows the timing diagrams, for
this feature. While PPB lock is set, the device cannot enter
the Temporary Sector Unprotection Mode.
The system accesses the SecSi Sector through a command
sequence (see “Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence”). After the sysem has written the
Enter SecSi Sector command sequence, it may read the
SecSi Sector by using the addresses normally occupied by
the boot sectors. This mode of operation continues until the
system issues the Exit SecSi Sector command sequence,
or until power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending
commands to the normal address space. Note that theACC
function and unlock bypass modes are not available when
the SecSi Sector is enabled.
FIGURE 3. TEMPORARY SECTOR UNPROTECT
OPERATION
START
Factory-Locked Area (64 words)
The factory-locked area of the SecSi Sector (000000h-
00003Fh) is locked when the part is shipped, whether or
not the area was programmed at the factory. The SecSi
Sector Factory-locked Indicator Bit (DQ7) is permanently
set to a “1”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
User-Lockable Area (64 words)
The user-lockable area of the SecSi Sector (000040h-
00007Eh) is shipped unprotected, which allows the user
to program and optionally lock the area as appropriate for
the application. The SecSi Sector User-locked Indicator Bit
(DQ6) is shipped as “0” and can be permanently locked to
“1” by issuing the SecSi Protection Bit Program Command.
The SecSi Sector can be read any number of times, but
can be programmed and locked only once. Note that
the accelerated programming (ACC) and unlock bypass
functions are not available when programming the SecSi
Sector.
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 268, 269 will
remain protected).
2. All previously protected sectors are protected once again
The User-lockable SecSi Sector area can be protected using
one of the following procedures:
ꢀ
Follow the SecSi Sector protection Agorithm as
shown in Figure 4. This allows in-system protection
of the SecSi Sector without raising any device pin
to a high voltage. Note that this method is only
appliacable to the SecSi Sector.
SecSi™ (SECURED SILICON) SECTOR
FLASH MEMORY REGION
The SecSi (Secured Silicon) Sector feature provides a Flash
memory region that enables permanent part identification
through an Electronic Serial Number (ESN) The 128-word
ꢀ
To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 5.
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FIGURE 4. SECSI SECTOR PROTECTION ALGORITHM
START
SecSiTM Sector Entry
Write AAh to address 555h
Write 55h to address 2AAh
Write 88h to a address 555h
SecSi Sector Entry
SecSi Sector
Protection Entry
Write AAh to address 555h
Write 55h to address 2AAh
Write 60h to a address 555h
PLSCNT = 1
Protect SecSi Sector:
write 68h to sector address
with A7-A0 = 00011010
Time out 256 µs
SecSi Sector Protection
Verify SecSi Sector:
write 48h to sector address
with A7-A0 = 00011010
Increment PLSCNT
Read from sector address
with A7-A0 = 00011010
No
No
PLSCNT = 25?
Data = 01h?
Yes
Yes
SecSi Sector
Protection Completed
Device Failed
SecSi Sector Exit
Write 555h/AAh
Write 2AAh/55Ah
Write SA0+555h/90h
Write XXXh/00h
SecSi Sector Exit
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Once the SecSi Sector is locked and verified, the system
must write the Exit SecSi Sector Region command
sequence to return to reading and writing the remainder
of the array.
program/erase circuits are disabled, and the device resets
to the read mode. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO
.
The SecSi Sector lock must be used with caution since,
once locked, there is no procedure available for unlocking
the SecSi Sector area and none of the bits in the SecSi
Sector memory space can be modified in any way.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CS#, or
WE# do not initiate a write cycle.
FIGURE 5. SecSi SECTOR PROTECT VERIFY
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL,
CS# = VIH or WE# = VIH. To initiate a write cycle, CS# and
WE# must be a logical zero while OE# is a logical one.
START
If data = 00h,
RESET# =
SecSi Sector is
VIH or VID
Power-Up Write Inhibit
unprotected.
If WE# = CS# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset to
the read mode on power-up.
If data = 01h,
SecSi Sector is
protected.
Wait 1 µs
Write 60h to
any address
Remove VIH or VID
from RESET#
COMMON FLASH MEMORY
INTERFACE (CFI)
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms
to be used for entire families of devices. Software support
can then be device-independent, JEDEC ID-independent,
and forward- and backward-compatible for the specified
flash device families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
A1 = 1, A0 = 0
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h, any
time the device is ready to read array data. The system
can read CFI information at the addresses given in Tables
9–12. To terminate reading CFI data, the system must write
the reset command. The CFI Query mode is not accessible
when the device is executing an Embedded Program or
embedded Erase algorithm.
SecSi Sector Protection Bits
The SecSi Sector Protection Bits prevent programming of
the SecSi Sector memory area. Once set, the SecSi Sector
memory area contents are non-modifiable.
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
The system can also write the CFI query command when
the device is in the autoselect mode. The device enters the
CFI query mode, and the system can read CFI data at the
addresses given in Tables 9–12. The system must write the
reset command to return the device to reading array data.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
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TABLE 9. CFI QUERY IDENTIFICATION STRING
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string "QRY"
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00H = none exists)
TABLE 10. SYSTEM INTERFACE STRING
Addresses
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
0009h
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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TABLE 11. DEVICE GEOMETRY DEFINITION
Addresses
Data
0018h
Description
Device Size = 2N byte
27h
28h
0001h
Flash Device Interface description
29h
0000h
2Ah
2Bh
0000h
0000h
Max. munber of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Region within device
Erase Block Region 1 Information
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
00FDh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
0000h
0000h
0000h
0000h
Erase Block Region 2 information
Erase Block Region 3 Information
Erase Block Region 4 Information
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TABLE 12. PRIMARY VENDOR-SPECIFIC EXTENDED QUERY
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII String "PRI"
43h
44h
45h
0031h
0033h
000Ch
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
0002h
0001h
0001h
0007h
00E7h
0000h
0002h
0085h
0095h
0001h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device, 02h = Bottom Boot Device, 03 = Top Boot Device, 04h = Both Top and
Bottom
50h
57h
58h
59h
5Ah
5Bh
0001h
0004h
0027h
0060h
0060h
0027h
Program Suspend
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
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ignores reset commands until the operation is complete.
COMMAND DEFINITIONS
The reset command may be written between the sequence
cyclesinaprogramcommandsequencebeforeprogramming
begins. This resets the bank to which the system was writing
to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing
the reset command returns that bank to the erase-suspend-
read mode. Once programming begins, however, the device
ignores reset commands until the operation is complete.
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
13 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state.Areset command is then required to return the device
to reading array data.
All addresses are latched on the falling edge of WE# or CS#,
whichever happens later. All data is latched on the rising
edge of WE# or CS#, whichever happens first. Refer to the
AC Characteristic section for timing diagrams.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to the read mode. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read
mode.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. Each bank is ready to read array data after completing
an Embedded Program or Embedded Erase algorithm.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the read
mode (or erase-suspend-read mode if that bank was in
Erase Suspend).
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend- read mode,
after which the system can read data from any non-erase-
suspended sector within the same bank. The system can
read array data using the standard read timing, except that
if it reads at an address within erase-suspended sectors, the
device outputs status data.After completing a programming
operation in the Erase Suspend mode, the system may
once again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands section for
more information.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes, and
determine whether or not a sector is protected.
The autoselect command sequence may be written to an
address within a bank that is either in the read or erase-
suspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing
in the other bank. The autoselect command sequence is
initiated by first writing two unlock cycles. This is followed
by a third write cycle that contains the bank address and the
autoselect command. The bank then enters the autoselect
mode. The system may read any number of autoselect
codes without reinitiating the command sequence.
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if DQ5 goes
high during an active program or erase operation, or if the
bank is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information. The
AC Characteristic table provides the read parameters, and
Figure 11 shows the timing diagram.
Table 13 shows the address and data requirements. To
determine sector protection information, the system must
write to the appropriate bank address (BA) and sector
address (SA). Table 4 shows the address range and bank
number associated with each sector.
Reset Command
Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don’t cares
for this command.
The system must write the reset command to return to the
read mode (or erase-suspend-read mode if the bank was
previously in Erase Suspend).
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to the read mode. Once erasure begins, however, the device
Enter SecSi™ Sector/Exit SecSi Sector Command
Sequence
The SecSi Sector region provides a secured data area
containing a random, eight word electronic serial number
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(ESN). The system can access the SecSi Sector region
by issuing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to normal
operation. The SecSi Sector is not accessible when the
device is executing an Embedded Program or embedded
Erase algorithm. Table 13 shows the address and data
requirements for both command sequences. See also
“SecSi™ (Secured Silicon) Sector Flash Memory Region”
for further information. Note that the ACC function and
unlock bypass modes are not available when the SecSi
Sector is enabled.
data to a bank faster than using the standard program
command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. That bank then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode.
The first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed
in the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
13 shows the requirements for the command sequence.
Word Program Command Sequence
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue
the two-cycle unlock bypass reset command sequence.
(See Table 14)
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system
is not required to provide further controls or timings. The
device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 13
shows the address and data requirements for the program
command sequence. Note that the SecSi Sector, autoselect,
and CFI functions are unavailable when a [program/erase]
operation is in progress.
The device offers accelerated program operations through
the WP#/ACC pin. When the system asserts VHH on the
WP# ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the WP#/ACC pin to accelerate
the operation. Note that the WP#/ACC pin must not be at
VHH any operation other than accelerated programming,
or device damage may result. In addition, the WP#/ACC
pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
When the Embedded Program algorithm is complete, that
bank then returns to the read mode and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ7, DQ6, or RY/BY#. Refer
to the Write Operation Status section for information on
these status bits.
Figure 6 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in theAC
Characteristics section for parameters, and Figure 16 for
timing diagrams.
Any commands written to the device during the Embedded
ProgramAlgorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back
to a “1.” Attempting to do so may cause that bank to set
DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read
will show that the data is still “0.” Only erase operations can
convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
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is in progress. However, note that a hardware reset
immediately terminates the erase operation. If that occurs,
the chip erase command sequence should be reinitiated
once that bank has returned to reading array data, to ensure
data integrity.
FIGURE 6. PROGRAM OPERATION
START
Figure 7 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the
AC Characteristics section for parameters, and Figure 17
section for timing diagrams.
Write Program
Command Sequence
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
13 shows the address and data requirements for the sector
erase command sequence.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
Yes
No
Increment Address
Last Address?
Yes
After the command sequence is written, a sector erase time-
out of 50 µs occurs. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50 µs, otherwise erasure may begin.Any sector
erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to ensure
all commands are accepted. The interrupts can be re-
enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend
during the time-out period resets that bank to the read
mode. The system must rewrite the command sequence
and any additional addresses and commands. Note that
SecSi Sector, autoselect, and CFI functions are unavailable
when a [program/erase] operation is in progress.
Programming
Completed
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
Table 13 shows the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no longer
latched. The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
the Write Operation Status section for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out (See the section on DQ3: Sector
Erase Timer). The time-out begins from the rising edge of
the final WE# pulse in the command sequence.
Any commands written during the chip erase operation
are ignored. Note that SecSi Sector, autoselect, and CFI
functions are unavailable when a [program/erase] operation
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
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latched. Note that while the Embedded Erase operation is
in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading DQ7, DQ6, DQ2, or RY/BY# in the
erasing bank. Refer to the Write Operation Status section
for information on these status bits.
ERASE SUSPEND/ERASE RESUME
COMMANDS
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from,
or program data to, any sector not selected for erasure. The
bank address is required when writing this command. This
command is valid only during the sector erase operation,
including the 80 µs time-out period during the sector erase
command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the sector
erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data
integrity.
The Erase Suspend command is ignored if written during the
chip erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of
20 µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation. Addresses are
“don’t-cares” when writing the Erase suspend command.
Figure 7 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the
AC Characteristics section for parameters, and Figure 17
section for timing diagrams.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can
read data from or program data to any sector not selected
for erasure. (The device “erase suspends” all sectors
selected for erasure.) Reading at any address within
erase-suspended sectors produces status information on
DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is
erase-suspended. Refer to the Write Operation Status
section for information on these status bits.
FIGURE 7. ERASE OPERATION
START
Write Erase
Command Sequence
(Notes 1, 2)
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the DQ7 or DQ6 status bits, just as in the standard
Word Program operation. Refer to the Write Operation
Status section for more information.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. The device allows
reading autoselect codes even at addresses within erasing
sectors, since the codes are not stored in the memory array.
When the device exits the autoselect mode, the device
reverts to the Erase Suspend mode, and is ready for another
valid operation. Refer to theAutoselect Mode andAutoselect
Command Sequence sections for details.
No
Data = FFh?
Yes
Erasure Completed
To resume the sector erase operation, the system must write
the Erase Resume command (address bits are don’t care).
The bank address of the erase-suspended bank is required
when writing this command. Further writes of the Resume
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
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command are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
PASSWORD PROTECTION MODE
LOCKING BIT PROGRAM COMMAND
The Password Protection Mode Locking Bit Program
Command programs the Password Protection Mode
Locking Bit, which prevents further verifies or updates to
the Password. Once programmed, the Password Protection
Mode Locking Bit cannot be erased! If the password
Protection Mode Locking Bit is verified as program without
margin, the Password Protection Mode Locking Bit Program
command can be executed to improve the program
margin. Once the Password Protection Mode Locking Bit is
programmed, the Persistent Sector Protection Locking Bit
program circuitry is disabled, thereby forcing the device to
remain in the Password Protection mode. Exiting the Mode
Locking Bit Program command is accomplished by writing
the Read/Reset command.
PASSWORD PROGRAM COMMAND
The Password Program Command permits programming
the password that is used as part of the hardware protection
scheme. The actual password is 64-bits long. Four Password
Program commands are required to program the password.
The system must enter the unlock cycle, password program
command (38h) and the program address/data for each
portion of the password when programming. There are
no provisions for entering the 2-cycle unlock cycle, the
password program command, and all the password
data. There is no special addressing order required for
programming the password. Also, when the password
is undergoing programming, Simultaneous Operation is
disabled. Read operations to any memory location will
return the programming status. Once programming is
complete, the user must issue a Read/Reset command to
return the device to normal operation. Once the Password
is written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Password
Program Command is only capable of programming “0”s.
Programming a “1” after a cell is programmed as a “0” results
in a time-out by the Embedded Program Algorithm™ with
the cell remaining as a “0”. The password is all ones when
shipped from the factory. All 64-bit password combinations
are valid as a password.
PERSISTENT SECTOR PROTECTION
MODE LOCKING BIT PROGRAM
COMMAND
The Persistent Sector Protection Mode Locking Bit Program
Command programs the Persistent Sector Protection Mode
Locking Bit, which prevents the Password Mode Locking
Bit from ever being programmed. If the Persistent Sector
Protection Mode Locking Bit is verified as programmed
without margin, the Persistent Sector Protection Mode
Locking Bit Program Command should be reissued to
improve program margin. By disabling the program circuitry
of the Password Mode Locking Bit, the device is forced to
remain in the Persistent Sector Protection mode of operation,
once this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by writing
the Read/Reset command.
PASSWORD VERIFY COMMAND
The Password Verify Command is used to verify the
Password. The Password is verifiable only when the
Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user
attempts to verify the Password, the device will always drive
all F’s onto the DQ data bus.
SecSi SECTOR PROTECTION BIT
PROGRAM COMMAND
The SecSi Sector Protection Bit Program Command
programs the SecSi Sector Protection Bit, which prevents
the SecSi sector memory from being cleared. If the SecSi
Sector Protection Bit is verified as programmed without
margin, the SecSi Sector Protection Bit Program Command
should be reissued to improve program margin. Exiting the
The Password Verify command is permitted if the SecSi
sector is enabled. Also, the device will not operate in
Simultaneous Operation when the Password Verify
command is executed. Only the password is returned
regardless of the bank address. The lower two address bits
(A1-A0) are valid during the Password Verify. Writing the
Read/Reset command returns the device back to normal
operation.
V
CC-level SecSi Sector Protection Bit Program Command is
accomplished by writing the Read/Reset command.
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PPB LOCK BIT SET COMMAND
PPB PROGRAM COMMAND
The PPB Lock Bit Set command is used to set the PPB
Lock bit if it is cleared either at reset or if the Password
Unlock command was successfully executed. There is no
PPB Lock Bit Clear command.
The PPB Program command is used to program, or set,
a given PPB. Each PPB is individually programmed (but
is bulk erased with the other PPBs). The specific sector
address (A22–A12) are written at the same time as the
program command 60h with A6 = 0. If the PPB Lock Bit is
set and the corresponding PPB is set for the sector, the PPB
Program command will not execute and the command will
time-out without programming the PPB.
Once the PPB Lock Bit is set, it cannot be cleared unless the
device is taken through a power-on clear or the Password
Unlock command is executed. Upon setting the PPB Lock
Bit, the PPBs are latched into the DYBs. If the Password
Mode Locking Bit is set, the PPB Lock Bit status is reflected
as set, even after a power-on reset cycle. Exiting the PPB
Lock Bit Set command is accomplished by writing the Read/
Reset command (only in the Persistent Protection Mode).
After programming a PPB, two additional cycles are needed
to determine whether the PPB has been programmed with
margin. If the PPB has been programmed without margin,
the program command should be reissued to improve the
program margin. Also note that the total number of PPB
program/erase cycles is limited to 100 cycles. Cycling the
PPBs beyond 100 cycles is not guaranteed.
DYB WRITE COMMAND
The DYB Write command is used to set or clear a DYB for
a given sector. The high order address bits
The PPB Program command does not follow the Embedded
Program algorithm.
(A22–A12) are issued at the same time as the code 01h or
00h on DQ7-DQ0. All other DQ data bus pins are ignored
during the data write cycle. The DYBs are modifiable at
any time, regardless of the state of the PPB or PPB Lock
Bit. The DYBs are cleared at power-up or hardware reset.
Exiting the DYB Write command is accomplished by writing
the Read/Reset command.
ALL PPB ERASE COMMAND
The All PPB Erase command is used to erase all PPBs in
bulk. There is no means for individually erasing a specific
PPB. Unlike the PPB program, no specific sector address
is required. However, when the PPB erase command
is written all Sector PPBs are erased in parallel. If the
PPB Lock Bit is set the ALL PPB Erase command will not
execute and the command will time-out without erasing the
PPBs. After erasing the PPBs, two additional cycles are
needed to determine whether the PPB has been erased
with margin. If the PPBs has been erased without margin,
the erase command should be reissued to improve the
program margin.
PASSWORD UNLOCK COMMAND
The Password Unlock command is used to clear the PPB
Lock Bit so that the PPBs can be unlocked for modification,
thereby allowing the PPBs to become accessible for
modification. The exact password must be entered in order
for the unlocking function to occur. This command cannot
be issued any faster than 2 µs at a time to prevent a hacker
from running through all 64-bit combinations in an attempt
to correctly match a password. If the command is issued
before the 2 µs execution window for each portion of the
unlock, the command will be ignored.
It is the responsibility of the user to preprogram all PPBs
prior to issuing the All PPB Erase command. If the user
attempts to erase a cleared PPB, over-erasure may occur
making it difficult to program the PPB at a later time. Also
note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles
is not guaranteed.
Once the Password Unlock command is entered, the
RY/BY# indicates that the device is busy. Approximately 1
µs is required for each portion of the unlock. Once the first
portion of the password unlock completes (RY/BY# is not
low or DQ6 does not toggle when read), the next part of the
password is written. The system must thus monitor RY/BY#
or the status bits to confirm when to write the next portion
of the password. Seven cycles are required to successfully
clear the PPB Lock Bit.
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DYB WRITE COMMAND
PPB STATUS COMMAND
The DYB Write command is used for setting the DYB, which
is a volatile bit that is cleared at reset. There is one DYB per
sector. If the PPB is set, the sector is protected regardless
of the value of the DYB. If the PPB is cleared, setting the
DYB to a 1 protects the sector from programs or erases.
Since this is a volatile bit, removing power or resetting the
device will clear the DYBs. The bank address is latched
when the command is written.
The programming of the PPB for a given sector can be
verified by writing a PPB status verify command to the
device.
PPB LOCK BIT STATUS COMMAND
The programming of the PPB Lock Bit for a given sector can
be verified by writing a PPB Lock Bit status verify command
to the device.
PPB LOCK BIT SET COMMAND
SECTOR PROTECTION STATUS
COMMAND
The PPB Lock Bit set command is used for setting the DYB,
which is a volatile bit that is cleared at reset. There is one
DYB per sector. If the PPB is set, the sector is protected
regardless of the value of the DYB. If the PPB is cleared,
setting the DYB to a 1 protects the sector from programs
or erases. Since this is a volatile bit, removing power or
resetting the device will clear the DYBs. The bank address
is latched when the command is written.
The programming of either the PPB or DYB for a given
sector or sector group can be verified by writing a Sector
Protection Status command to the device.
Note that there is no single command to independently
verify the programming of a DYB for a given sector group.
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COMMAND DEFINITIONS TABLES
TABLE 13. MEMORY ARRAY COMMAND DEFINITIONS
Command (Notes)
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data
RA RD
XXX F0
Addr
Data
Addr
Data
20
Addr
Data
00
Read (5)
Reset (6)
Autoselect Manufacturer ID
(Note 7)
1
1
4
6
4
555
555
555
AA 2AA
AA 2AA
AA 2AA
55
55
55
555
555
555
90
90
90
(BA)X00
(BA)X0
X03
04
7E
Device ID (10)
SecSi Sector
Factory Protect (8)
(BA)X0E
(BA)X0F
(see note
8)
Sector Group
Protect Verify (9)
4
555 AAA 2AA
55
555
90
(SA)X02
XX00/
XX01
Program
Chip Erase
Sector Erase
4
6
6
1
1
1
2
3
2
2
1
2
555
555
555
BA
BA
55
XX
555
XX
XX
XX
AA 2AA
AA 2AA
AA 2AA
B0
30
98
55
55
55
555
555
555
A0
80
80
PA
555
555
PD
AA
AA
2AA
2AA
55
55
555
SA
10
30
Program/Erase Suspend (11)
Program/Erase Resume (12)
CFI Query (13)
Accelerated Program (15)
Unlock Bypass Entry (15)
Unlock Bypass Program (15)
Unlock Bypass Erase (15)
Unlock Bypass CFI (13, 15)
Unlock Bypass Reset (15)
A0
PA
PD
55
PD
10
AA 2AA
555
20
A0
80
98
PA
XX
XXX 90
XXX
00
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or erase
operation. Determined by A22:A20, see Tables 4 and for more detail.
PA = Program Address (A22:A0). Addresses latch on falling edge of
WE# or CS# pulse, whichever happens later.
RA = Read Address (A22:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A22:A12) for verifying (in autoselect mode) or erasing.
WD = Write Data. See “Configuration Register” definition for specific write data. Data
latched on rising edge of WE#.
X = Don’t care
PD = Program Data (DQ15:DQ0) for each chip written to location PA. Data latches
on rising edge of WE# or CS# pulse, whichever happens first.
Notes:
9. The data is 00h for an unprotected sector group and 01h for a protected sector
group.
10. Device ID must be read across cycles 4, 5, and 6.
11. System may read and program in non-erasing sectors, or enter autoselect
mode, when in Program/Erase Suspend mode. Program/Erase Suspend
command is valid only during a sector erase operation, and requires bank
address.
12. Program/Erase Resume command is valid only during Erase
Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or when device is In
autoselect mode.
14. WP#/ACC must be at VID during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock Bypass
operation. Unlock Bypass Reset command is required to return to the reading
array.
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as
shown in table, address bits higher than A11 (except where BA is required) and data
bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to reading array (or to erase-suspend-read
mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5
goes high (while bank is providing status information).
7. Fourth cycle of autoselect command sequence is a read cycle. System must provide
bank address to obtain manufacturer ID or device ID information. See Autoselect
Command Sequence section for more information.
8. The data is C0h for factory and customer locked and 80h for factory locked.
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TABLE 14. SECTOR PROTECTION COMMAND DEFINITIONS
Command (Notes)
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection
Bit Program (5, 6)
1
3
4
6
XXX
555
555
555
F0
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
88
90
60
XX
OW
00
68
OW
OW
48
OW
RD (0)
Sector Protection
Bit Status
Password
Program (5, 7, 8)
Password Verify
(6, 8, 9)
Password Unlock
(7, 10, 11)
PPB Program
(5, 6, 12)
5
4
4
7
6
555
555
555
555
555
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
555
555
555
555
555
60
38
C8
28
60
OW
48
RD(0)
XX[0-3]
PD[0-3]
PWA[0-3] PWD[0-3]
PWA[0]
(SA)WP
PWD[0]
68
PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]
(SA)WP
48
(SA)WP
RD(0)
PPB Status
All PPB Erase
(5, 6, 13, 14)
4
6
555
555
AA
AA
2AA
2AA
55
55
555
555
90
60
(SA)WP
WP
RD(0)
60
(SA)
40
(SA)WP
RD(0)
PPB Lock Bit Set
PPB Lock Bit
Status (15)
3
4
555
555
AA
AA
2AA
2AA
55
55
555
555
78
58
SA
RD(1)
DYB Write (7)
DYB Erase (7)
DYB Status (6)
PPMLB Program
(5, 6, 12)
4
4
4
6
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
48
48
58
60
SA
SA
SA
PL
X1
X0
48
68
PL
48
PL
SL
RD(0)
RD(0)
PPMLB Status (5)
SPMLB Program
(5, 6, 12)
5
6
555
555
AA
AA
2AA
2AA
55
55
555
555
60
60
PL
SL
48
68
PL
SL
RD(0)
48
SPMLB Status (5)
5
555
AA
2AA
55
555
60
SL
48
SL
RD(0)
Legend:
DYB = Dynamic Protection Bit
RD(1) = Read Data DQ1 for PPB Lock status.
OW = Address (A7:A0) is (00011010)
SA = Sector Address where security command applies. Address bits
A22:A12 uniquely select any sector.
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
X = Don’t care
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
shown in table, address bits higher than A11 (except where BA is required) and data
bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been
fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be
issued and verified again.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when
DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again.
Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
7. Data is latched on the rising edge of WE#.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
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Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data
on DQ7. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if
the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15–DQ0
may be still invalid. Valid data on DQ15–DQ0 will appear
on successive read cycles.
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 15 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation
is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in
progress or has been completed.
Table 15 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 19
in the AC Characteristic section shows the Data# Polling
timing diagram.
DQ7: DATA# POLLING
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is
in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
FIGURE 8. DATA# POLLING ALGORITHM
START
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to read
valid status information on DQ7. If a program address falls
within a protected sector, Data# Polling on DQ7 is active
for approximately 1 µs, then that bank returns to the read
mode.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The
system must provide an address within any of the sectors
selected for erasure to read valid status information on
DQ7.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7
is active for approximately 400 µs, then the bank returns
to the read mode. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads DQ7 at an address within a
protected sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
When the system detects DQ7 has changed from
the complement to true data, it can read valid data at
DQ15–DQ0 on the following read cycles. Just prior to the
completion of an Embedded Program or Erase operation,
DQ7 may change asynchronously with DQ15–DQ0 while
1. VA = Valid address for programming. During a sector erase operation, a valid address
is any sector address within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change
simultaneously with DQ5.
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and stops toggling once the Embedded Program algorithm
is complete.
RY/BY#: READY/BUSY#
The RY/BY# is a dedicated, open-drain output pin which
indicates whether an EmbeddedAlgorithm is in progress or
complete. The RY/BY# status is valid after the rising edge
of the final WE# pulse in the command sequence. Since
RY/BY# is an open-drain output, several RY/BY# pins can
Table 15 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between DQ2
and DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
be tied together in parallel with a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
in the read mode, the standby mode, or one of the banks is
in the erase-suspend- read mode.
FIGURE 9. TOGGLE BIT ALGORITHM
START
Table 15 shows the outputs for RY/BY#.
Read Byte
(DQ7–DQ0)
Address =VA
DQ6: TOGGLE BIT I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final WE# pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to
toggle. The system may use either OE# or CS# to control
the read cycles. When the operation is complete, DQ6
stops toggling.
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 400 µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
Read Byte Twice
(DQ7–DQ0)
Address = VA
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7: Data#
Polling).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit
may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2
for more information.
If a program address falls within a protected sector, DQ6
toggles for approximately 1 µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
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The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation (top of
Figure 9).
DQ2: TOGGLE BIT II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after
the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CS# to control the read
cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 15 to compare
outputs for DQ2 and DQ6.
DQ5: EXCEEDED TIMING LIMITS
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0”
back to a “1.” Under this condition, the device halts the
operation, and when the timing limit has been exceeded,
DQ5 produces a “1.”
Figure 9 shows the toggle bit algorithm in flowchart form, and
the section “DQ2: Toggle Bit II” explains the algorithm. See
also the DQ6: Toggle Bit I subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between DQ2 and DQ6 in graphical form.
Under both these conditions, the system must write the
reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).
READING TOGGLE BITS DQ6/DQ2
DQ3: SECTOR ERASE TIMER
Refer to Figure 9 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should
read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure that the device has accepted the command
sequence, and then read DQ3. If DQ3 is “1,” the Embedded
Erase algorithm has begun; all further commands (except
Erase Suspend) are ignored until the erase operation is
complete. If DQ3 is “0,” the device will accept additional
sector erase commands. To ensure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see
the section on DQ5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If
it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high.
Table 15 shows the status of DQ3 relative to the other
status bits.
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TABLE 15. WRITE OPERATION STATUS
Status
DQ7
(Note 2)
DQ7#
0
DQ6
DQ5
(Note 1)
DQ3
DQ2 (Note 2)
RY/BY#
Standard Mode Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
N/A
1
No Toggle
Toggle
0
0
Erase Suspend
Mode
Erase-Suspend-
Read
Erase
1
Not toggle
0
Data
0
N/A
Data
N/A
Toggle
Data
N/A
1
1
0
Suspended Sector
Non-Erase
Suspend Sector
Data
DQ7#
Data
Erase-Suspend-Program
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has
exceeded the maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the
appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address
where the Embedded Algorithm is in progress. The device outputs array data if the system
addresses a non-busy bank
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ABSOLUTE MAXIMUM RATINGS (1, 2)
CAPACITANCE
TA = +25°C, f = 1.0MHz
Parameter
Unit
°C
V
°C
cycles
Operating Temperature
Supply Voltage Range (VCC
-55 to +125
-0.5 to +4.0
Parameter
Symbol
CWE
CCS
CI/O
CAD
Max
11
Unit
pF
pF
pF
pF
pF
pF
pF
)
WE# capacitance
CS# capacitance
Data I/O capacitance
Address input capacitance
RESET# capacitance
RY/BY#
Storage Temperature Range
Endurance (write/erase cycles)
-55 to +125
1,000,000 min.
13
12
23
20
20
23
NOTES:
CRS
CRB
1. Stesses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5V.
During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to
–2.0V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9,
OE#, and RESET# is +12.5V which may overshoot to +14.0V for periods up to 20 ns.
Maximum DC input voltage on WP#/ACC is +9.5V which may overshoot to +12.0V
for periods up to 20 ns.
OE# capacitance
COE
This parameter is guaranteed by design but not tested.
RECOMMENDED OPERATING CONDITIONS
DATA RETENTION
Parameter
Supply Voltage
I/O Supply Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
VCC
VIO
TA
TA
Min
3.0
3.0
-55
-40
Max
3.6
3.6
+125
+85
Unit
V
V
°C
°C
Parameter
Pattern Data
Retention Time
Test Conditions
150°C
Min
10
20
Unit
Years
Years
125°C
Note: For all AC and DC specifications: VIO = VCC
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DC CHARACTERISTICS - CMOS COMPATABLE
VCC = 3.3V 0.3V. -55°C ≤ TA ≤ +125°C
Parameter Description
Input Load Current (Addresses)
Output Leakage Current
VCC Active Read Current (Notes 1, 2)
VCC Active Write Current (Notes 2, 3)
Symbol Test Conditions
Min
-2
-1
Max
2
1
60
50
75
75
90
90
0.8
VCC+0.3
9.5
12.5
0.4
Unit
µA
µA
mA
mA
µA
µA
mA
mA
V
V
V
V
V
V
V
ILI
ILO
VIN =VSS to VCC; VCC =VCC max
VOUT = VSS to VCC, OE# = VIH; VCC = VCC max
OE# = VIH, VCC = VCC max, f = 5 MHz (Note 1)
OE# = VIH, WE# =VIL
CS#, RESET#, WP/ACC# = VIO 0.3 V
VIH = VIO 0.3 V; VIL = VSS 0.3 V
OE# = VIH
lOC1
ICC2
lCC3
ICC5
ICC6
ICC7
VIL
VCC Standby Current (Note 2)
Automatic Sleep Mode (Notes 2, 4, 5)
VCC Active Read-While-Program Current (Notes 1, 2, 5)
VCC Active Read-While-Erase Current (Notes 1, 2, 5)
Input Low Voltage
OE# = VIH
VIO = 3.3V 0.3V
-0.5
2.0
8.5
Input High Voltage
VIH
VIO = 3.3V 0.3V
Voltage for ACC Program Acceleration
Voltage for Autoselect and Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
Low VCC Lock-Out Voltage (Note 5)
VHH
VID
VCC = 3.0 V 0.3V
Vcc = 3.0 V 0.3V
11.5
VOL
VOH
VLKO
IOL = 2.0 mA, VCC = VCC min, VIO = 3.3V 0.3V
IOH = -2.0 mA, VCC = VCC min, VIO = 3.3V 0.3V
2.4
2.3
2.5
Notes:
1. The lCC current listed is typically less than 5 mA/MHz, with OE# at VIH.
2. Maximum lCC specifications are tested with VCC = VCCMAX.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable
for tACC + 150 ns. Typical sleep mode current is 2 µA.
5. Not tested.
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AC TEST CONDITIONS
FIG 10:
AC TEST CIRCUIT
Parameter
Input Pulse Levels
Typ
Unit
V
IOL
VIL - 0, VIH = 2.5
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
5
1.5
1.5
ns
V
V
Current Source
VZ~ 1.5v
(Bipolar Supply)
D.U.T.
CEFF = 50 pf
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16 mA.
Tester Impedance Z0 = 50Ω.
VZ is typically the midpoint of VOH and VOL.
IOH
IOL & IOH are adjusted to similate a typical resistive load circuit.
ATE tester Includes jig capacitance.
Current Source
AC CHARACTERISTICS - READ-ONLY OPERATIONS
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-70
-90
-100
-120
Unit
Min Max
Min Max
Min Max
Min Max
Read Cycle Time (3)
Address Access Time
tAVAV
tAVQV
tELQV
tRC
tACC
tCE
tPACC
tOE
tDF
tDF
tOH
70
70
70
25
30
20
20
5
90
90
90
25
40
20
20
5
100
100
100
100
40
120
120
120
120
50
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select Access Time
Page Access Time
Output Enable to Output Valid
Chip Select High to Output High Z
Output Enable High to Output High Z
tOLQV
tEHQZ
tGHQZ
tAXQX
20
20
20
20
Output Hold from Addresses, CS# or OE#
Change, Whichever occurs first
5
5
Output Enable Hold
Time (1)
Read
Toggle and
Data# Polling
tOEH
0
10
0
10
0
10
0
10
1. Guaranteed by design, not tested.
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FIG 11: AC WAVEFORMS FOR READ OPERATIONS
tRC
Addresses
Addresses Stable
tACC
CS#
OE#
tRH
tDF
tOE
tOEH
tCE
WE#
tOH
High Z
High Z
Outputs
Output Valid
RESET#
RY/BY#
OV
FIG 12: PAGE READ OPERATION TIMINGS
Same Page
A22-A3
A2-A0
Aa
tACC
Ab
tPACC
Ac
tPACC
Ad
tPACC
Qc
Data
CS#
Qa
Qb
Qd
OE#
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AC CHARACTERISTICS - HARDWARE RESET (1)
Parameter
Symbol
Unit
Min
Max
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (1)
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (1)
tready
tready
20
µs
ns
500
RESET# Pulse Width
tRP
tRH
tRPD
tRB
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (1)
RESET# Low to Standby Mode (1)
RY/BY# Recovery Time
NOTE:
1. Not tested.
FIG. 13: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
RY/BY#
CS#, OE#
RESET#
tRH
tRP
tReady
FIG. 14: RESET TIMINGS DURING EMBEDDED ALGORITHMS
tReady
RY/BY#
tRB
CS#, OE#
RESET#
tRP
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AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-70
-90
-100
-120
Unit
Min Max
Min Max
Min Max
Min Max
Write Cycle Time (3)
Chip Select Setup Time (3)
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High (3)
tAVAV
tELWL
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWC
tCS
tWP
tAS
tDS
tDH
tAH
70
0
35
0
45
0
90
0
35
0
45
0
100
0
50
0
50
0
50
30
300
120
0
50
0
50
0
50
30
300
ns
ns
ns
ns
ns
ns
ns
ns
µs
45
20
300
45
30
300
tWPH
Duration of Byte Programming
Operation (1)
Sector Erase (2)
Read Recovery Time before Write (3)
tWHWH2
tGHWL
tVCS
5
5
5
5
sec
ns
µs
sec
ns
0
0
0
0
VCC Setup Time (3)
50
200
15
50
200
15
50
200
15
50
200
15
Chip Programming Time (4)
Address Setup Time to OE# low during
toggle bit polling
tASO
Write Recovery Time from RY/BY# (3)
Program/Erase Valid to RY/BY#
tRB
tBUSY
0
70
0
90
0
90
0
90
ns
ns
Notes:
1. Typical value for tWHWH1 is 6µs.
2. Typical value for tWHWH2 is 0.5 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 50 sec. The typical chip program time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
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FIG. 15: PROGRAM OPERATION
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CS#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3.
DOUT is the output of the data written to the device.
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FIG 16: ACCELETATED PROGRAM TIMING DIAGRAM
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
FIG 17: CHIP/SECTOR ERASE OPERATION TIMINGS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
2AAh
SA
VA
VA
555h for
chip erase
tAH
CS#
OE#
tCH
tWHWH2
tWP
WE#
Data
tWPH
tCS
tDS
tDH
30h
DOUT
55h
Status
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "write operation status")
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FIG 18: BACK TO BACK READ/WRITE CYCLE TIMINGS
tWC
Valid PA
tWC
Valid PA
tRC
tWC
Valid RA
Valid PA
tAS
Addresses
tAH
tAS
tCPH
tAH
tACC
tCS
CS#
OE#
tCP
tOE
tOEH
tGHWL
tWP
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CS# Controlled Write Cycles
FIG 19: DATA# POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
Addresses
VA
tACC
tCS
VA
VA
CS#
OE#
tCH
tOE
tOEH
tDF
tOH
WE#
DQ7
High Z
High Z
Valid Data
Complement
Complement
True
Status Data
True
Valid Data
Status Data
DQ6–DQ0
RY/BY#
tBUSY
NOTE: VA = Valid address. Illustration shows first status cycles after command sequence, last status read cycles, and array data read cycle.
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FIG 20: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tAHT
tAS
Addresses
CS#
tAHT
tASO
tCSPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Valid
Status
Valid
DQ6/DQ2
RY/BY#
Valid Data
Status
Status
(first read)
(second read)
(stops toggling)
FIG 21: DQ2 VS. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.
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FIG 22: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotec t
Verify
40h
Data
60h
60h
1 µs
CS#
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
WE#
OE#
NOTES:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
AC CHARACTERISTICS - ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS
Parameter
JEDEC
Description
Speed Options
Unit
Std
tWS
tAS
tAH
tDS
70
70
0
45
45
0
90
90
0
100
100
0
120
120
0
50
50
0
tVAVAV
tAVWL
tELAX
tDVEH
tEHDX
tGHEL
Write Cycle Time (1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
45
45
0
45
45
0
tDH
tGHEL
Read Recovery Time Before Write (OE# High
to WE# Low)
0
0
0
0
tWLEL
tEHWH
tELEH
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
CS# Pulse Width
CS# Pulse Width High
Programming Operation
Accelerated Programming Operation
Sector Erase Operation
Min
Min
Min
Min
Typ
Typ
Typ
0
0
35
30
6
0
0
35
30
6
0
0
45
30
6
0
0
50
30
6
ns
ns
ns
tEHEL
tCPH
ns
tWHWH1
tWHWH1
tWHWH2
tWHWH1
tWHWH1
tWHWH2
µs
µs
sec
4
0.5
4
0.5
4
0.5
4
0.5
NOTE:
1. Not tested.
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FIG 23: ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CS#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
NOTES:
1. Figure Indicated last two bus cycles of a program or erase operation.
2. PA = program address. SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
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TEMPORARY SECTOR UNPROTECT
Parameter
JEDEC
Description
Std
All Speed Options
Unit
tVIDR
tVHH
tRSP
tRRB
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector Unprotect
RESET# Hold Time from RY/BY# High for Temporary Sector
Unprotect
Min
Min
Min
Min
500
250
4
ns
ns
µs
µs
4
NOTE: Not tested.
FIG 24: TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
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PACKAGE: 159 PBGA (PLASTIC BALL GRID ARRAY)
BOTTOM VIEW
159 X Ø 0.762 (0.030) NOM
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.61 (0.024) NOM
2.34 (0.092) MAX
1.27 (0.050) NOM
11.43 (0.450) NOM
13.15 (0.518) MAX
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W 7 8M32 V XXX B X
White Eletronic Designs Corp.
Flash:
Organization, 8Mx32:
User configurable as 2 x 8M x 16
3.3V Power Supply:
Access Time (ns):
70 = 70ns
90 = 90ns
100 = 100ns
120 = 120ns
Package Type:
B = 159 PBGA, 13mm x 22mm
Devise Grade:
M = Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
I = Industrial
C = Commercial
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Document Title
8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operations Multi-Chip Package
Revision History
Rev #
Rev 0
History
Release Date Status
Initial Release
June 2004
Advanced
Rev 1
Changes (Pg. 1, 54)
October 2004
Preliminary
1.1 Change status to Preliminary
Rev 2
Changes (Pg. 1, 2,14, 34, 40, 41, 42, 43, 45, 46, 50, 52, 53, 54) December 2005
2.1 Change status to Final
Final
2.2 Add 70 ns speed grade
2.3 Correct ball A5 to VIO
2.4 Correct Manufacturer ID
2.5 Add Capacitance data
2.6 Add VIO to Recommended Operating Conditions
2.7 Change ILI to -2 to 2 µA.
2.8 Add Note 5 for ICC5-7 in DC Characteristics table
2.9 Remove ICC3 and ICC5 to 75 µA in DC Characteristics table
Rev 3
Changes (All pages)
April 2006
Final
3.1 Correct typo in DC Characteristics table VOH condition
VCC = VCCmin
3.2 AC test conditions tester impedance Zo = 50Ω
3.3 Correct typo in AC characteristics read-only operations
table tAVAQV to tAVQV and tCLQV to tOLQV
3.4 Change tPACC to 25 ns for 70 ns and 90 ns speed grades
3.5 Change tDS and tAH to 25ns for 70 ns speed grade, this was
typographical error.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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