WE32K32-120G1UQ [WEDC]
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 23.90 MM, CERAMIC, LQFP-68;
| 型号： | WE32K32-120G1UQ |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 23.90 MM, CERAMIC, LQFP-68 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE32K32-XXX
White Electronic Designs
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
■ Data Retention at 25°C, 10 Years
■ Write Endurance, 10,000 Cycles
■ Access Times of 80*, 90, 120, 150ns
■ MIL-STD-883 Compliant Devices Available
■ Packaging:
■ Organized as 32Kx32; User Configurable 64Kx16
or 128Kx8
68 lead, Hermetic CQFP (G2U), 122ꢀ4mm
(0ꢀ880") square, 3ꢀ56mm (0ꢀ140") height
(Package 510)ꢀ
■ Commercial, Industrial and Military Temperature
Ranges
68 lead, Hermetic CQFP (G1U)1, 23ꢀ9mm
(0ꢀ940") square, 3ꢀ56mm (0ꢀ140") high (Pack
age 519)
■ Automatic Page Write Operation
■ Page Write Cycle Time: 10ms Max
■ Data Polling for End of Write Detection
■ Hardware and Software Data Protection
■ TTL Compatible Inputs and Outputs
■ 5 Volt Power Supply
68 lead, Hermetic CQFP (G1T), 23ꢀ9mm
(0ꢀ940") square, 4ꢀ06mm (0ꢀ160"), (Package
524)
66-pin, PGA Type, 1ꢀ075" square, Hermetic
Ceramic HIP (Package 400)
■ Low Power CMOS, 10mA Standby Typical
■ Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation
*
80nsspeedisnotfullycharacterizedandissubjecttochangeor
cancellation without noticeꢀ
NOTE 1: Package not recommended for new design
FIGꢀ 1 PIN CONFIGURATION FOR WE32K32N-XH1X
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
I/O
8
9
WE
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
A0-14
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
I/O
CS2
CS
4
4
I/O10
GND
I/O11
WE
Output Enable
Power Supply
A
13
14
A
6
7
I/O27
VCC
A
A10
A11
A12
VCC
A
A
3
4
5
3
3
A0
A1
A2
GND
NC
Ground
NC
NC
NC
NC
NC
A
Not Connected
WE
1
A
8
9
A
BLOCK DIAGRAM
I/O
I/O
I/O
I/O
7
A
WE
CS
I/O23
I/O22
I/O21
I/O20
WE3 CS3
WE4 CS4
WE1 CS1
WE2 CS2
OE
I/O
I/O
I/O
0
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
A
0-14
1
2
5
4
GND
I/O19
32K x 8
32K x 8
32K x 8
32K x 8
3
11
22
33
44
55
66
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
1
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
October 2002 Revꢀ 3
WE32K32-XXX
White Electronic Designs
FIGꢀ 2 PIN CONFIGURATION FOR WE32K32-XG2UX, WE32K32-XG1UX1,
AND WE32K32-XG1TX
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-14
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
GND
NC
Not Connected
GND
I/O
8
9
I/O
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
BLOCK DIAGRAM
WE3 CS3
WE4 CS4
WE2 CS2
WE1 CS1
OE
A
0-14
32K x 8
32K x 8
32K x 8
32K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O8-15
I/O0-7
Note 1: Package not recommended for new design
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
2
WE32K32-XXX
White Electronic Designs
TRUTH TABLE
WE Mode
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
TA
Unit
°C
°C
V
CS
H
LL H
LH
X
OE
X
Data I/O
High Z
X
Read
Standby
Data
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE and A9
NOTE:
-55 to +125
-65 to +150
-0%6 to +6%25
-0%6 to +13%5
Out
In
TSTG
VG
L
Write
X
Data
Out Disable
Write
H
X
LX
High Z/Data Out
V
X
X
H
Inhibit
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device% This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied% Exposure to absolute maximum
rating conditions for extended periods may affect device reliability%
CAPACITANCE
(TA = 25° C)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Max Unit
Parameter
Symbol
VCC
VIH
Min
4%5
2%0
-0%5
-55
-40
Max
5%5
Unit
V
Address Input Capacitance
OE Capacitance
CAD
COE
VIN = 0V, f = 1%0MHz 50 pF
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp% (Mil%)
Operating Temp% (Ind%)
VCC + 0%3
+0%8
V
CS1-4 Capacitance
WE1-4 Capacitance
CCS
CWE
CI/O
VIN = 0V, f = 1%0MHz 20 pF
VIN = 0V, f = 1%0MHz 20 pF
VIN = 0V, f = 1%0MHz 20 pF
VIL
V
TA
+125
°C
°C
Data I/
O Capacitance
TA
+85
This parameter is guaranteed by design but not tested%
DC CHARACTERISTICS
(VCC = 5ꢀ0V, GND = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
Conditions
-80
-90
-120
-150Units
Min Max Min Max Min Max Min Max
Input Leakage Current
Output Leakage Current
ILI
VCC = 5%5, VIN = GND to VCC
10
10
10
10
10
10
10
10
µA
µA
mA
mA
V
ILO x 32 CS = VIH, OE = VIH, VOUT = GND to VCC
Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz
320
2%5
250
2%5
200
2%5
150
2%5
Standby Current
ISB
VOL
VOH
CS = VIH, OE = VIH, f = 5MHz
IOL = 2%1mA, VCC = 4%5V
IOH = -400µA, VCC = 4%5V
Output Low Voltage
Output High Voltage
0%45
0%45
0%45
0%45
2%4
2%4
2%4
2%4
V
NOTE: DC test conditions: VIH = VCC -0%3V, VIL = 0%3V
FIGꢀ 3 AC TEST CIRCUIT
AC TEST CONDITIONS
Typ
Parameter
Unit
V
Input Pulse Levels
VIL = 0, VIH = 3%0
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1%5
1%5
V
≈
Notes:
VZ is programmable from -2V to +7Vꢀ
IOL & IOH programmable from 0 to 16mAꢀ
Tester Impedance Z0 = 75 Wꢀ
VZ is typically the midpoint of VOH and VOLꢀ
IOL & IOH are adjusted to simulate a typical resistive load circuitꢀ
ATE tester includes jig capacitanceꢀ
3
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
WRITE
erationꢀ Each subsequent WE transition from high to
low that occurs before the completion of the 150 µsec
time out will restart the timer from zeroꢀ The operation
of the timer is the same as a retriggerable one-shotꢀ
A write cycle is initiated when OE is high and a low pulse
is on WE or CS with CS or WE lowꢀ The address is
latched on the falling edge of CS or WE whichever oc-
curs lastꢀ The data is latched by the rising edge of CS
or WE, whichever occurs firstꢀ A byte write operation
will automatically continue to completionꢀ
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relation-
shipsꢀ A write cycle begins with address application,
write enable and chip selectꢀ Chip select is accom-
plished by placing the CS line lowꢀ Write enable con-
sists of setting the WE line lowꢀ The write cycle begins
when the last of either CS or WE goes lowꢀ
The WE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode op-
AC WRITE CHARACTERISTICS
(VCC = 5ꢀ0V, GND = 0V, TA = -55°C TO +125°C)
WRITE
CYCLE
-80-90-120-150
Write Cycle Parameter
Symbol
tWC
Min
Max
Min
Max
Min
Max
Min
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time, TYP = 6ms
Address Set-up Time
10
10
10
10
tAS
0
100
0
0
100
0
30
150
0
30
150
0
Write Pulse Width (WE or CS)
Chip Select Set-up Time
Address Hold Time
tWP
tCS
tAH
50
0
50
0
100
10
0
100
10
0
Data Hold Time
tDH
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
0
0
50
50
10
10
50
50
10
10
100
50
10
10
100
50
10
10
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
tWPH
tOES
tOEH
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4
WE32K32-XXX
White Electronic Designs
FIGꢀ 4 WRITE WAVEFORMS WE CONTROLLED
t
WC
OE
t
t
OEH
OES
ADDRESS
t
CSH
t
AS
t
AH
CS 1-4
WE 1-4
t
CS
t
WP
t
WPH
DH
t
t
DS
DATA IN
FIGꢀ 5 WRITE WAVEFORMS CS CONTROLLED
tWC
OE
tOEH
t OES
ADDRESS
tCSH
tAS
tAH
WE1 - 4
CS1 - 4
tCS
tWP
t WPH
t DH
tDS
DATA IN
5
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
READ
The WE32K32-XXX stores data at the memory loca-
tion determined by the address pinsꢀ When CS and
OE are low and WE is high, this data is present on the
outputsꢀ When CS and OE are high, the outputs are in
a high impedance stateꢀ This 2 line control prevents
bus contentionꢀ
AC READ CHARACTERISTICS (SEE FIGURE 6)
(VCC = 5ꢀ0V, GND = 0V, TA = -55°C TO +125°C)
READ CYCLE
Symbol
-80-90-12U0-n15it0
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
80
90
120
150
ns
ns
ns
ns
ns
ns
Address Access Time
CS Access Time
80
80
90
90
120
120
150
150
Output Hold from Add% Change, OE or CS
Output Enable to Output Valid
Chip Select or OE to Output in High Z
0
0
0
0
tOE
40
40
50
50
85
70
85
70
tDF
FIGꢀ 6 READ WAVEFORMS
t RC
ADDRESS VALID
ADDRESS
CS
tACS
tOE
OE
NOTES:
tDF
1ꢀ OE may be delayed up to tACS - tOE after the falling
edge of CS without impact on tOE or by tACC - tOE after
an address change without impact on tACCꢀ
2ꢀ tCHZ, tOHZ are specified from OE or CS whichever
occurs first (CL = 5pF)ꢀ
tACC
t OH
HIGH Z
OUTPUT
VALID
OUTPUT
3ꢀ All I/O transitions are measured ±200 mV from steady
state with loading as specified in "Load Test Circuitsꢀ"
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
6
WE32K32-XXX
White Electronic Designs
DATA POLLING
The WE32K32-XXX offers a data polling feature
which allows a faster method of writing to the
deviceꢀ Figure 7 shows the timing diagram for this
functionꢀ During a byte or page write cycle, an
attempted read of the last byte written will result in
the complement of the written data on D7 (for each
chipꢀ) Once the write cycle has been completed,
true data is valid on all outputs and the next cycle
may beginꢀ Data polling may begin at any time
during the write cycleꢀ
DATA POLLING CHARACTERISTICS
(VCC = 5ꢀ0V, GND = 0V, TA = -55°C TO +125°C)
Parameter
Symbol Min Max Unit
Data Hold Time
OE Hold Time
tDH
tOEH
tOE
10
10
ns
ns
ns
ns
OE To Output Valid
Write Recovery Time
100
tWR
0
FIGꢀ 7 DATA POLLING WAVEFORMS
WE1-4
CS1-4
tOEH
OE
tOE
tDH
I/O7
HIGH Z
tWR
ADDRESS
7
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
The usual procedure is to increment the least signifi-
cant address lines from A0 through A5 at each write
cycleꢀ In this manner a page of up to 64 bytes can be
loaded in to the EEPROM in a burst mode before be-
ginning the relatively long interval programming cycleꢀ
PAGE WRITE OPERATION
The WE32K32-XXX has a page write operation that al-
lows one to 64 bytes of data to be written into the device
and consecutively loads during the internal programming
periodꢀ Successive bytes may be loaded in the same
manner after the first data byte has been loadedꢀ An in-
ternal timer begins a time out operation at each write cycleꢀ
If another write cycle is completed within 150µs or less, a
new time out period beginsꢀ Each write cycle restarts the
delay periodꢀ The write cycles can be continued as long
as the interval is less than the time out periodꢀ
After the 150µs time out is completed, the EEPROM
begins an internal write cycleꢀ During this cycle the
entire page of bytes will be written at the same timeꢀ
The internal programming cycle is the same regardless
of the number of bytes accessedꢀ
PAGE WRITE CHARACTERISTICS
(VCC = 5ꢀ0V, GND = 0V, TA = -55°C TO +125°C)
PAGE MODE WRITE CHARACTERISTICS
Parameter
Symbol
-80-90 -120U-1n5i0t
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
Data Set-up Time
tWC
tDS
10
10
10
10
ms
ns
ns
ns
µs
ns
50
0
50
0
100
10
100
10
Data Hold Time
tDH
Write Pulse Width
tWP
tBLC
tWPH
100
100
150
150
Byte Load Cycle Time
Write Pulse Width High
150
150
150
150
50
50
50
50
FIGꢀ 8 PAGE WRITE WAVEFORMS
OE
CS
tWP
tBLC
tWPH
WE
tDS
tDH
ADDRESS (1)
VALID
ADDRESS
tWC
VALID DATA
DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE n
BYTE n + 1
NOTE:
1ꢀ Decoded Address Lines must be valid for the duration of the writeꢀ
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
8
WE32K32-XXX
White Electronic Designs
FIGꢀ 9
SOFTWARE BLOCK DATA
PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
WRITES ENABLED(2)
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
ENTER DATA
TO
PROTECT STATE
LAST ADDRESS
NOTES:
1ꢀ Data Format: D7 - D0 (Hex);
Address Format: A14 - A0 (Hex)ꢀ
2ꢀ Write Protect state will be activated at end of write even if no
other data is loadedꢀ
3ꢀ Write Protect state will be deactivated at end of write period
even if no other data is loadedꢀ
4ꢀ 1 to 64 bytes of data may be loadedꢀ
9
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
SOFTWARE DATA PROTECTION
FIGꢀ 10
A software write protection feature may be enabled
or disabled by the userꢀ When shipped by White
Microelectronics, the WE32K32-XXX has the
feature disabledꢀ Write access to the device is
unrestrictedꢀ
SOFTWARE BLOCK DATA
PROTECTION DISABLE ALGORITHM(1)
To enable software write protection, the user writes
three access code bytes to three special internal
locationsꢀ Once write protection has been enabled,
each write to the EEPROM must use the same
three byte write sequence to permit writingꢀ After
setting software data protection, any attempt to
write to the device without the three-byte command
sequence will start the internal write timersꢀ No data
will be written to the device, however, for the
duration of tWCꢀ The write protection feature can be
disabled by a six byte write sequence of specific
data to specific locationsꢀ Power transitions will not
reset the software write protectionꢀ
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
Each 32KByte block of the EEPROM has indepen-
dent write protectionꢀ One or more blocks may be
enabled and the rest disabled in any combinationꢀ
The software write protection guards against inad-
vertent writes during power transitions, or unautho-
rized modification using a PROM programmerꢀ
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
(3)
EXIT DATA
PROTECT STATE
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE32K32-XXXꢀ These are included to improve reli-
ability during normal operation:
LOAD DATA XX
TO
ANY ADDRESS(4)
(3)
LOAD LAST BYTE
TO
LAST ADDRESS
a) VCC power on delay
As VCC climbs past 3ꢀ8V typical the device will wait
5msec typical before allowing write cyclesꢀ
b) VCC sense
While below 3ꢀ8V typical write cycles are inhibitedꢀ
c) Write inhibiting
Holding OE low and either CS or WE high inhibits
write cyclesꢀ
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a
write cycleꢀ
NOTES:
1ꢀ Data Format: D7 - D0 (Hex);
Address Format: A14 - A0 (Hex)ꢀ
2ꢀ Write Protect state will be activated at end of write even if no
other data is loadedꢀ
3ꢀ Write Protect state will be deactivated at end of write period
even if no other data is loadedꢀ
4ꢀ 1 to 64 bytes of data may be loadedꢀ
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
10
WE32K32-XXX
White Electronic Designs
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) 0.25 (0.010) Sꢀ
PIN 1 IDENTIFIER
SꢀUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
0.13 (0.005)
1.42 (0.056) 0.13 (0.005)
0.76 (0.030) 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
11
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
25.15 (0.990) 0.25 (0.010) Sꢀ
3.51 (0.140) MAX
22.36 (0.880) 0.25 (0.010) Sꢀ
0.25 (0.010) 0.10 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
0.25 (0.010)
0.53 (0.021)
0.18 (0.007)
1
/ 7
1.01 (0.040)
0.13 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2U
CQFP fills the same fit
and function as the
JEDEC 68 lead CQFJ or
68 PLCCꢀ But the G2U
has the TCE and lead
inspection advantage of
the CQFP formꢀ
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
12
WE32K32-XXX
White Electronic Designs
PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE
CQFP (G1U)1
25.27 (0.995) 0.13 (0.005) Sꢀ
3.56 (0.140) MAX
23.88 (0.940) 0.25 (0.010) Sꢀ
0.25 (0.010)
0.61 (0.024)
0.15 (0.006)
0.84 (0.033) REF
DETAIL A
SEE DETAIL "A"
1.27 (0.050)
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE 1: Package not recommended for new design
PACKAGE 524: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE
CQFP (G1T)
25.27 (0.995) ± 0.13 (0.005) SQ
4.06 (0.160) MAX
23.88 (0.940) ± 0.25 (0.010) SQ
0.25 (0.010) MAX
0.83 (0.033)
± 0.32 (0.013)
0.84 (0.033) REF
DETAIL A
SEE DETAIL "A"
1.27 (0.050)
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
WE32K32-XXX
White Electronic Designs
ORDERING INFORMATION
W E 32K32 X - XXX X X X
WHITE ELECTRONIC DESIGNS CORPꢀ
EEPROM
ORGANIZATION, 32K x 32
User Configurable as 64Kx16 or 128Kx8
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
ACCESS TIME (ns)
PACKAGE TYPE:
H1 = Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22%4mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 510)
G1U1 = 23%9mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 519)
G1T = 23%9mm Ceramic Quad Flat Pack, CQFP (Package 524)
DEVICE GRADE:
Q
M
I
=
=
=
=
MIL-STD-883 Compliant
Military Screened
Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C
Commercial
LEAD FINISH:
Blank = Gold plated leads
A
=
Solder dip leads
NOTE 1: Package not recommended for new design
DEVICE TYPE
SPEED
PACKAGE
SMD NOꢀ
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
120ns
90ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94614 01HXX
5962-94614 02HXX
5962-94614 03HXX
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
120ns
90ns
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
5962-94614 01HZX
5962-94614 02HZX
5962-94614 03HZX
1
1
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
120ns
90ns
68 lead CQFP/J (G1U)
68 lead CQFP/J (G1U)
68 lead CQFP/J (G1U)
5962-94614 01H9X
5962-94614 02H9X
5962-94614 03H9X
1
1
1
1
NOTE 1: Package not recommended for new design
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
14
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