WED3DG7264V10JD1G [WEDC]
DRAM,;
| 型号： | WED3DG7264V10JD1G |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DRAM, 动态存储器 |
| 文件： | 总10页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY*
512MB – 2x32Mx72 SDRAM, UNBUFFERED w/PLL
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Burst Mode Operation
The WED3DG7264V is a 2x32Mx72 synchronous DRAM
module which consists of eighteen 32Mx8 stack SDRAM
components in TSOP II package, and one 2Kb EEPROM
in an 8 pin TSSOP package for Serial Presence Detect
which are mounted on a 144 pin SO-DIMM multilayer
FR4 Substrate.
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
* This product is under development, is not qualified or characterized and is subject to
change without notice.
ꢀ
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
NOTE: Consult factory for availability of:
• Lead-Free Products
ꢀ
ꢀ
3.3V 0.3V Power Supply
JEDEC144 Pin SO-DIMM JEDEC
• JD1: 31.75mm (1.25”)
• Vendor source control options
• Industrial temperature options
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Address Input (Multiplexed)
Select Bank
Data Input/Output
Clock Input
Check Bit (Data-In/Data-Out)
A0 – A12
BA0-1
DQ0-63
CLK0
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN FRONT PIN BACK
1
3
5
7
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VCC
A0
A1
2
4
6
8
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VCC
A3
A4
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
DQ13
DQ14
DQ15
VSS
CB0
CB1
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
DQ45
DQ46
DQ47
VSS
CB4
CB5
CKE0
VCC
CAS#
CKE1
A12
NC
NC
VSS
CB6
CB7
VCC
97
99
DQ22
DQ23
VCC
A6
A8
VSS
A9
98
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
100
102
104
106
108
110
112
114
CB0-7
101
103
105
107
109
111
113
CKE0,CKE1 Clock Enable Input
CS0#,CS1# Chip Select Input
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
SDA
SCL
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
CLK0
VCC
A10
VCC
RAS#
WE#
CS0#
CS1#
NC
VSS
CB2
CB3
VCC
DQ16
DQ17
DQ18
DQ19
VSS
115 DQM2 116 DQM6
117 DQM3 118 DQM7
Serial Data I/O
Serial Clock
119
121
123
125
127
129
131
133
135
137
139
141
143
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
120
122
124
126
128
130
132
134
136
138
140
142
144
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
DNU
NC
Do Not Use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
A2
VSS
A5
VSS
DQ48
DQ49
DQ50
DQ51
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ40
DQ41
DQ42
DQ43
VCC
DQ20
DQ21
DQ52
DQ53
SDA
VCC
SCL
VCC
DQ12
DQ44
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS1#
WE#
CS0#
DQM0
·
DQM4
DQM
S
S
S
WE#
S
S
S
WE#
WE#
WE#
S
S
WE#
WE#
S
S
WE#
WE#
DQM
DQM
DQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM1
DQM5
DQM
DQM
DQM
DQM
WE#
WE#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM6
S
WE#
S
WE#
DQM
DQM
DQM
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM2
DQM7
S
WE#
S
WE#
DQM
DQM
S
WE#
S
WE#
DQM
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM3
S
WE#
S
WE#
DQM
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CLK0
SDRAM
PLL
NOTE: DQ wiring may differ than described in this drawing, however
DQ/DQMB/CKE/S relationships must be maintained as shown.
RAS#
RAS#: SDRAM
CAS#
CKE0
CAS#: SDRAM
CKE0: SDRAM
CKE1: SDRAM
CKE1
SERIAL PD
BA0-BA1
A0-A12
BA0-BA1: SDRAM
A0-A12: SDRAM
SCL
SDA
A0
A1
A2
VCC
VSS
SDRAM
SDRAM
Note: All resistor values are 10 ohms unless otherwise specified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
V
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C
Parameter
Symbol
VCC
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
3.0
—
Max
3.6
Unit
V
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VCCQ+0.3
0.8
V
1
2
VIL
V
VOH
VOL
ILI
—
—
V
IOH= -2mA
IOL= + 2mA
3
—
0.4
V
-10
—
10
µA
Note:
1.
2.
3.
V
V
IH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
IL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
Any input 0V ≤ VIN ≤ VCCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA ≤ 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter
Symbol
CIN1
Max
74
Unit
Input Capacitance (A0-A12)
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
CIN2
74
CIN3
40
Input Capacitance (CLK0)
CIN4
5.5
40
Input Capacitance (CS0#)
CIN5
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data Input/Output Capacitance (DQ0-DQ63)
CIN6
11
CIN7
74
COUT
15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V 0.3V, 0°C ≤ TA ≤ +70°C
Version
Parameter
Symbol
Conditions
100/133
Units
Note
Operating Current
(One bank active)
ICC1
Burst Length = 1
tRC ≤ tRC(min)
IOL = 0mA
mA
1
1,620
Precharge Standby Current
in Power Down Mode
ICC2
ICC3
ICC4
CKE ≤ VIL(max), tCC = 10ns
mA
mA
35
Active Standby Current in
Power-Down Mode
CKE ≥ VIL(max), tCC = 10ns
540
Io = mA
Page burst
4 Banks activated
tCCD = 2CK
Operating Current (Burst mode)
1,800
mA
1
2
Refresh Current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
3,600
110
mA
mA
Self Refresh Current
Notes:
1.
2.
Measured with outputs open.
Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC = 3.3V 0.3V, 0°C ≤ TA ≤ +70°C
AC CHARACTERISTICS
7
75/10
PARAMETER
SYMBOL
tAC(3)
tAC(2)
tAH
MIN
MAX
5.4
MIN
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
-
NOTES
Access time from CLK (pos. edge)
CL = 3
CL = 2
27
5.4
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
tAS
tCH
tCL
CL = 3
CL = 2
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
23
23
7.5
0.8
1.5
0.8
1.5
0.8
1.5
CKE hold time
0.8
1.5
0.8
1.5
0.8
1.5
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
tDS
Data-out high-impedance time
CL = 3
CL = 2
tHZ(3)
tHZ(2)
tLZ
5.4
5.4
5.4
6
10
10
Data-out low-impedance time
Data-out hold time (load)
1
1
tOH
2.7
1.8
37
60
15
2.7
1.8
44
66
20
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
tOHN
tRAS
tRC
28
120K
64
120K
64
tRCD
tREF
tRFC
tRP
66
15
14
0.3
66
20
15
0.3
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
tRRD
tT
1.2
1.2
7
WRITE recovery time
tWR
1 CLK +
7ns
1 CLK +
7ns
24
14
67
15
75
ns
ns
14, 25
20
Exit SELF REFRESH to ACTIVE command
tXSR
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
AC FUNCTIONAL CHARACTERISTICS
VCC = 3.3V 0.3V, 0°C ≤ TA ≤ +70°C
PARAMETER
SYMBOL
tCCD
tCKED
tPED
7
1
1
1
0
0
2
0
4
2
1
1
2
2
75/10
UNITS
tCK
NOTES
17
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
1
1
1
0
0
2
0
5
2
1
1
2
2
tCK
14
tCK
14
tDQD
tDQM
tDQZ
tCK
17
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
tCK
17
tCK
17
tDWD
tDAL
tCK
17
tCK
15, 21
16, 21
17
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
tDPL
tCK
tBDL
tCK
tCDL
tCK
17
tRDL
tCK
16, 21
26
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
tMRD
tCK
Data-out to high-impedance from PRECHARGE command
CL = 3
CL = 2
tROH(3)
tROH(2)
3
2
3
2
tCK
tCK
17
17
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
Notes
1.
All voltages referenced to VSS
This parameter is sampled. VCC, VCCQ = +3.3V; = 25°C; pin under test biased at
1.4V. f = 1 MHz, TA
.
minimum cycle rate.
16. Timing actually specified by tWR
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease in a proportional amount by the amount
the frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for 75/10 and 7.
2.
.
3.
IDD is dependent on output loading and cycle rates.Specified values are obtained
with mini-mum cycle time and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ ≤ 70°C) is TA ensured.
An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.)
The two AUTO REFRESH command wake-ups should be repeated any time the
4.
5.
6.
22.
VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL
(MIN) = -2V for a pulse width ≤ 3ns.
t
REF refresh requirement is exceeded.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
7.
8.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
Outputs measured at 1.5V with equivalent load:
9.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
Q
26. JEDEC and PC100, PC133 specify three clocks.
50pF
27.
tAC for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For 75/10, CL = 3, tCK = 7.5ns; For 7, CL = 2, tCK = 7.5ns
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
IDD6 limit is actually a nominal value and does not result in a fail value.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point. If the input transition time is longer than 1ns, then
the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V
crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13.
IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
PACKAGE DIMENSIONS FOR JD1
Ordering Information
WED3DG7264V10JD1
WED3DG7264V7JD1
WED3DG7264V75JD1
NOTES:
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
Height*
31.75 (1.25”) MAX
31.75 (1.25”) MAX
31.75 (1.25”) MAX
CL=2
CL=3
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is
shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult
factory for qualified sourcing options. (M = Micron, S = Samsung and consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD1
67.72
(2.661 Max)
6.48
(0.255)
MAX
2.01 (0.079 Min)
WEDC
31.75
(1.25)
Max
4.01
(0.158)
MIN
3.99
(0.157)
19.99
(0.787)
32.79
(1.291)
23.14
(0.913)
3.20
(0.126)
MIN
0.99 0.10
(0.039 0.004)
4.60 (0.181)
28.2
1.50 (0.059)
(1.112)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
PACKAGE DIMENSIONS FOR D1
Ordering Information
WED3DG7264V10D1
WED3DG7264V7D1
WED3DG7264V75D1
NOTES:
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
Height*
31.75 (1.25”) MAX
31.75 (1.25”) MAX
31.75 (1.25”) MAX
CL=2
CL=3
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is
shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult
factory for qualified sourcing options. (M = Micron, S = Samsung and consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D1
67.72
(2.661 Max)
6.48
(0.255)
MAX
2.01 (0.079 Min)
WEDC
31.75
(1.25)
Max
4.01
(0.158)
MIN
3.99
(0.157)
19.99
(0.787)
32.79
(1.291)
23.14
(0.913)
3.20
(0.126)
MIN
0.99 0.10
(0.039 0.004)
4.60 (0.181)
28.2
1.50 (0.059)
(1.112)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG7264V-D1
-JD1
White Electronic Designs
PRELIMINARY
Document Title
512MB – 2x32Mx72 SDRAM, UNBUFFERED w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Created Datasheet
Updates
10-00
Advanced
Rev 1
Rev 2
10-02
3-05
Advanced
2.1 Added series resistors
Preliminary
2.2 Corrected block diagram
2.3 Added package JD1 option
2.4 Added lead-free and RoHS notes
2.5 Provided source control option
2.6 Availability of industrial temperature
2.7 Moved from Advanced to Preliminary
2.8 Updated laminate diagram
Rev 3
3.1 Updated CAP specs
3.2 Updated IDD specs
5-05
Preliminary
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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