WSE128K16-73G2TC [WEDC]
128Kx16 SRAM/EEPROM MODULE; 128Kx16 SRAM / EEPROM模块
| 型号： | WSE128K16-73G2TC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128Kx16 SRAM/EEPROM MODULE |
| 文件： | 总15页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WSE128K16-XXX
White Electronic Designs
PRELIMINARY*
128Kx16 SRAM/EEPROM MODULE
ꢀ
Commercial, Industrial and Military Temperature
Ranges
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
Access Times of 35ns (SRAM) and 150ns (EEPROM)
ꢀ
ꢀ
TTL Compatible Inputs and Outputs
Access Times of 45ns (SRAM) and 120ns (EEPROM)
Access Times of 70ns (SRAM) and 300ns (EEPROM)
Packaging
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
ꢀ
Weight - 13 grams typical
• 66 pin, PGA Type, 1.075" square HIP, Hermetic
Ceramic HIP (H1) (Package 400)
EEPROM MEMORY FEATURES
• 68 lead, Hermetic CQFP (G2T), 22mm (0.880")
square (Package 509). Designed to fit JEDEC 68
lead 0.990" CQFJ footprint (FIGURE 2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation
ꢀ
ꢀ
ꢀ
128Kx16 SRAM
Automatic Page Write Operation
Page Write Cycle Time 10ms Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
128Kx16 EEPROM
Organized as 128Kx16 of SRAM and 128Kx16 of
EEPROM Memory with separate Data Buses
ꢀ
ꢀ
Both blocks of memory are User Configurable as
256Kx8
Low Power CMOS
* This product is under development, is not qualified or characterized and is subject to
change without notice.
FIGURE 1 – WSE128K16-XH1X PIN
CONFIGURATION
PIN DESCRIPTION
ED0-15
SD0-15
A0-16
EEPROM Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
Top View
1
12
23
34
45
56
SWE#1-2
SCS#1-2
OE#
VCC
GND
NC
EWE#1-2
ECS#1-2
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
EEPROM Write Enable
EEPROM Chip Select
SD8
SD9
SD10
A13
SWE2#
SCS2#
GND
SD11
A10
SD15
SD14
SD13
SD12
OE#
NC
ED8
ED9
ED10
A6
VCC
ECS2#
EWE2#
ED11
A3
ED15
ED14
ED13
ED12
A0
A14
A7
A15
A11
NC
A8
A4
A1
A16
A12
SWE#1
SD7
A5
A2
BLOCK DIAGRAM
SWE1
#
SCS1
#
SWE2
#
SCS2
#
EWE1
#
ECS1
#
EWE2# ECS2#
NC
VCC
A9
EWE1#
ECS1#
GND
ED3
ED7
ED6
ED5
ED5
OE#
A0-16
SD0
SD1
SD2
SCS1#
NC
SD6
ED0
ED1
ED2
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
SRAM
128K x 8
SRAM
SD5
SD3
SD4
8
8
8
8
11
22
33
44
55
66
ED0-7
ED8-15
SD0-7
SD8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
FIGURE 2 WSE128K16-XG2TX PIN CONFIGURATION
Top View
PIN DESCRIPTION
ED0-15
SD0-15
A0-16
EEPROM Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
SD8
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
GND
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
SWE#1-2 SRAM Write Enable
SCS#1-2
OE#
VCC
GND
NC
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
EWE#1-2 EEPROM Write Enable
ECS#1-2
SD9
SD10
SD11
SD12
SD13
SD14
SD15
EEPROM Chip Select
BLOCK DIAGRAM
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SWE1
#
SCS1
#
SWE2
#
SCS2
#
EWE1
#
ECS1
#
EWE2# ECS2#
OE#
A0-16
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
SRAM
128K x 8
SRAM
8
8
8
8
ED0-7
ED8-15
SD0-7
SD8-15
0.940"
The WEDC 68 lead G2T CQFP fills the same fit and
function as the JEDEC 68 lead CQFJ or 68 PLCC. But
the G2T has the TCE and lead inspection advantage
of the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
TA
TSTG
VG
TJ
VCC
Min
-55
-65
-0.5
Max
+125
+150
VCC+0.5
150
Unit
°C
°C
V
°C
V
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
VCC
VIH
VIL
TA
Min
4.5
2.0
-0.3
-55
Max
5.5
VCC + 0.3
+0.8
Unit
V
V
V
°C
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
+125
-0.5
7.0
EEPROM TRUTH TABLE
CAPACITANCE
CS# OE# WE#
Mode
Standby
Read
Data I/O
High Z
Data Out
Data In
TA = +25°C
H
L
L
X
X
X
X
L
H
H
X
L
X
H
L
Parameter
OE# capacitance
WE#1-4 capacitance
HIP (PGA)
Symbol Conditions
Max Unit
50 pF
COE
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VI/O = 0 V, f = 1.0 MHz 20 pF
VIN = 0 V, f = 1.0 MHz 50 pF
Write
X
H
X
Out Disable
Write
Inhibit
High Z/Data Out
20
CWE
pF
CQFP G2T
20
20 pF
CS#1-4 capacitance
Data I/O capacitance
Address input capacitance
CCS
CI/O
CAD
SRAM TRUTH TABLE
This parameter is guaranteed by design but not tested.
SCS# OE# SWE#
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Power
Standby
Active
Active
Active
H
L
L
X
L
H
X
H
H
L
L
X
Data In
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
ILI
Conditions
Min
Max
10
Unit
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
VCC = 5.5, VIN = GND to VCC
µA
µA
mA
mA
V
ILO
SCS# = VIH, OE# = VIH, VOUT = GND to VCC
SCS# = VIL, OE# = ECS# = VIH, f = 5MHz, VCC = 5.5
ECS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 8.0mA, VCC = 4.5
10
I
CCx16
ISB
360
31.2
0.4
0.4
(35 to 45ns)
SRAM Output Low Voltage
(70ns)
(35 to 45ns)
SRAM Output High Voltage
(70ns)
EEPROM Operating Supply Current x 16 Mode
EEPROM Output Low Voltage
EEPROM Output High Voltage
VOL
VOL
IOL = 2.1mA, VCC = 4.5
V
VOH
VOH
ICC1
VOL
IOH = -4.0mA, VCC = 4.5
2.4
2.4
V
IOH = -1mA, VCC = 4.5
V
ECS# = VIL, OE# = SCS# = VIH
IOL = 2.1 mA, VCC = 4.5V
155
0.45
mA
V
VOH1
IOH = 400 µA, VCC = 4.5V
2.4
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH
.
2. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
SRAM AC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-35
-45
-70
Parameter
Read Cycle
Symbol
Units
Min
Max
Min
Max
Min
Max
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
1. This parameter is guaranteed by design but not tested.
tRC
tAA
tOH
tACS
tOE
tCLZ1
tOLZ1
tCHZ1
tOHZ1
35
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
45
70
0
0
5
35
20
45
25
70
35
3
0
3
0
5
5
20
20
20
20
25
25
SRAM AC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
-35
-45
-70
Symbol
Units
Write Cycle
Min
35
25
25
20
25
0
Max
Min
45
30
30
25
30
0
Max
Min
70
60
60
30
50
5
Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tAH
0
4
0
4
5
5
tOW1
tWHZ1
tDH
20
25
25
0
0
0
1. This parameter is guaranteed by design but not tested.
FIGURE 3 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
NOTES:
VIL = 0, VIH = 3.0
V
ns
V
IOL
5
1.5
1.5
Current Source
V
D.U.T.
Ceff = 50 pf
VZ ≈ 1.5V
(Bipolar Supply)
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL
.
IOH
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
FIGURE 4 – SRAM READ CYCLES
tRC
ADDRESS
SCS#
tRC
tAA
ADDRESS
tAA
tACS
tCLZ
tCHZ
tOH
SOE#
SRAM
PREVIOUS DATA VALID
DATA VALID
DATA I/O
tOE
tOLZ
tOHZ
DATA VALID
SRAM
DATA I/O
READ CYCLE 1, (SCS# = OE# = VIL, SWE# = VIH
)
HIGH IMPEDANCE
READ CYCEL 2, (SWE# = VIH
)
FIGURE 5 – SRAM WRITE CYCLE SWE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS#
tAS
tWP
SWE#
tOW
tDH
tDW
tWHZ
SRAM
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCEL SCS# CONTROLLED
tWC
ADDRESS
tAW
tAH
tAS
tCW
SCS#
SWE#
tWP
tDH
tDW
SRAM
DATA VALID
DATA I/O
WRITE CYCLE 2, SCS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
EEPROM AC WRITE CHARACTERISTICS
EEPROM WRITE
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
A write cycle is initiated when OE# is high and a low pulse
is on EWE# or ECS# with ECS# or EWE# low. The address
is latched on the falling edge of ECS# or EWE# whichever
occurs last. The data is latched by the rising edge of ECS#
or EWE#, whichever occurs first. A byte write operation
will automatically continue to completion.
Write Cycle Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Symbol Min
tWC
Max
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
tWP
tCS
0
150
0
Write Pulse Width (EWE# or ECS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tAH
tDH
100
10
0
100
10
10
50
WRITE CYCLE TIMING
tCSH
tDS
tOES
tOEH
tWPH
Figures 7 and 8 show the write cycle timing relationships.
Awrite cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing the
ECS# line low. Write enable consists of setting the EWE#
line low. The write cycle begins when the last of either
ECS# or EWE# goes low.
The EWE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent EWE# transition from high
to low that occurs before the completion of the 150 µsec
time out will restart the timer from zero. The operation of
the timer is the same as a retriggerable one-shot.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
FIGURE 7 – EEPROM WRITE WAVEFORMS EWE# CONTROLLED
tWC
OE#
tOEH
tOES
ADDRESS
ECS#1-2
tCSH
tAS
tAH
EWE#1-2
tCS
tWP
tWPH
tDH
tDS
EEPROM
DATA IN
FIGURE 8 – EEPROM WRITE WAVEFORMS ECS# CONTROLLED
tWC
OE#
tOEH
tOES
ADDRESS
ECS#1-2
tCSH
tAS
tAH
tCS
EWE#1-2
tWP
tWPH
tDH
tDS
EEPROM
DATA IN
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
EEPROM READ
The WSE128K16-XXX EEPROM stores data at the
memory location determined by the address pins. When
ECS# and OE# are low and EWE# is high, this data is
present on the outputs. When ECS# and OE# are high,
the outputs are in a high impedance state. This two line
control prevents bus contention.
EEPROM AC READ CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-120
-150
-300
Unit
Read Cycle Parameter
Symbol
Min
Max
Min
Max
Min
Max
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Add. Change, OE# or ECS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
tRC
tACC
tACS
tOH
tOE
tDF
120
150
300
ns
ns
ns
ns
ns
ns
120
120
150
150
300
300
0
0
0
0
0
0
50
70
55
70
85
70
FIGURE 9 – EEPROM READ WAVEFORMS
tRC
ADDRESS VALID
ADDRESS
ECS#1-2
tACS
tOE
OE#
tDF
tACC
tOH
EEPROM
DATA
OUTPUT
HIGH Z
OUTPUT
VALID
Note: OE# may be delayed up to tACS - tOE after the falling edge of ECS# without impact on tOE or by tACC - tOE after an address change without impact on tACC
.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
EEPROM DATA POLLING CHARACTERISTICS
EEPROM DATA POLLING
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
The WSE128K16-XXX offers a data polling feature for
the EEPROM which allows a faster method of writing to
the device. Figure 11 shows the timing diagram for this
function. During a byte or page write cycle, an attempted
read of the last byte written will result in the complement
of the written data on D7 (for each chip.) Once the write
cycle has been completed, true data is valid on all outputs
and the next cycle may begin. Data polling may begin at
any time during the write cycle.
Parameter
Symbol
tDH
tOEH
tOE
Min
10
10
Max
Unit
ns
ns
ns
ns
Data Hold Time
OE# Hold Time
OE# To Output Valid
Write Recovery Time
55
tWR
0
FIGURE 10 – EEPROM DATA POLLING WAVEFORMS
EWE#1-2
ECS#1-2
OE#
tOEH
tDH
tOE
ED7
HIGH Z
tWR
ADDRESS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
EEPROM PAGE WRITE OPERATION
The WSE128K16-XXX has a page write operation
that allows one to 128 bytes of data to be written into
the device and consecutively loads during the internal
programming period. Successive bytes may be loaded
in the same manner after the first data byte has been
loaded. An internal timer begins a time out operation at
each write cycle. If another write cycle is completed within
150µs or less, a new time out period begins. Each write
cycle restarts the delay period. The write cycles can be
continued as long as the interval is less than the time out
period.
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
EEPROM PAGE WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Page Mode Write Characteristics
Parameter
Symbol Min
Max
Unit
Write Cycle Time, TYP = 6ms
Address Set-up Time
Address Hold Time (1)
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
NOTE:
tWC
tAS
tAH
tDS
tDH
tWP
tBLC
tWPH
10
ms
ns
ns
ns
ns
ns
µs
ns
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In
this manner a page of up to 128 bytes can be loaded in
to the EEPROM in a burst mode before beginning the
relatively long interval programming cycle.
0
100
100
10
150
150
50
1. Page address must remain valid for duration of write cycle.
FIGURE 11 – EEPROM PAGE MODE WRITE WAVEFORMS
OE#
ECS#1-2
tWPH
tBLC
tWP
EWE#1-2
tAS
tAH
VALID
ADDRESS
ADDRESS
tDS
tDH
tWC
VALID
DATA
EEPROM
DATA
BYTE 3
BYTE 0 BYTE 1
BYTE 2
BYTE 127
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
FIGURE 12 – EEPROM SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
ꢁ
LOAD DATA 55
TO
ADDRESS 2AAA
ꢁ
LOAD DATA A0
WRITES ENABLED(2)
TO
ADDRESS 5555
ꢁ
LOAD DATA XX
TO
ANY ADDRESS(4)
ꢁ
LOAD LAST BYTE
ENTER DATA
TO
PROTECT STATE
LAST ADDRESS
NOTES:
1. Data Format: ED7 - ED0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
FIGURE 13 – EEPROM SOFTWARE DATA
EEPROM SOFTWARE DATA
PROTECTION
PROTECTION DISABLE ALGORITHM(1)
A software write protection feature may be enabled
or disabled by the user. When shipped by WEDC, the
WSE128K16-XXX has the feature disabled. Write access
to the device is unrestricted.
LOAD DATA AA
TO
ADDRESS 5555
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of twc. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
ꢁ
LOAD DATA 55
TO
ADDRESS 2AAA
ꢁ
LOAD DATA 80
TO
ADDRESS 5555
ꢁ
LOAD DATA AA
TO
ADDRESS 5555
ꢁ
LOAD DATA 55
TO
Each 128K byte block of the EEPROM has independent
write protection. One or more blocks may be enabled and
the rest disabled in any combination. The software write
protection guards against inadvertent writes during power
transitions, or unauthorized modification using a PROM
programmer.
ADDRESS 2AAA
ꢁ
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA(3)
ꢁ
PROTECT STATE
LOAD DATA XX
TO
ANY ADDRESS(4)
EEPROM HARDWARE DATA
PROTECTION
These features protect against inadvertent writes to
the WSE128K16-XXX. These are included to improve
reliability during normal operation:
ꢁ
LOAD LAST BYTE
TO
LAST ADDRESS
a)
VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5 msec typical before allowing write cycles.
b)
V
CC sense
NOTES:
1. Data Format: ED7 - ED0 (Hex);
While below 3.8V typical write cycles are inhibited.
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data
is loaded.
3. Write Protect state will be deactivated at end of write period even if no
other data is loaded.
4. 1 to 128 bytes of data may be loaded.
c) Write inhibiting
Holding OE# low and either ECS# or EWE# high
inhibits write cycles.
d) Noise filter
Pulses of <8ns (typ) on EWE# or ECS# will not
initiate a write cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
1.42 (0.056) 0.13 (0.005)
0.13 (0.005)
0.76 (0.030) 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) 0.26 (0.010) SQ
4.57 (0.180) MAX
22.36 (0.880) 0.26 (0.010) SQ
0.27 (0.011) 0.04 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.03 (0.946)
0.26 (0.010)
0.19 (0.007)
0.06 (0.002)
1° / 7°
1.0 (0.040)
0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
The WEDC 68 lead G2T CQFP fills the same
fit and function as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the TCE and lead
inspection advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSE128K16-XXX
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION
W S E 128K16 - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
35 = 35ns SRAM and 150ns EEPROM
42 = 45ns SRAM and 120ns EEPROM
73 = 70ns SRAM and 300ns EEPROM
ORGANIZATION, 128K x 16
EEPROM
SRAM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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