WV3HG2128M64EEU403D6SG [WEDC]
2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED; 2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED
| 型号： | WV3HG2128M64EEU403D6SG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED |
| 文件： | 总11页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED*
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
Unbuffered 240-pin, dual in-line memory module
The WV3HG2128M64EEU is a 2x128Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 128Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
V
V
CC = VCCQ = 1.8V
CCSPD = +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms 8,192 cycle refresh)
Gold edge contacts
Product is lead-free
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-6400*
400MHz
6-6-6
PC2-5300*
333MHz
5-5-5
PC2-4300
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
August 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No.
1
Symbol
VREF
VSS
Pin No.
Symbol
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCC
Pin Name
Function
61
A4
VSS
A0-A13
Address Inputs
2
62
VCC
DQ4
DQ5
VSS
A3
BA0,BA2
SDRAM Bank Address
Data Input/Output
Data strobes
3
DQ0
DQ1
VSS
63
A2
A1
4
64
VCC
VCC
DQ0-DQ63
DQS0-DQS7
DQS0#-DQS7#
DM0-DM7
5
65
VSS
DM0
NC
CK0
CK0#
VCC
6
DQS0#
DQS0
VSS
66
VSS
Data strobes complement
Data masks
7
67
VCC
VSS
8
68
NC
DQ6
DQ7
VSS
A0
9
DQ2
DQ3
VSS
69
VCC
VCC
ODT0, ODT1
On-die termination control
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
A10/AP
BA0
BA1
VCC
CK0,CK0#-CK2,CK2# Clock Inputs
71
DQ12
DQ13
VSS
DQ8
DQ9
VSS
72
VCC
RAS#
CS0#
VCC
CKE0, CKE1
CS0#, CS1#
RAS#
Clock Enables
73
WE#
CAS#
VCC
Chip Selects
74
DM1
NC
Row Address Strobe
Column Address Strobe
Write Enable
DQS1#
DQS1
VSS
75
ODT0
A13
76
CS1#
ODT1
VCCQ
VSS
VSS
CAS#
77
CK1
CK1#
VSS
VCC
WE#
NC
78
VSS
SA0-SA2
SDA
SPD address
NC
79
DQ36
DQ37
VSS
VSS
80
DQ32
DQ33
VSS
DQ14
DQ15
VSS
SPD Data Input/Output
SPD Clock Input
Core Power (1.8V)
Ground
DQ10
DQ11
VSS
81
SCL
82
DM4
NC
VCC
83
DQS4#
DQS4
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
84
VSS
VSS
85
DQ38
DQ39
VSS
VREF
Power Supply for Reference
SPD Power
86
DQ34
DQ35
VSS
DM2
NC
V
CCSPD
DQS2#
DQS2
VSS
87
88
VSS
DQ44
DQ45
VSS
NC
Spare pins, No connect
89
DQ40
DQ41
VSS
DQ22
DQ23
VSS
DQ18
DQ19
VSS
90
91
DM5
NC
92
DQS5#
DQS5
VSS
DQ28
DQ29
VSS
DQ24
DQ25
VSS
93
VSS
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
DM3
NC
DQS3#
DQS3
VSS
96
97
VSS
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ30
DQ31
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2#
VSS
SA2
NC
NC
NC
NC
NC
VSS
VSS
DM6
NC
VSS
DQS6#
DQS6
VSS
NC
NC
NC
VSS
NC
VSS
DQ54
DQ55
VSS
VSS
DQ50
DQ51
VSS
NC
NC
NC
NC
VSS
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VCC
VCC
CKE1
VCC
CKE0
VCC
DM7
NC
DQS7#
DQS7
VSS
NC
BA2
NC
NC
VSS
VCC
DQ62
DQ63
VSS
VCC
DQ58
DQ59
VSS
A12
A9
A11
A7
VCC
VCCSPD
SA0
SA1
VCC
SDA
SCL
A8
A5
A6
August 2006
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ30
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serical PD
V
CCSPD
SCL
WP
Serial PD
SDA
DDR2 SDRAMs
A0
A1
SA1
A2
SA2
V
CC\VCCQ
SA0
VREF
DDR2 SDRAMs
DDR2 SDRAMs
V
SS
*Clock Wiring
Clock
Input
CS0#
CS1#
BA0-BA2
CS0#: DDR 2 SDRAMs
CS1#: DDR 2 SDRAMs
BA0-BA2: DDR 2 SDRAMs
A0-A13: DDR 2 SDRAMs
RAS#: DDR 2 SDRAMs
CAS#: DDR 2 SDRAMs
WE#: DDR 2 SDRAMs
CKE0: DDR 2 SDRAMs
CKE1: DDR 2 SDRAMs
ODT0: DDR 2 SDRAMs
ODT1: DDR 2 SDRAMs
DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
4
6
6
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
A0-A13
RAS#
CAS#
WE#
*Wire per Clock Loading
Table/Wiring Diagrams
CKE0
CKE1
ODT0
ODT1
Notes:
1. DQ, DM, DQS/DQS# resistors: 5.1 Ohms +/-5%
2. BAx, Ax RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%
August 2006
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
1.8
Max
1.9
Unit
V
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
3.6
V
VTT
V
VCCSPD
-
V
1
VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
3. VCCQ of all IC's are tied to VCC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
2.3
100
80
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
°C
µA
Command/Address,
RAS#, CAS#, WE#,
-80
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
-40
-30
-10
-10
-32
40
30
10
10
32
µA
µA
µA
µA
µA
IL
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
IVREF
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz, VCC = 1.8V
Parameter
Symbol
CIN1
Min
20
12
12
10
9
Max
36
20
20
16
11
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A13, BA0~BA2, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance (CS0#, CS1#))
CIN2
CIN3
Input Capacitance (CK0, CK0#-CK2, CK2#)
CIN4
CIN5 (665)
CIN5 (534, 403)
COUT (665)
COUT (534, 403)
Input Capacitance (DQS0~DQS7), (DM0-DM7)
Input Capacitance (DQ0~DQ63)
9
12
11
9
9
12
August 2006
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature (Commercial)
TOPER
0ºC to 85ºC
ºC
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIL(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
VREF+ 0.250
VREF+ 0.200
V
V
V
V
VREF - 0.250
VREF - 0.200
August 2006
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge current;
806
665
553
403
Units
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
816
776
736
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
TBD
896
856
816
mA
ICC2P* Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
TBD
192
640
720
192
560
640
192
560
640
mA
mA
mA
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD
TBD
480
192
400
192
400
192
mA
mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
TBD
TBD
800
720
720
mA
mA
mA
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,336
1,336
1,136
1,136
1,016
1,016
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B** Burst auto refresh current;
t
CK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
TBD
TBD
3,520
160
3,440
160
3,360
160
mA
mA
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
TBD
2,496
2,336
2,176
mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
August 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
ps
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
TBD
ps
TBD
CK high-level width
CK low-level width
Half clock period
Clock jitter
tCK
tCK
ps
tCL
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tHP
MIN(tCH,tCL)
-125
MIN(tCH,tCL)
-125
MIN(tCH,tCL)
-125
tJIT
125
125
125
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
tLZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
ps
Data-out low-impedance window from
CK/CK#
TBD
TBD
TBD
TBD
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
DQ and DM input setup time relative to
DQS
tDS
tDH
100
225
0.35
100
225
0.35
150
275
0.35
DQ and DM input hold time relative to DQS
TBD
TBD
TBD
TBD
DQ and DM input pulse width (for each
input)
tDIPW
tQHS
tQH
tCK
ps
ps
Data hold skew factor
TBD
TBD
TBD
TBD
340
400
450
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
-400
+400
240
-450
+450
300
-500
+500
350
0.2
0.2
0.2
tCK
DQS falling edge from CK rising … hold
time
tDSH
0.2
0.2
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
TBD
TBD
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
Write command to first DQS latching
transition
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tDQSS
tIPW
tCK
tCK
Address and control input pulse width for
each input
0.6
0.6
0.6
TBD
TBD
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
August 2006
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
MAX
MIN
55
MAX
MIN
55
MAX
UNIT
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tRC
55
7.5
TBD
tRRD
7.5
7.5
ns
TBD
tRCD
15
15
15
ns
TBD
tFAW
37.5
40
37.5
37.5
40
37.5
37.5
40
37.5
ns
TBD
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRAS
70,000
70,000
70,000
ns
TBD
tRTP
7.5
7.5
7.5
ns
TBD
tWR
15
15
15
ns
TBD
Auto precharge write recovery + precharge
time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
tRP
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRPA
tRP+tCK
2
tRP+tCK
2
tRP+tCK
2
TBD
tMRD
TBD
tDELAY
tIS+tCK
tIH
tIS+tCK
tIH
tIS+tCK
tIH
TBD
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
127.5
70,000
7.8
127.5
70,000
7.8
127.5
70,000
7.8
ns
TBD
TBD
TBD
Average periodic refresh interval
tREFI
µs
ns
tRFC(MIN)
+10
tRFC(MIN)
+10
tRFC(MIN)
+10
TBD
Exit self refresh to non-READ command
tXSNR
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
200
tIS
200
tIS
200
tIS
tCK
ps
TBD
TBD
TBD
TBD
TBD
tISXR
TBD
TBD
TBD
tAOND
2
2
2
2
2
2
tCK
tAC(MAX)
+1000
tAC(MAX)
+1000
tAC(MAX)
+1000
ODT turn-on
tAON
tAC(MIN)
tAC(MIN)
tAC(MIN)
ps
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
TBD
TBD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MIN)
tAC(MIN)
tAC(MIN)
2 x tCK
+
2 x tCK
+
2 x tCK+
TBD
TBD
TBD
TBD
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC(MAX)
+1000
tAC(MAX)
+1000
tAC(MAX)
+1000
ps
ps
2.5 x
2.5 x
2.5 x
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK+
tAOFPD
tAC(MAX)
+1000
tAC(MAX)
+1000
tAC(MAX)
+1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
TBD
TBD
TBD
TBD
TBD
TBD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tXP
7-AL
6-AL
6-AL
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
A Exit precharge power-down to any non-
READ command.
2
3
2
3
2
3
CKE minimum high/low time
tCKE
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
August 2006
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D6
Speed/Data Rate
Frequency
Part Number
CAS Latency
tRCD
tRP
Height**
WV3HG2128M64EEU806D6xxG*
WV3HG2128M64EEU665D6xxG*
WV3HG2128M64EEU534D6xxG
WV3HG2128M64EEU403D6xxG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
* Contact factory for availability
NOTES:
• RoHS compliant product. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.50 (5.256)
133.20 (5.244)
4.00 (0.158)
MAX
3.00 (0.118)
(4X)
4.00 (0.158)
(4X)
30.50 (1.201)
29.85 (1.175)
17.80 (0.700)
TYP.
1.37 (0.054
1.17 (0.046
PIN 1
5.175 (0.204)
10.00 (0.394)
TYP.
(2X)
1.0 (0.039)
TYP.
0.80 (0.032)
TYP.
1.50 (0.059)
PIN 120
123.0 (4.843)
TYP.
BACK VIEW
PIN 121
PIN 240
5.0 (0.197) TYP.
63.0 (2.480)
TYP.
55.0 (2.165)
TYP.
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
August 2006
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 128M 64 E E U xxx D6 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH (x8)
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 240 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
August 2006
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D6
White Electronic Designs
ADVANCED
Document Title
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
DRAM Die Options:
• SAMSUNG: B-Die
• MICRON: U28A: A-Die, move to U38Z: D-Die Q4'06 and U48B: E-Die Q2'07
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Created
June 2006
Concept
August 2006
Advanced
1.0 Engineering review
1.1 Updated AC Specs
1.2 Moved from concept to advanced
August 2006
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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