WV3HG264M72EEU403D6MG [WEDC]
1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED; 1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED型号: | WV3HG264M72EEU403D6MG |
厂家: | WHITE ELECTRONIC DESIGNS CORPORATION |
描述: | 1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED |
文件: | 总11页 (文件大小:185K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
ꢀ
240-pin, dual in-line memory module (DIMM)
The WV3HG264M72EEU is a 2x64Mx74 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
ꢀ
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
ꢀ
Utilizes 800*, 667*, 533 and 400 MT/s DDR2
SDRAM components
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VCC = VCCQ = 1.8V 0.1V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual Rank
RoHS compliant
Package
• 240 Pin DIMM: 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
January 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Function
Address Input
Bank Address
Data Input/output
Check Bits
Data Strobe
Data Strobe negative
On Die Termination
Pin No.
1
2
3
4
5
6
7
8
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
Pin No.
61
Symbol
A4
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
VSS
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
A1
VCC
CK0
CK0#
VCC
A0
VCC
BA1
VCCQ
RAS#
CS0#
VCCQ
ODT0
A13
Pin Name
A0-A13
BA0, BA1
DQ0 ~ DQ63
CB0-CB7
DQS0 ~ DQS8
DQS0# ~ DQS8#
ODT0, ODT1
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
VCCQ
A2
VCC
VSS
VSS
VCC
NC
VCC
A10/AP
BA0
DQ4
DQ5
VSS
DM0
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
CK1
CK1#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CK0,CK0# - CK2, Clock Input
VCCQ
WE#
CAS#
VCCQ
CS1#
ODT1
VCCQ
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
CK2#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
VCC
VCCQ
VSS
SA0 ~ SA2
SDA
Clock enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Voltage Supply (1.8V 0.1Vꢀ
I/O Power (1.8Vꢀ
Ground
SPD Address
Serial Data I/O
Serial clock
Data Masks
VCC
VSS
NC
NC
VSS
DQ36
DQ37
VSS
DM4
NC
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
VCCQ
CKE0
VCC
NC
NC
VCCQ
A11
A7
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK2
CK2#
VSS
DM6
NC
SCL
VSS
DM(0-8ꢀ
A10/AP
VREF
VCCSPD
NC
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8
NC
VSS
CB6
CB7
VSS
VCCQ
CKE1
VCC
NC
NC
VCCQ
A12
A9
Address input/Auto precharge
I/O reference supply
Serial EEPROM
No Connect
94
95
96
97
98
99
DQ48
DQ49
VSS
SA2
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
VCCSPD
SA0
SA1
VCC
A8
A6
VCC
A5
January 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ8
DQ9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serial PD
SCL
WP
V
CCSPD
Serial PD
SDA
A0
A1
A2
V
CC/VCCQ
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SA0
SA1
SA2
V
REF
V
SS
*Clock Wiring
Clock
Input
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
DDR2 SDRAMs
CS0# : DDR2 SDRAMs
CS1# : DDR2 SDRAMs
CS0#
CS1#
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
BA0 - RBA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE0 : DDR2 SDRAMs
CKE1 : DDR2 SDRAMs
ODT0 : DDR2 SDRAMs
ODT1 : DDR2 SDRAMs
BA0 - BA1
A0 - A13
RAS#
*Wire per Clock Loading
Table/Wiring Diagrams
CAS#
WE#
CKE0
CKE1
Notes:
ODT0
1. DQ, DM, DQS, DQS# resistors: 5.1 Ohms +/- 5%
2. BAx, Ax, RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%
ODT1
NOTE: All resistor values are 22 ohms unless otherwise specified.
January 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
1.8
Max.
1.9
Units
Notes
Supply Voltage
V
V
V
V
V
1
4
4
2
3
I/O Supply Voltage
VCCL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
Notes:
VCCQ
VCCL
VREF
VTT
1.7
1.8
1.9
1.7
1.8
1.9
0.49*VCCQ
VREF-0.04
0.50*VCCQ
VREF
0.51*VCCQ
VREF+0.04
1.
2.
V
CC and VCCQ must track each other. VCCQ must be less than or equal to VCC
.
V
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/- percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3.
4.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
V
CCQ tracks with VCC; VCCL track with VCC
.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
VCC
Parameter
Min
- 1.0
- 0.5
- 0.5
- 0.5
-55
Max
2.3
2.3
2.3
2.3
100
85
Unit
V
Voltage on VCC pin relative to VSS
Voltage on VCCQ pin relative to VSS
Voltage on VCCL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VCCQ
VCCL
V
V
VIN, VOUT
TSTG
V
°C
°C
µA
TCASE
IL
Device operating Temperature
0
Input leakage current; Any input 0V<VIN<VCC
VREF input 0V<VIN<<0.95; Other pins not
under test = 0V
;
Command/Address, RAS#,
CAS#, WE#
-90
90
CS#, CKE
CK, CK#
-45
-30
-10
-10
45
30
10
10
µA
µA
µA
µA
DM
IOZ
Output leakage current; 0V<VOUT<VCCQ; DQs
and ODT are disable
DQ, DQS, DQS#
IVREF
VREF leakage current; VREF = Valid VREF level
-36
36
µA
January 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
Min
22
13
13
10
9
Max
40
22
22
16
11
Units
pF
Input Capacitance: (A0 ~ A13 , BA0 ~ BA1, RAS#, CAS#, WE#ꢀ
Input Capacitance: (CKE0, CKE1ꢀ, (ODT0, ODT1ꢀ
Input Capacitance: (CS0#, CS1#ꢀ
CIN1
CIN2
pF
CIN3
pF
Input Capacitance: (CK0, CK0# ~ CK2, CK2#ꢀ
CIN4
pF
CIN6 (E6ꢀ
CIN6 (D5ꢀ
COUT1 (E6ꢀ
COUT1 (D5ꢀ
pF
Input Capacitance: (DM0 ~ DM8ꢀ, (DQS0-DQS8ꢀ
Input Capacitance: (DQ0 ~ DQ63ꢀ, (CB0-CB7ꢀ
9
12
11
pF
9
pF
9
12
pF
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature
TOPER
0ºC to 85ºC
ºC
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DCꢀ
VIL(DCꢀ
Min
VREF + 0.125
-0.300
Max
Units
Input High (Logic 1ꢀ Voltage
Input Low (Logic 0ꢀ Voltage
VREF + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(ACꢀ
VIL(ACꢀ
VIL(ACꢀ
Min
Max
Units
AC Input High (Logic 1ꢀ Voltage
VREF+ 0.250
V
V
V
AC Input Low (Logic 0ꢀ Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0ꢀ Voltage DDR2-667, DDR2-800 (TBDꢀ
-
-
VREF - 0.250
VREF - 0.200
January 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol Proposed Conditions
Operating one bank active-precharge current;
806
665
534
403
Units
ICC0*
t
CK = tCK(ICCꢀ, tRC = tRC(ICCꢀ, tRAS = tRASmin(ICCꢀ; CKE is HIGH, CS# is HIGH between valid
837
792
792
mA
TBD
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICCꢀ, AL = 0; tCK = tCK(ICCꢀ, tRC = tRC (ICCꢀ, tRAS = tRAS MIN(ICCꢀ,
tRCD = tRCD(ICCꢀ; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
ICC1*
972
972
972
mA
TBD
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICCꢀ; CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
144
630
720
144
540
630
144
540
630
mA
mA
mA
TBD
TBD
TBD
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICCꢀ; CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICCꢀ; CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12ꢀ = 0
540
216
540
216
540
216
mA
mA
TBD
TBD
All banks open; tCK = tCK(ICCꢀ; CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
ICC3P**
ICC3N**
ICC4W**
ICC4R*
ICC5B**
ICC6*
Slow PDN Exit MRS(12ꢀ = 1
Active standby current;
All banks open; tCK = tCK(ICCꢀ, tRC = tRC(ICCꢀ, tRAS = tRAS MIN(ICCꢀ; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
990
1332
1377
2700
144
900
1152
1197
2520
144
900
1062
1062
2520
144
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICCꢀ, AL = 0; tCK = tCK(ICCꢀ, tRAS
=
tRAS MAX(ICCꢀ, tRP = tRP(ICCꢀ; CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICCꢀ, AL = 0; tCK
= tCK(ICCꢀ, tRAS = tRAS MAX(ICCꢀ, tRP = tRP(ICCꢀ; CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICCꢀ; Refresh command at every tRFC(ICCꢀ interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
Normal
address bus inputs are FLOATING; Data bus inputs are
FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICCꢀ, AL = tRCD(ICCꢀ-1*tCK(ICCꢀ; tCK
tCK(ICCꢀ, tRC = tRC(ICCꢀ, tRRD = tRRD(ICCꢀ, tRCD = 1*tCK(ICCꢀ; CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
=
ICC7*
2052
2052
2052
mA
TBD
* Value calculated as one module rank in thes operating condition, and all other module ranks in
January 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
ps
ps
ps
tCK
tCK
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6ꢀ
TBD
tCK (5ꢀ
3000
3750
5000
0.45
0.45
8000
8000
8000
0.55
0.55
TBD
TBD
Clock cycle time
tCK (4ꢀ
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
TBD
TBD
tCK (3ꢀ
TBD
TBD
CK high-level width
CK low-level width
tCH
TBD
TBD
TBD
tCL
0.45
0.55
0.45
0.55
TBD
MIN (tCH
tCL
-450
,
MIN (tCH
tCL
-500
,
MIN (tCH
tCL
-600
,
Half clock period
tHP
ps
ps
ps
TBD
TBD
TBD
TBD
ꢀ
ꢀ
ꢀ
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
tAC
+450
+500
+600
TBD
tHZ
tAC (MAXꢀ
tAC (MAXꢀ
tAC (MAXꢀ
TBD
Data-out low-impedance window from
CK/CK#
tLZ
tAC (MINꢀ tAC (MAXꢀ tAC (MINꢀ tAC (MAXꢀ tAC (MINꢀ tAC (MAXꢀ
ps
TBD
TBD
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
tDS
tDH
100
225
100
225
150
275
ps
ps
TBD
TBD
TBD
TBD
A DQ and DM input pulse width (for each
tDIPW
0.35
0.35
0.35
tCK
ps
ps
TBD
TBD
TBD
TBD
inputꢀ
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tQHS
340
400
450
TBD
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
TBD
tQH
- tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
Data valid output window (DVWꢀ
tDVW
ns
TBD
TBD
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
tDQSH
tDQSL
tDQSCK
tDSS
0.35
0.35
-400
0.2
0.35
0.35
-450
0.2
0.35
0.35
-500
0.2
tCK
tCK
ps
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
+400
240
+450
300
+500
350
TBD
TBD
tDSH
0.2
0.2
0.2
TBD
DQS…DQ skew, DQS to last DQ valid, per
group,
tDQSQ
ps
TBD
TBD
per access
DQS read preamble
tRPRE
tRPST
tWPRES
tWPRE
0.9
0.4
0
0.35
0.4
1.1
0.6
0.9
0.4
0
0.35
0.4
1.1
0.6
0.9
0.4
0
0.35
0.4
1.1
0.6
tCK
tCK
ps
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
DQS read postamble
DQS write preamble setup time
DQS write preamble
TBD
TBD
TBD
DQS write postamble
tWPST
0.6
0.6
0.6
TBD
Write command to first DQS latching
WL
WL +
0.25
WL
WL +
0.25
WL
WL +
0.25
tDQSS
tCK
tCK
TBD
TBD
TBD
transition
- 0.25
- 0.25
- 0.25
Address and control input pulse width for
each input
tIPW
0.6
0.6
0.6
TBD
NOTE:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
January 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
806 665
AC CHARACTERISTICS
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
200
275
2
55
7.5
15
37.5
45
7.5
15
tWR + tRP
10
15
MAX
MIN
250
375
2
55
7.5
15
37.5
45
7.5
15
tWR + tRP
7.5
15
MAX
MIN
250
475
2
55
7.5
15
37.5
45
7.5
15
tWR + tRP
10
15
MAX UNIT
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bankꢀ command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tIS
ps
ps
tCK
ns
ns
ns
TBD
tIH
TBD
tCCD
TBD
tRC
TBD
tRRD
TBD
tRCD
TBD
tFAW
37.5
70,000
37.5
70,000
37.5
70,000 ns
TBD
tRAS
TBD
tRTP
ns
ns
ns
ns
TBD
tWR
TBD
tDAL
TBD
tWTR
TBD
tRP
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRPA
tWR + tCK
2
tIS + tCK + tIH
tWR + tCK
2
tIS + tCK + tIH
tWR + tCK
2
tIS + tCK + tIH
ns
tCK
ns
TBD
tMRD
TBD
tDELAY
TBD
REFRESH to REFRESH command interval
Average periodic refresh interval
tRFC
127.5
70,000
7.8
127.5
70,000
7.8
127.5
70,000 ns
TBD
TBD
TBD
tREFI
7.8
µs
ns
TBD
tRFC (MINꢀ
+ 10
tRFC (MINꢀ
+ 10
tRFC (MINꢀ
+ 10
Exit self refresh to non-READ command
tXSNR
TBD
TBD
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
200
tIS
2
200
tIS
2
200
tIS
2
tCK
ps
tCK
TBD
TBD
TBD
TBD
TBD
2
2
2
TBD
tAC (MAXꢀ
tAC (MAXꢀ
tAC (MAXꢀ
+ 1000
2.5
ODT turn-on
tAON
tAC (MINꢀ
2.5
t
AC (MINꢀ
2.5
t
AC (MINꢀ
2.5
ps
tCK
ps
TBD
TBD
TBD
TBD
+ 1000
+ 1000
ODT turn-off delay
ODT turn-off
tAOFD
2.5
2.5
TBD
t
AC (MAXꢀ
t
AC (MAXꢀ
t
AC (MAXꢀ
tAOF
tAC (MINꢀ
tAC (MINꢀ
tAC (MINꢀ
TBD
+ 600
+ 600
+ 600
2 x tCK
+
2 x tCK
+
2 x tCK +
tAC (MINꢀ +
2000
t
t
AC (MINꢀ +
2000
t
t
AC (MINꢀ +
2000
ODT turn-on (power-down modeꢀ
ODT turn-off (power-down modeꢀ
tAONPD
tAC (MAXꢀ
tAC (MAXꢀ
tAC (MAXꢀ ps
+ 1000
TBD
TBD
TBD
+ 1000
+ 1000
2.5 x tCK
+
2.5 x tCK
+
2.5 x tCK +
tAC (MINꢀ +
2000
AC (MINꢀ +
2000
AC (MINꢀ +
2000
tAOFPD
tAC (MAXꢀ
+ 1000
tAC (MAXꢀ
+ 1000
tAC (MAXꢀ ps
+ 1000
TBD
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
3
8
3
8
2
3
8
2
tCK
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
2
TBD
TBD
TBD
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6 - AL
6 - AL
tCK
tCK
tCK
TBD
A Exit precharge power-down to any non-READ
tXP
2
3
2
3
2
3
TBD
TBD
TBD
command.
CKE minimum high/low time
tCKE
TBD
NOTE:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
January 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D6
Clock/Data Rate
Frequency
Part Number
CAS Latency
tRCD
tRP
Height*
W3HG264M72EEU806D6xG**
W3HG264M72EEU665D6xG**
W3HG264M72EEU534D6xG
W3HG264M72EEU403D6xG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
** Consult factory for availability
NOTES:
• RoHS compliant product. (G = RoHS Compliantꢀ
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(G = Infineon, M = Micron, S = Samsung & consult factory for othersꢀ
• Consult factory for availability of industrial temperature (-40°C to 85°Cꢀ option
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.35 (5.25)
133.20 (5.244)
3.00
(0.118)
(4x)
30.50 (1.201)
29.85 (1.175)
+
+
17.80 (0.700)
TYP
10.00 (0.394)
TYP
4.00
(0.158)
(4x)
0.80 0.05
(0.032 0.002) TYP
4.00 (0.158)
PIN 20
PIN 1
2.50 0.20
(0.098 0.007)
1.50 0.10
(0.059 0.004)
1.00 (0.039) TYP
0.158 (4.00)
MAX
5.00
(0.196)
BACK VIEW
63.00 (2.48) TYP
55.00 (2.165) TYP
PIN 121
PIN 1
0.054 (1.37)
0.046 (1.17)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHESꢀ
January 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 64M 72 E E U xxx D6 x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 240 PIN
COMPONENT VENDOR
NAME
(G = Infineon)
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
January 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D6
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev 0
Created
January 2006
Advanced
January 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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