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W27L010S-12 [WINBOND]

128K ⅴ 8 ELECTRICALLY ERASABLE EPROM; 128K ⅴ 8电可擦除EPROM
W27L010S-12
型号： W27L010S-12
厂家： WINBOND    WINBOND
描述：

128K ⅴ 8 ELECTRICALLY ERASABLE EPROM
128K ⅴ 8电可擦除EPROM

可编程只读存储器 电动程控只读存储器
文件： 总14页 (文件大小：122K)
中文：  中文翻译
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Preliminary W27L010  
128K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 131072 ´ 8 bits. It requires only one supply in the range of 3.0V to 3.6V in  
normal read mode. The W27L010 provides an electrical chip erase function.  
FEATURES  
· High speed access time:  
90/120 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 10 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
· Erase/Programming operating current:  
compatible  
30 mA (max.)  
· Three-state outputs  
· Standby current: 20 mA (max.)  
· Available packages: 32-pin 600 mil DIP, 450  
· Low voltage power supply range, 3.0V to 3.6V  
mil SOP and PLCC  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
Q0  
.
.
PGM  
CE  
OUTPUT  
BUFFER  
Vcc  
Vpp  
A16  
A15  
A12  
A7  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
1
CONTROL  
DECODER  
PGM  
NC  
2
Q7  
OE  
3
A14  
A13  
A8  
4
5
A0  
.
A6  
6
CORE  
ARRAY  
A5  
7
A9  
32-pin DIP  
A11  
A4  
8
.
A3  
9
OE  
A16  
A2  
10  
11  
12  
13  
14  
A10  
A1  
CE  
Q7  
V
CC  
A0  
GND  
Q0  
Q6  
Q5  
V
PP  
Q1  
Q2  
18  
17  
Q4  
Q3  
15  
16  
GND  
PIN DESCRIPTION  
/
A
1
6
A
A
1
5
V
p
p
V
c
P
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
1
2
N
C
G
M
c
A0- A16  
Q0- Q7  
CE  
3
2
3
1
4
3
2
1
3
0
5
6
7
8
9
10  
11  
12  
13  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
Chip Enable  
A9  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
Ground  
No Connection  
OE  
32-pin PLCC  
A11  
OE  
A10  
CE  
Q7  
PGM  
VPP  
1
8
1
9
2
0
1
7
1
4
1
5
1
6
VCC  
GND  
NC  
Q
1
Q
2
Q
5
G
N
D
Q
3
Q
4
Q
6
Publication Release Date: February 1999  
Revision A1  
- 1 -  
Preliminary W27L010  
FUNCTIONAL DESCRIPTION  
Read Mode  
Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at  
the outputs.  
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.  
When addresses are stable, the address access time (TACC) is equal to the delay from CE to output  
(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings  
are met.  
Erase Mode  
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,  
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half  
an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by  
using an EPROM writer with a special erase algorithm.  
Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 =  
VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing PGM low starts  
the erase operation.  
Erase Verify Mode  
After an erase operation, all of the bytes in the chip must be verified to check whether they have been  
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase  
margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low,  
PGM high.  
Program Mode  
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only  
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP  
(12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input  
pins equal the desired inputs. Pulsing PGM low starts the programming operation.  
Program Verify Mode  
All of the bytes in the chip must be verified to check whether they have been successfully  
programmed with the desired data or not. Hence, after each byte is programmed, a program verify  
operation should be performed. The program verify mode automatically ensures a substantial  
program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low,  
OE low, and PGM high.  
Erase/Program Inhibit  
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different  
data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the  
CE, the W27L010 may have common inputs.  
- 2 -  
Preliminary W27L010  
Standby Mode  
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby  
mode, all outputs are in a high impedance state, independent of OE and PGM.  
Two-line Output Control  
Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for  
multiple memory connections. Two-line control provides for lowest possible memory power  
dissipation and ensures that data bus contention will not occur.  
System Considerations  
EPROM power switching characteristics require careful device decoupling. System designers are  
concerned with three supply current issues: standby current levels (Isb), active current levels (Icc),  
CE  
and transient current peaks produced by the falling and rising edges of  
. Transient current  
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and  
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have  
a 0.1 mF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherent-  
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight  
devices, a 4.7 mF electrolytic capacitor should be placed at the array's power supply connection  
between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace  
inductances.  
TABLE OF OPERATING MODES  
VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL  
MODE  
PINS  
A0  
A9  
X
VCC  
VPP  
OUTPUTS  
CE  
VIL  
OE  
VIL  
VIH  
X
PGM  
Read  
X
X
X
X
X
X
VCC VCC DOUT  
VCC VCC High Z  
VCC VCC High Z  
VCC VCC High Z  
Output Disable  
Standby (TTL)  
Standby (CMOS)  
Program  
VIL  
X
VIH  
X
X
X
X
X
VCC ±0.3V  
VIL  
VIH  
VIL  
X
VIL  
VIH  
X
X
X
VCP  
VCP  
VPP DIN  
Program Verify  
Program Inhibit  
Erase  
VIL  
X
X
VPP DOUT  
VIH  
X
X
VCP VPP High Z  
VIL  
VIH  
VIL  
X
VIL  
VIH  
X
VIL  
X
VPE  
X
VCP VPE FF (Hex)  
Erase Verify  
Erase Inhibit  
VIL  
VCP  
VPE DOUT  
VIH  
X
X
VCP VPE High Z  
Product Identifier-  
Manufacturer  
VIL  
VIL  
X
VIL  
VHH VCC VCC DA (Hex)  
Product Identifier-device  
VIL  
VIL  
X
VIH  
VHH VCC VCC 01 (Hex)  
Publication Release Date: February 1999  
Revision A1  
- 3 -  
Preliminary W27L010  
DC CHARACTERISTICS  
Absolute Maximum Ratings  
PARAMETER  
RATING  
0 to +70  
UNIT  
°C  
Operation Temperature  
Storage Temperature  
-65 to +125  
-0.5 to VCC +0.5  
°C  
Voltage on all Pins with Respect to Ground Except VCC, VPP  
and A9 Pins  
V
Voltage on VCC Pin with Respect to Ground  
Voltage on VPP Pin with Respect to Ground  
Voltage on A9 Pin with Respect to Ground  
-0.5 to +7  
-0.5 to +14.5  
-0.5 to +14.5  
V
V
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the  
device.  
DC Erase Characteristics  
(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)  
PARAMETER  
SYM.  
CONDITIONS  
LIMITS  
UNIT  
MIN.  
-10  
-
TYP. MAX.  
Input Load Current  
VCC Erase Current  
ILI  
VIN = VIL or VIH  
-
-
10  
30  
mA  
ICP  
mA  
CE = VIL, OE = VIH,  
PGM = VIL, A9 = VHH  
VPP Erase Current  
IPP  
-
-
30  
mA  
CE = VIL, OE = VIH,  
PGM = VIL, A9 = VHH  
Input Low Voltage  
VIL  
-
-0.3  
2.4  
-
-
0.8  
5.5  
V
V
V
V
V
V
V
Input High Voltage  
VIH  
-
Output Low Voltage (Verify)  
Output High Voltage (Verify)  
A9 Erase Voltage  
VOL  
VOH  
VID  
IOL = 2.1 mA  
-
-
0.45  
-
IOH = -0.4 mA  
2.4  
-
-
-
-
13.25  
13.25  
4.5  
14.0  
14.0  
5.0  
14.25  
14.25  
5.5  
VPP Erase Voltage  
VPE  
VCE  
VCC Supply Voltage (Erase)  
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.  
- 4 -  
Preliminary W27L010  
CAPACITANCE  
(VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz)  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
CONDITIONS  
VIN = 0V  
MAX.  
6
UNIT  
pF  
Output Capacitance  
COUT  
VOUT = 0V  
12  
pF  
AC CHARACTERISTICS  
AC Test Conditions  
PARAMETER  
Input Pulse Levels  
CONDITIONS  
0.45V to 2.4V  
Input Rise and Fall Times  
10 nS  
Input and Output Timing Reference Level  
Output Load  
0.8V/2.0V  
CL = 100 pF,  
IOH/IOL = -0.1 mA/1.6 mA  
AC Test Load and Waveforms  
+1.3V  
(IN914)  
3.3K ohm  
D
OUT  
100 pF (Including Jig and Scope)  
Output  
Input  
2.4V  
Test Points  
Test Points  
2.0V  
0.8V  
2.0V  
0.8V  
0.45V  
Publication Release Date: February 1999  
Revision A1  
- 5 -  
Preliminary W27L010  
READ OPERATION DC CHARACTERISTICS  
(VCC = 3.0V to 3.6V, TA = 0 to 70° C)  
PARAMETER  
SYM.  
CONDITIONS  
LIMITS  
UNIT  
MIN.  
-5  
TYP.  
MAX.  
5
Input Load Current  
ILI  
VIN = 0V to VCC  
-
-
-
mA  
mA  
mA  
Output Leakage Current  
ILO  
ISB  
VOUT = 0V to VCC  
-10  
-
10  
Standby VCC Current  
(TTL input)  
200  
CE = VIH  
Standby VCC Current  
(CMOS input)  
ISB1  
ICC  
-
-
-
-
20  
10  
mA  
CE = VCC ±0.2V  
VCC Operating Current  
mA  
CE = VIL  
IOUT = 0 mA  
f = 5 MHz  
VPP Operating Current  
Input Low Voltage  
IPP  
VPP = VCC  
-
-0.3  
2.0  
-
-
-
-
-
-
10  
0.6  
mA  
V
VIL  
-
Input High Voltage  
Output Low Voltage  
Output High Voltage  
VPP Operating Voltage  
VIH  
VOL  
VOH  
VPP  
-
IOL = 1.6 mA  
IOH = -0.1 mA  
-
VCC +0.5  
0.4  
V
-
V
2.4  
-
V
VCC -0.7  
VCC  
V
READ OPERATION AC CHARACTERISTICS  
(VCC = 3.0V to 3.6V, TA = 0 to 70° C)  
PARAMETER  
SYM.  
W27L010-90  
W27L010-12  
UNIT  
MAX.  
MIN.  
-
MAX.  
MIN.  
-
Read Cycle Time  
TRC  
90  
-
120  
nS  
nS  
nS  
nS  
nS  
Chip Enable Access Time  
Address Access Time  
TCE  
TACC  
TOE  
TDF  
90  
90  
40  
25  
-
-
-
-
120  
120  
55  
-
Output Enable Access Time  
-
-
30  
OE High to High-Z Output  
Output Hold from Address Change  
TOH  
0
-
0
-
nS  
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.  
- 6 -  
Preliminary W27L010  
DC PROGRAMMING CHARACTERISTICS  
(VCC = 5.0V ±10%, TA = 25° C ±5° C)  
PARAMETER  
SYM.  
CONDITIONS  
LIMITS  
UNIT  
MIN.  
TYP. MAX.  
Input Load Current  
ILI  
VIN = VIL or VIH  
-
-
-
-
10  
30  
mA  
VCC Program Current  
ICP  
mA  
CE = VIL, OE = VIH,  
PGM = VIL  
VPP Program Current  
IPP  
-
-
30  
mA  
CE = VIL, OE = VIH,  
PGM = VIL  
Input Low Voltage  
VIL  
-
-0.3  
2.4  
-
0.8  
5.5  
0.45  
-
V
V
V
V
V
V
V
Input High Voltage  
VIH  
-
-
Output Low Voltage (Verify)  
Output High Voltage (Verify)  
A9 Silicon I.D. Voltage  
VPP Program Voltage  
VOL  
VOH  
VID  
IOL = 2.1 mA  
-
-
-
IOH = -0.4 mA  
2.4  
-
-
-
11.5  
11.75  
4.5  
12.0  
12.5  
VPP  
VCP  
12.0 12.25  
5.0 5.5  
VCC Supply Voltage (Program)  
AC PROGRAMMING/ERASE CHARACTERISTICS  
(VCC = 5.0V ±10%, TA = 25° C ±5° C)  
PARAMETER  
SYM.  
LIMITS  
UNIT  
MIN.  
2.0  
2.0  
2.0  
95  
95  
2.0  
2.0  
-
TYP.  
MAX.  
VPP Setup Time  
TVPS  
TAS  
-
-
mS  
mS  
mS  
mS  
mS  
Address Setup Time  
Data Setup Time  
-
-
TDS  
-
-
TPWP  
TPWE  
TDH  
100  
105  
PGM Program Pulse Width  
100  
105  
PGM Erase Pulse Width  
Data Hold Time  
-
-
-
-
-
-
-
-
mS  
mS  
nS  
nS  
TOES  
TOEV  
TDFP  
TAH  
-
OE Setup Time  
150  
Data Valid from OE  
OE High to Output High Z  
0
130  
0
-
-
-
mS  
mS  
mS  
Address Hold Time after PGM High  
Address Hold Time (Erase)  
TAHE  
TCES  
2.0  
2.0  
CE Setup Time  
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.  
Publication Release Date: February 1999  
Revision A1  
- 7 -  
Preliminary W27L010  
TIMING WAVEFORMS  
AC Read Waveform  
V
IH  
Address  
Address Valid  
V
IL  
V
IH  
CE  
V
IL  
TCE  
V
IH  
OE  
T
DF  
V
IL  
T
OE  
T
OH  
T
ACC  
High Z  
Outputs  
Valid Output  
High Z  
Erase Waveform  
Read  
Manufacturer  
Read  
Device  
Blank Check  
Read Verify  
Erase Verify  
SID  
A9 = 12.0V  
SID  
Chip Erase  
A9 = 14.0V  
Others = V  
IL  
Others = V  
IL  
V
IH  
Address  
Stable  
Address  
Stable  
A0=V  
IH  
Address  
Stable  
Address  
Data  
A0 = V  
IL  
Others=V  
IL  
V
IL  
T
AS  
T
AS  
T
AS  
T
T
AHC  
ACC  
T
DFP  
D
OUT  
D
DA  
01  
D
OUT  
OUT  
Data All One  
T
DS  
T
DH  
T
AH  
14.0V  
5.0V  
3.3V  
2.7V  
T
VPS  
V
PP  
T
CE  
V
IH  
CE  
V
IL  
T
OES  
T
OE  
T
OE  
T
OE  
V
IH  
OE  
V
IL  
T
OEV  
T
PWE  
T
CES  
PGM  
- 8 -  
Preliminary W27L010  
Timing Waveforms, Continued  
Programming Waveform  
Program  
Verify  
Read  
Verify  
Program  
V
IH  
Address Stable  
Address Valid  
Address Stable  
Address  
Data  
V
IL  
T
DFP  
T
AS  
T
ACC  
D
D
OUT  
D
OUT  
OUT  
Data In Stable  
T
AH  
T
DS  
T
DH  
12.0V  
V
PP  
5V  
5.0V  
T
VPS  
T
CES  
V
IH  
CE  
V
IL  
T
OE  
V
IH  
OE  
V
IL  
T
OES  
T
OEV  
V
IH  
T
PWP  
PGM  
V
IL  
Publication Release Date: February 1999  
Revision A1  
- 9 -  
Preliminary W27L010  
SMART PROGRAMMING ALGORITHM  
Start  
Address = First Location  
Vcc = 5V  
Vpp = 12V  
X = 0  
Program One 100 S Pulse  
m
Increment X  
Yes  
X = 25?  
No  
Fail  
Verify  
One Byte  
Fail  
Verify  
One Byte  
Pass  
Pass  
No  
Last  
Address?  
Increment  
Address  
Yes  
Vcc = 3.3V  
Vpp = 3.3V  
Compare  
All Bytes to  
Fail  
Original Data  
Pass  
Fail  
Device  
Pass  
Device  
- 10 -  
Preliminary W27L010  
SMART ERASE ALGORITHM  
Start  
X = 0  
Vcc = 5V  
Vpp = 14V  
IL  
A9 = 14V; A0 = V  
Chip Erase 100 mS Pulse  
Address = First Location  
Increment X  
Vcc = 2.7V  
Vpp = 2.7V  
No  
Fail  
Erase  
Verify  
X = 20?  
Pass  
Yes  
No  
Increment  
Address  
Last  
Address?  
Yes  
Vcc = 3.3V  
Vpp = 3.3V  
Compare  
All Bytes to  
FFs (HEX)  
Fail  
Pass  
Pass  
Device  
Fail  
Device  
Publication Release Date: February 1999  
Revision A1  
- 11 -  
Preliminary W27L010  
ORDERING INFORMATION  
PART NO.  
ACCESS  
TIME  
POWER SUPPLY  
CURRENT MAX.  
(mA)  
STANDBY VCC  
CURRENT MAX.  
PACKAGE  
(nS)  
(mA)  
W27L010-90  
W27L010-12  
W27L010S-90  
W27L010S-12  
W27L010P-90  
W27L010P-12  
90  
120  
90  
8
8
8
8
8
8
20  
20  
20  
20  
20  
20  
600 mil DIP  
600 mil DIP  
450 mil SOP  
450 mil SOP  
32-pin PLCC  
32-pin PLCC  
120  
90  
120  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in  
applications where personal injury might occur as a consequence of product failure.  
PACKAGE DIMENSIONS  
32-pin P-DIP  
Dimension in mm  
Dimension in Inches  
Symbol  
A
Nom.  
Nom.  
Min.  
Max. Min.  
0.210  
Max.  
5.33  
0.010  
0.150  
0.25  
1
A
0.155 0.160  
3.81  
0.41  
1.22  
0.20  
3.94  
0.46  
1.27  
0.25  
4.06  
0.56  
1.37  
0.36  
2
A
0.016 0.018  
0.022  
0.054  
B
0.050  
0.048  
0.008  
1
B
0.010 0.014  
1.650 1.660  
D
c
D
E
17  
32  
41.91 42.16  
15.49  
14.10  
2.79  
0.610  
15.24  
13.97  
2.54  
0.590 0.600  
14.99  
13.84  
0.545  
0.090 0.100  
0.555  
0.110  
0.550  
1
E
2.29  
3.05  
0
e 1  
L
E1  
0.120  
0
0.140  
15  
3.30  
0.130  
3.56  
15  
a
0.630  
0.670 16.00  
0.085  
17.02  
2.16  
0.650  
16.51  
A
e
S
16  
1
Notes:  
E
S
1. Dimensions D Max. & S include mold flash or tie bar burr  
2. Dimension E1 does not include interlead flash.  
3. Dimensions D & E1 include mold mismatch and are  
determined at the mold parting line.  
4. Dimension B1 does not include dambar protrusion/intrusi  
5. Controlling dimension: Inches.  
6. General appearance spec. should be based on final visua  
inspection spec.  
c
2
A
A
L
A1  
Base Plane  
Seating Plane  
B
B
1
e
eA  
a
1
- 12 -  
Preliminary W27L010  
Package Dimensions, Continued  
32-pin SO Wide Body  
Dimension in mm  
Min. Nom. Max. Min. Nom. Max.  
Dimension in Inches  
Symbol  
0.118  
3.00  
A
17  
32  
0.004  
0.101  
0.014  
0.10  
2.57  
0.36  
0.15  
A 1  
A 2  
b
c
D
e1  
0.106 0.111  
2.69  
0.41  
2.82  
0.51  
0.016  
0.020  
0.012  
0.817  
0.450  
0.20  
0.31  
0.006 0.008  
0.805  
20.75  
11.43  
1.42  
20.45  
11.30  
1.27  
E H  
E
11.18  
1.12  
0.445  
0.440  
E
e
0.044 0.050 0.056  
q
0.556  
0.039  
0.546 0.556  
0.023  
13.87 14.12 14.38  
HE  
L
0.031  
0.047 0.055  
0.58  
1.19  
0.79  
1.40  
0.99  
L
0.063  
0.036  
1.60  
0.91  
L E  
S
y
Detail F  
1
16  
b
0.10  
10  
0.004  
10  
q
0
0
Notes:  
1. Dimensions D Max. & S include mold flash  
or tie bar burrs.  
2. Dimension b does not include dambar  
protrusion/intrusion.  
e1  
D
c
3. Dimensions D & E include mold mismatch  
.
A
A2  
and determined at the mold parting line.  
4. Controlling dimension: Inches.  
5. General appearance spec should be based  
on final visual inspection spec.  
e
S
y
L
E
A 1  
See Detail F  
Seating Plane  
32-Lead PLCC  
H E  
E
4
1
32  
30  
Dimension in Inches  
Dimension in mm  
Symbol  
A
Min. Nom. Max. Min. Nom. Max.  
5
29  
0.140  
3.56  
0.020  
0.105  
0.026  
0.016  
0.008  
0.50  
2.67  
0.66  
0.41  
0.20  
1
A
A
b
b
c
D
E
e
0.110  
0.028  
0.018  
0.010  
0.550  
0.450  
0.050  
0.510  
0.410  
0.590  
0.490  
0.090  
0.115  
0.032  
0.022  
0.014  
2.80  
0.71  
2.93  
0.81  
0.56  
0.35  
2
1
0.46  
G
D
0.25  
D
H
D
0.547  
0.447  
0.044  
0.490  
0.390  
0.585  
0.485  
0.075  
0.553  
0.453  
0.056  
0.530  
0.430  
0.595  
0.495  
0.095  
0.004  
13.89  
11.35  
1.12  
14.05  
11.51  
1.42  
13.97  
11.43  
1.27  
12.95  
12.45  
9.91  
13.46  
10.92  
15.11  
12.57  
2.41  
GD  
10.41  
14.99  
12.45  
2.29  
E
G
21  
13  
14.86  
12.32  
1.91  
HD  
E
H
L
y
14  
c
20  
0.10  
°
0
°
10  
°
0
°
10  
q
L
Notes:  
A2  
A
1. Dimensions D & E do not include interlead flash.  
2. Dimension b1 does not include dambar protrusion/intrusion.  
3. Controlling dimension: Inches.  
q
e
1
b
A
4. General appearance spec. should be based on final  
visual inspection sepc.  
b 1  
Seating Plane  
y
G
E
Publication Release Date: February 1999  
Revision A1  
- 13 -  
Preliminary W27L010  
VERSION HISTORY  
VERSION  
DATE  
Feb. 1999  
PAGE  
DESCRIPTION  
A1  
Initial Issued  
Winbond Electronics (H.K.) Ltd.  
Winbond Electronics North America Corp.  
Headquarters  
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5792647  
123 Hoi Bun Rd., Kwun Tong,  
Winbond Microelectronics Corp.  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
Winbond Systems Lab.  
2730 Orchard Parkway, San Jose,  
CA 95134, U.S.A.  
TEL: 1-408-9436666  
FAX: 1-408-9436668  
http://www.winbond.com.tw/  
Voice & Fax-on-demand: 886-2-7197006  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-7190505  
FAX: 886-2-7197502  
Note: All data and specifications are subject to change without notice.  
- 14 -  

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