W49F002UT70N [WINBOND]
Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, TSOP-32;
| 型号： | W49F002UT70N |
| 厂家： | 
WINBOND |
| 描述： | Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, TSOP-32 光电二极管 |
| 文件： | 总30页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W49F002U Data Sheet
256K × 8 CMOS FLASH MEMORY
Table of Content-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 4
FUNCTIONAL DESCRIPTION.................................................................................................... 5
6.1
Device Operation............................................................................................................ 5
6.1.1 Read Mode.......................................................................................................................5
6.1.2 Write Mode.......................................................................................................................5
6.1.3 Standby Mode ..................................................................................................................5
6.1.4 Output Disable Mode........................................................................................................5
6.1.5 Auto-select Mode..............................................................................................................5
6.1.6 Reset Mode: Hardware Reset ..........................................................................................6
Data Protection ............................................................................................................... 6
6.2.1 Low VDD Inhibit................................................................................................................6
6.2.2 Write Pulse "Glitch" Protection .........................................................................................6
6.2.3 Logical Inhibit ...................................................................................................................6
6.2.4 Power-up Write and Read Inhibit......................................................................................6
Command Definitions ..................................................................................................... 7
6.3.1 Read Command ...............................................................................................................7
6.3.2 Auto-select Command......................................................................................................7
6.3.3 Byte Program Command..................................................................................................7
6.3.4 Chip Erase Command ......................................................................................................8
6.3.5 Sector Erase Command ...................................................................................................8
Write Operation Status ................................................................................................... 8
6.4.1 DQ7: Data Polling.............................................................................................................8
6.4.2 DQ6: Toggle Bit................................................................................................................9
6.2
6.3
6.4
7.
8.
TABLE OF OPERATING MODES .............................................................................................. 9
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Device Bus Operations................................................................................................... 9
Auto-select Codes (High Voltage Method) ................................................................... 10
Embedded Programming Algorithm.............................................................................. 11
Embedded Erase Algorithm.......................................................................................... 12
Embedded #Data Polling Algorithm.............................................................................. 13
Embedded Toggle Bit Algorithm................................................................................... 13
Software Product Identification and Boot Block Lockout Detection Acquisition Flow .. 14
Boot Block Lockout Enable Acquisition Flow................................................................ 15
DC CHARACTERISTICS.......................................................................................................... 16
8.1
8.2
8.3
Absolute Maximum Ratings.......................................................................................... 16
DC Operating Characteristics....................................................................................... 16
Power-up Timing........................................................................................................... 17
Publication Release Date: April 19, 2005
- 1 -
Revision A7
W49F002U
9.
10.
CAPACITANCE......................................................................................................................... 17
AC CHARACTERISTICS .......................................................................................................... 17
10.1 AC Test Conditions....................................................................................................... 17
10.2 AC Test Load and Waveform ....................................................................................... 17
10.3 Read Cycle Timing Parameters.................................................................................... 18
10.4 Write Cycle Timing Parameters.................................................................................... 18
10.5 Datah Polling and Toggle Bit Timing Parameters......................................................... 19
10.6 Reset Timing Parameters............................................................................................. 19
TIMING WAVEFORMS............................................................................................................. 20
11.1 Read Cycle Timing Diagram......................................................................................... 20
11.2 #WE Controlled Command Write Cycle Timing Diagram............................................. 20
11.3 #CE Controlled Command Write Cycle Timing Diagram.............................................. 21
11.4 Program Cycle Timing Diagram.................................................................................... 21
11.5 #DATA Polling Timing Diagram.................................................................................... 22
11.6 Toggle Bit Timing Diagram ........................................................................................... 22
11.7 Boot Block Lockout Enable Timing Diagram ................................................................ 23
11.8 Chip Erase Timing Diagram.......................................................................................... 23
11.9 Sector Erase Timing Diagram....................................................................................... 24
11.10 Reset Timing Diagram................................................................................................. 24
ORDERING INFORMATION..................................................................................................... 25
HOW TO READ THE TOP MARKING...................................................................................... 26
PACKAGE DIMENSIONS......................................................................................................... 27
14.1 32-pin P-DIP ................................................................................................................. 27
14.2 32-pin PLCC ................................................................................................................. 27
14.3 32-pin STSOP (8 x 14 mm) .......................................................................................... 28
14.4 32-pin TSOP (8 x 20 mm)............................................................................................. 28
VERSION HISTORY................................................................................................................. 29
11.
12.
13.
14.
15.
- 2 -
W49F002U
1. GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
•
Single 5-volt operations:
− 5-volt Read
−
−
•
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
− 5-volt Erase
− 5-volt Program
•
Fast Program operation:
− Byte-by-Byte programming: 35 µS (typ.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 70/90/120 nS
Endurance: 10K cycles (typ.)
Ten-year data retention
•
End of program or erase detection
− Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP, 32-pin
STSOP (8 mm × 14 mm), 32-pin TSOP
(8 mm × 20 mm) , 32-pin-PLCC
and 32-pin-PLCC Lead free
•
•
•
•
•
•
−
•
•
•
•
Hardware data protection
One 16K byte Boot Block with Lockout
protection
•
•
•
Two 8K byte Parameter Blocks
Two Main Memory Blocks (96K, 128K) Bytes
Low power consumption
Publication Release Date: 8/10/2000
Revision A2.1
- 3 -
W49F002U
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
V
DD
32
31
30
29
28
27
#RESET
1
2
VDD
V
SS
#WE
A16
A15
A12
A7
3
A17
A14
4
DQ0
.
#CE
#OE
#WE
5
A13
OUTPUT
BUFFER
.
6
CONTROL
A8
A9
A6
7
26
25
24
23
22
21
20
A5
DQ7
32-pin
DIP
8
A11
#OE
A10
A4
#RESET
9
A3
10
A2
A1
11
12
13
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
A0
3FFFF
3C000
3BFFF
DQ0
BOOT BLOCK
16K BYTES
14
15
16
19
DQ1
DQ2
Vss
18
17
A0
.
PARAMETER
BLOCK1
8K BYTES
DECODER
3A000
39FFF
.
#
R
E
PARAMETER
BLOCK2
8K BYTES
A
1
2
A
V
D
D
#
W
E
A
A
1
5
S
E
T
1
6
1
7
A17
38000
37FFF
4
3
2
1
32 31 30
MAIN MEMORY
BLOCK1
96K BYTES
5
6
29
28
27
26
25
24
23
22
21
A14
A13
A8
A7
A6
20000
1FFFF
7
A5
MAIN MEMORY
32-pin
PLCC
8
A9
A4
BLOCK2
9
A11
#OE
A10
#CE
DQ7
A3
00000
128K BYTES
10
11
12
13
A2
A1
A0
DQ0
14 15 16 17 18 19 20
D
Q
1
D
Q
2
V
s
D
Q
4
D
Q
3
D
Q
5
D
Q
6
s
5. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
#OE
A10
#CE
DQ7
DQ6
DQ5
A11
A9
SYMBOL
PIN NAME
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A8
#RESET
A0 − A17
DQ0 − DQ7
#CE
Reset
A13
A14
A17
Address Inputs
Data Inputs/Outputs
Chip Enable
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
#WE
VDD
#RESET
A16
A15
A12
A7
32-pin
TSOP
#OE
#WE
Output Enable
Write Enable
Power Supply
Ground
A1
A6
A5
A4
A2
A3
VDD
VSS
- 4 -
W49F002U
6. FUNCTIONAL DESCRIPTION
6.1 Device Operation
6.1.1 Read Mode
The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for details.
6.1.2 Write Mode
Device erase and program are accomplished via the command register. The content of the register
serves as inputs to the internal state machine. The state machine outputs dictate the function of the
device.
The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state when #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
6.1.3 Standby Mode
There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin.
A CMOS standby mode is achieved with the #CE input held at VDD -0.3V. Under this condition the current is
typically reduced to less than 100 µA. A TTL standby mode is achieved with the #CE pin held at VIH.
Under this condition the current is typically reduced to less than 3 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
6.1.4 Output Disable Mode
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
6.1.5 Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended to be used by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9.
Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to
VIH. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes"). Note: The hardware
SID read function is not included in all parts; please refer to Ordering Information for details.
The manufacturer and device codes may also be read via the command register; i.e., the W49F002U is
erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".
Publication Release Date: April 19, 2005
- 5 -
Revision A7
W49F002U
Byte 0 (A0 = VIL) represents the manufacturer′s code (Winbond = DAh) and byte 1 (A0 = VIH) the
device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be VIL.
6.1.6 Reset Mode: Hardware Reset
The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of tRP, the device immediately terminates any
operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device
enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
6.2 Data Protection
The W49F002U is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
6.2.1 Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W49F002U locks out
when VDD < 2.5V. The write and read operations are inhibited when VDD is less than 2.5V typical. The
W49F002U ignores all write and read operations until VDD > 2.5V. The user must ensure that the
control pins are in the correct logic state when VDD > 2.5V to prevent unintentional writes.
6.2.2 Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.
6.2.3 Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
6.2.4 Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising
edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
- 6 -
W49F002U
6.3 Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read
mode.
6.3.1 Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
6.3.2 Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto the address lines is not generally a desirable system design
practice.
The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAh. A read cycle from address XX01H returns the device code (W49F002U =
0Bh).
6.3.3 Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later
and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of
#CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm.
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Publication Release Date: April 19, 2005
- 7 -
Revision A7
W49F002U
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot
be programmed back to a "1". Only erase operations can convert "0"s to "1"s.
Refer to the Embedded Programming Algorithm using typical command strings and bus operations.
6.3.4 Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each sector at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
6.3.5 Sector Erase Command
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase
command. The sector address (any address location within the desired sector) is latched on the falling
edge of #WE, while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase. When erasing a sector or
sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase
command pulse and terminates when the data on DQ7, Data Polling, is "1."
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
6.4 Write Operation Status
6.4.1 DQ7: Data Polling
The W49F002U device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.
The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm".
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
#WE pulse.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while
the output enable (#OE) is asserted low. This means that the device is driving status information on
DQ7 at one instant of time and then that byte′s valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
- 8 -
W49F002U
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –
DQ6 may be still invalid. The valid data on DQ0 − DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out (see "Command Definitions").
See " #DATA Polling During Embedded Algorithm Timing Diagrams".
6.4.2 DQ6: Toggle Bit
The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be
read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge
of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the
rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is
valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active during the sector
erase time-out.
7. TABLE OF OPERATING MODES
7.1 Device Bus Operations
PIN
MODE
#CE
VIL
VIL
VIH
VIH
VIH
VIL
X
#OE
VIL
VIH
X
#WE
VIH
VIL
VIL
X
#RESET
VIH
A0 − A17
DQ0 − DQ7
Dout
Read
Write
Ain
Ain
X
X
X
VIH
X
Din
High Z/DOUT
High Z/DOUT
High Z
Write Inhibit
X
X
VIH
Standby
X
VIH
Output Disable
Reset
VIH
X
VIH
X
VIH
X
High Z
VIL
X
High Z
Publication Release Date: April 19, 2005
Revision A7
- 9 -
W49F002U
7.2 Auto-select Codes (High Voltage Method)
OTHER
DQ7
A0
DESCRIPTION
#CE
VIL
#OE
VIL
#WE
VIH
A9
VID
VID
A1
VIL
VIL
ADD
TO DQ0
Manufacturer ID: Winbond
X
X
VIL
VIH
DAh
0Bh
Device ID: W49F002U
(Top Boot Block)
VIL
VIL
VIH
Notes:
1. SA = Sector Address, X = Don′t Care. Sector Protection Verification: 01h (protected); 00h (unprotected).
2. The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
Hardware Sequence Flags
DQ7
(NOTE)
OPERATION
DQ6
Embedded Program Algorithm
Embedded Erase Algorithm
#DQ7
0
Toggle
Toggle
Standard Mode
Note: DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Command Definition(1)
1TH CYCLE
2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
COMMAND
DESCRIPTION
NO. OF
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
CYCLES
ADDR. DATA
1
6
6
4
6
3
3
1
AIN DOUT
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
XXXX F0
Read
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
5555 80
5555 80
5555 A0
5555 80
5555 90
5555 F0
5555 AA
5555 AA
AIN DIN
5555 AA
2AAA 55
2AAA 55
5555 10
SA(3) 30
Chip Erase
Sector Erase
Byte Program
Boot Block Lockout
Product ID Entry
Product ID Exit (2)
Product ID Exit (2)
Notes:
2AAA 55
5555 40
1. Address Format: A14 − A0 (Hex); Data Format: DQ7 − DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
3. SA means: Sector Address
If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,
nothing will happen and the device will go back to read mode after 100nS.
If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.
If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.
If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.
If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.
If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.
- 10 -
W49F002U
7.3 Embedded Programming Algorithm
Start
Write Program Command Sequence
(see below)
#Data Polling/ Toggle bit
Pause TBP
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Publication Release Date: April 19, 2005
Revision A7
- 11 -
W49F002U
7.4 Embedded Erase Algorithm
Start
Write Erase Command Sequence
(see below)
#Data Polling or Toggle Bit
Successfully Completed
Pause
EC
SEC
/T
T
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector Erase
Command Sequence
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
Sector Address/30H
- 12 -
W49F002U
7.5 Embedded #Data Polling Algorithm
Start
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
Read Byte
(DQ0 - DQ7)
Address = VA
= Valid address equals any sector group
address during chip erase
No
DQ7 = Data
?
Yes
Pass
7.6 Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
Yes
DQ6 = Toggle
?
No
Pass
Publication Release Date: April 19, 2005
Revision A7
- 13 -
W49F002U
7.7 Software Product Identification and Boot Block Lockout Detection Acquisition
Flow
Product
Product
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Identification Exit(6)
Identification
Entry (1)
Load data AA
to
Load data AA
to
address 5555
address 5555
(2)
(2)
(4)
Load data 55
to
Load data 55
to
Read address = 0000
data = 00DA
address 2AAA
address 2AAA
Load data 90
Load data F0
to
Read address = 0001
data = 00AE
to
address 5555
address 5555
Read address = 0002
data in DQ0 =1/0
Pause 10 S
Pause 10 S
µ
µ
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ15 − DQ8 (Don't Care), DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)
(2) A1 − A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the
lockout feature is inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout
detection.
- 14 -
W49F002U
7.8 Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause 200 mS
Exit
Publication Release Date: April 19, 2005
Revision A7
- 15 -
W49F002U
8. DC CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage to Vss Potential
Operating Temperature
RATING
UNIT
-0.5 to +7.0
0 to +70
V
°C
°C
V
Storage Temperature
-65 to +150
D.C. Voltage on Any Pin to Ground Potential Except A9
Transient Voltage (<20 nS) on Any Pin to Ground Potential
Voltage on A9 Pin to Ground Potential
-0.5 to VDD +1.0
-1.0 to VDD +1.0
-0.5 to 12.5
V
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2 DC Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
LIMITS
MIN. TYP.
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MAX.
#CE = #OE = VIL, #WE = VIH,
all DQs open
Address inputs = VIL/VIH, at f = 5 MHz
mA
Power Supply
ICC
-
25
50
Current
ISB1 #CE = VIH, all DQs open
Other inputs = VIL/VIH
Standby VDD Current
(TTL input)
-
-
2
3
mA
Standby VDD Current
(CMOS input)
#CE = VDD -0.3V, all DQs open
µA
ISB2
20
100
Other inputs = VDD -0.3V/ Vss
Input Leakage
Current
Output Leakage
Current
ILI
VIN = Vss to VDD
-
-
-
-
10
10
µA
µA
ILO
VOUT = Vss to VDD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIL
VIH
-
-
-0.3
2.0
-
-
-
-
-
0.8
VDD +0.5
0.45
V
V
V
V
VOL IOL = 2.1 mA
VOH IOH = -0.4 mA
2.4
-
- 16 -
W49F002U
8.3 Power-up Timing
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
SYMBOL
TPU. READ
TPU. WRITE
TYPICAL
UNIT
µS
mS
100
5
9. CAPACITANCE
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
VIN = 0V
MAX.
12
6
UNIT
pF
pF
CIN
10. AC CHARACTERISTICS
10.1AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
Input Rise/Fall Time
Input/Output Timing Level
Output Load
0V to 3V
<5 nS
1.5V / 1.5V
1 TTL Gate and CL = 30pF (for 70 nS/ 90 nS), 100 pF (for 120 nS)
10.2AC Test Load and Waveform
+5V
1.8K
Ω
D
OUT
30 pF for 70nS / 90nS
100 pF for 120nS
1.3K
Ω
(Including Jig and Scope)
Input
Output
3V
1.5V
1.5V
0V
Test Point
Test Point
Publication Release Date: April 19, 2005
Revision A7
- 17 -
W49F002U
AC Characteristics, continued
10.3Read Cycle Timing Parameters
(VDD = 5.0V ±10%, VDD = 0V, TA = 0 to 70° C)
W49F002U-70 W49F002U-90 W49F002U-120
PARAMETER
Read Cycle Time
SYM.
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
TRC
70
-
-
90
-
-
120
-
120
120
50
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
Chip Enable Access Time
Address Access Time
TCE
70
70
35
-
90
90
40
-
-
-
TAA
-
-
Output Enable Access Time
#CE Low to Active Output
#OE Low to Active Output
#CE High to High-Z Output
#OE High to High-Z Output
Output Hold from Address Change
TOE
-
-
-
TCLZ
TOLZ
TCHZ
TOHZ
TOH
0
0
-
0
0
-
0
0
-
-
-
-
25
25
-
25
25
-
30
30
-
-
-
-
0
0
0
10.4Write Cycle Timing Parameters
PARAMETER
Address Setup Time
Address Hold Time
#WE and #CE Setup Time
#WE and #CE Hold Time
#OE High Setup Time
#OE High Hold Time
#CE Pulse Width
SYMBOL
TAS
MIN.
TYP.
-
MAX.
UNIT
0
50
0
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
S
TAH
-
-
TCS
-
-
TCH
0
-
-
TOES
TOEH
TCP
0
-
-
0
-
-
-
-
100
100
100
50
10
-
#WE Pulse Width
TWP
TWPH
TDS
-
-
#WE High Width
-
-
Data Setup Time
-
-
Data Hold Time
TDH
-
-
Byte Programming Time
Erase Cycle Time
TBP
35
0.1
50
0.2
TEC
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 18 -
W49F002U
AC Characteristics, continued
10.5Datah Polling and Toggle Bit Timing Parameters
W49F002U-70 W49F002U-90 W49F002U-120
PARAMETER
SYM.
UNIT
MIN.
MAX.
35
MIN.
MAX.
40
MIN.
MAX.
50
#OE to Data Polling Output Delay
#CE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
#CE to Toggle Bit Output Delay
TOEP
TCEP
TOET
TCET
-
-
-
-
-
-
-
-
-
-
-
-
nS
nS
nS
nS
70
90
120
50
35
40
70
90
120
10.6Reset Timing Parameters
PARAMETER
VDD stable to Reset Active
Reset Pulse Width
SYMBOL
TPRST
TRSTP
TRSTF
TRST
MIN.
TYP.
MAX.
UNIT
1
500
-
-
-
-
-
-
-
mS
nS
nS
µS
Reset Active to Output Float
Reset Inactive to Input Active
50
-
1
Publication Release Date: April 19, 2005
Revision A7
- 19 -
W49F002U
11. TIMING WAVEFORMS
11.1Read Cycle Timing Diagram
T
RC
Address A17-0
#CE
TCE
TOE
#OE
TOHZ
TOLZ
V
IH
#WE
TCLZ
T
OH
TCHZ
High-Z
High-Z
DQ7-0
Data Valid
Data Valid
AA
T
11.2#WE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A17-0
#CE
TCS
TOES
TCH
TOEH
#OE
#WE
TWP
TWPH
TDS
DQ7-0
Data Valid
TDH
- 20 -
W49F002U
Timing Waveforms, continued
11.3#CE Controlled Command Write Cycle Timing Diagram
AS
T
TAH
Address A17-0
#CE
T
CPH
T
CP
T
OES
T
OEH
#OE
#WE
T
DS
High Z
DQ7-0
Data Valid
T
DH
11.4Program Cycle Timing Diagram
Byte Program Cycle
5555 Address
2AAA
Address A17-0
5555
55
A0
Data-In
AA
DQ7-0
#CE
#OE
#WE
T
WPH
BP
T
WP
T
Internal Write Start
Byte 1
Byte 0
Byte 2
Byte 3
Publication Release Date: April 19, 2005
Revision A7
- 21 -
W49F002U
Timing Waveforms, continued
11.5#DATA Polling Timing Diagram
Address A17-0
#WE
An
An
An
An
TCEP
#CE
#OE
TOEH
TOES
TOEP
DQ7
X
X
X
X
TBP or TEC
11.6Toggle Bit Timing Diagram
Address A17-0
#WE
#CE
TOES
TOEH
#OE
DQ6
TBP orTEC
- 22 -
W49F002U
Timing Waveforms, continued
11.7Boot Block Lockout Enable Timing Diagram
Six byte code for Boot Block
Lockout Feature Enable
Address A17-0
5555
80
5555
5555
2AAA
55
5555
AA
2AAA
55
DQ7-0
#CE
AA
40
#OE
#WE
WP
T
EC
T
WPH
T
SB0
SB2
SB3
SB5
SB4
SB1
11.8Chip Erase Timing Diagram
Six-byte code for 5V-only software
chip erase
Address A17-0
5555
80
5555
2AAA
55
5555
AA
5555
2AAA
55
DQ7-0
#CE
AA
10
#OE
#WE
TWP
SB0
TEC
TWPH
Internal Erase starts
SB2
SB3
SB5
SB4
SB1
Publication Release Date: April 19, 2005
Revision A7
- 23 -
W49F002U
Timing Waveforms, continued
11.9Sector Erase Timing Diagram
Six-byte code for 5V-only software
Main Memory Erase
5555
5555
2AAA
55
5555
SA
2AAA
55
Address A17-0
80
DQ7-0
#CE
AA
AA
30
#OE
#WE
TWP
SB0
TEC
TWPH
Internal Erase starts
SB2
SB3
SB5
SB4
SB1
SA = Sector Address
11.10
Reset Timing Diagram
VDD
T
PRST
T
RSTP
#RESET
T
RSTF
T
RST
Address A17-0
DQ7-0
- 24 -
W49F002U
12. ORDERING INFORMATION
STANDBY
VDD
ACCES POWER
HARDWARE
CYCLE SID READ
FUNCTION
S TIME SUPPLY
PART NO.
PACKAGE
CURRENT
MAX. (µA)
CURRENT
(nS) MAX. (mA)
W49F002U-70B
W49F002U-90B
W49F002U-12B
W49F002UT70B
W49F002UT90B
W49F002UT12B
W49F002UP70B
W49F002UP90B
W49F002UP12B
W49F002UQ70B
W49F002UQ90B
W49F002UQ12B
W49F002U70BN
W49F002U90BN
W49F002U12BN
W49F002UT70N
W49F002UT90N
W49F002UT12N
W49F002UP70N
W49F002UP90N
W49F002UP12N
W49F002UQ70N
W49F002UQ90N
W49F002UQ12N
W49F002UP12Z
70
90
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
100 (CMOS) 32-pin DIP
100 (CMOS) 32-pin DIP
100 (CMOS) 32-pin DIP
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
120
70
100 (CMOS)
100 (CMOS)
100 (CMOS)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
90
120
70
100 (CMOS) 32-pin PLCC
100 (CMOS) 32-pin PLCC
100 (CMOS) 32-pin PLCC
90
120
70
100 (CMOS)
100 (CMOS)
100 (CMOS)
32-pin STSOP (8 mm × 14 mm)
32-pin STSOP (8 mm × 14 mm)
32-pin STSOP (8 mm × 14 mm)
90
120
70
100 (CMOS) 32-pin DIP
100 (CMOS) 32-pin DIP
100 (CMOS) 32-pin DIP
90
120
70
100 (CMOS)
100 (CMOS)
100 (CMOS)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
90
120
70
100 (CMOS) 32-pin PLCC
100 (CMOS) 32-pin PLCC
100 (CMOS) 32-pin PLCC
90
120
70
100 (CMOS)
100 (CMOS)
100 (CMOS)
32-pin STSOP (8 mm × 14 mm)
32-pin STSOP (8 mm × 14 mm)
32-pin STSOP (8 mm × 14 mm)
90
120
120
100 (CMOS) 32-pin PLCC Lead free
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. Winbond offers Top Boot Block device, if any of Bottom Boot Block devices is required, please contact Winbond FAEs.
4. In Hardware SID read function column: Y = with SID read function; N = without SID read function.
Publication Release Date: April 19, 2005
- 25 -
Revision A7
W49F002U
13. HOW TO READ THE TOP MARKING
Example: The top marking of 48-pin TSOP W49F002UT70B
W49F002UT70B
2138977A-A12
149OBSA
1st line: winbond logo
2nd line: the part number: W49F002UT70B
3rd line: the lot number
4th line: the tracking code: 149 O B SA
149: Packages made in ’01, week 49
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
SA: Process code
- 26 -
W49F002U
14. PACKAGE DIMENSIONS
14.132-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
5.33
0.210
0.010
0.150 0.155 0.160 3.81
0.25
A
A
B
1
3.94
0.46
4.06
0.56
2
0.016 0.018
0.41
1.22
0.022
0.054
0.050
1.27
1.37
0.048
0.008
1
B
0.010 0.014 0.20
1.650 1.660
0.25
0.36
c
D
17
32
41.91
15.24
13.97
2.54
42.16
15.49
14.10
2.79
D
E
0.610
0.555
0.110
0.590 0.600
14.99
13.84
2.29
0.545
0.550
E
1
0.090 0.100
e1
1
E
3.05
0
3.30
0.120 0.130 0.140
15
3.56
15
L
0
a
0.630 0.650 0.670 16.00 16.51 17.02
0.085
e
S
A
2.16
16
1
Notes:
E
S
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
c
2.Dimension E1 does not include interlead flash.
A
2
A
L
A1
Base Plane
3.Dimensions D & E1 include mold mismatch and
.
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
Seating Plane
5.Controlling dimension: Inches
B
B
1
e
eA
a
6.General appearance spec. should be based on
final visual inspection spec.
1
14.232-pin PLCC
Dimension in Inches
Min. Nom. Max. Min. Nom. Max.
Dimension in mm
Symbol
H E
E
0.140
3.56
A
0.020
0.105
0.026
0.016
0.008
0.50
2.67
0.66
0.41
0.20
A
A
b
b
c
1
2
1
4
1
32
30
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.51
0.115
0.032
0.022
0.014
2.80
0.71
0.46
0.25
13.97
11.43
1.27
12.9
2.93
0.81
0.56
0.35
5
29
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
13.89
11.35
1.12
14.05
11.51
1.42
D
E
e
12.45
9.91
13.46
10.92
15.11
12.57
2.41
G
G
H
H
D
G
D
0.410
0.590
0.49
10.41
14.99
12.45
2.29
E
D
E
D
HD
14.86
12.32
1.91
0.090
L
0.10
y
0
10
0
10
θ
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
14
20
c
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A
θ
e
1
b
b 1
A
Seating Plane
y
E
G
Publication Release Date: April 19, 2005
Revision A7
- 27 -
W49F002U
Package Dimensions, continued
14.332-pin STSOP (8 x 14 mm)
HD
D
Dimension in Inches Dimension in mm
c
Symbol
Max.
1.20
Min. Nom. Max. Min. Nom.
0.047
e
A
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
0.15
1
A
0.040
1.00
0.22
2
E
A
1.05
0.27
0.007 0.009 0.010
b
b
0.004
0.008
-----
12.40
8.00
0.21
-----
0.488
c
D
E
H
0.315
0.551
0.020
14.00
D
0.50
0.60
0.80
e
L
0.50
0.70
0.020 0.024 0.028
0.031
1
L
θ
0.000
0.00
0
0.10
5
0.004
5
Y
A
A
1 A
2
L
Y
0
3
3
θ
L
1
14.432-pin TSOP (8 x 20 mm)
H D
D
Dimension in Inches
Min. Nom. Max.
Dimension in mm
Max.
Symbol
Min. Nom.
__
__
__
__
A
1.20
0.15
1.05
0.047
0.006
c
__
__
0.002
0.037
0.05
0.95
A 1
A 2
b
0.041
0.009
1.00
0.20
0.15
0.039
M
e
0.007 0.008
0.17
0.12
0.23
0.17
E
c
0.005 0.006
0.720 0.724
0.007
0.728
0.10(0.004)
18.30 18.40 18.50
D
b
0.311 0.315
7.90
8.00
8.10
0.319
E
0.780 0.787
19.80
__
20.00 20.20
0.795
__
HD
e
__
__
0.020
0.50
0.016 0.020
0.40
__
0.50
0.60
__
L
0.024
__
__
0.031
0.80
__
L
1
A
__
0.000
0.004
5
0.10
5
0.00
1
Y
A2
A1
1
3
3
θ
θ
L
Y
L1
Note:
Controlling dimension: Millimeters
- 28 -
W49F002U
15. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
Renamed from W49F002/B/U/N
Add the 120 nS bin
A1
A2
Nov. 1999
Apr. 2000
-
1, 13 − 15, 20
14
Change Tbp(typ.) from 10 µS to 35 µS
Change Tec (max.) from 1 Sec to 0.2 Sec
A3
Dec. 2000
All
3, 9, 25
1, 25, 27
All
16,22
1, 25, 28
4
Modify some function description
Add in Hardware SID read note
Add in 32-pin TSOP (8 mm x 14 mm) package
Typo correction
Add Reset Timing Parameters and Diagram
Rename STOP (8 x 14 mm) as STSOP (8 x 14 mm)
Modify Low VDD Write Inhibit description
A4
A5
A6
Jan. 2001
Aug. 13, 2001
Feb. 21, 2002
13
Add in Software Product Identification and Boot Block
Lockout Detection Acquisition Flow
14
24
1, 24
Add in Boot Block Lockout Enable Acquisition Flow
Add HOW TO READ THE TOP MARKING
Addition 32 PLCC Lead free package
A7
April 19, 2005
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date: April 19, 2005
- 29 -
Revision A7
W49F002U
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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