W536020K [WINBOND]
VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series); VOICE / MELODY / LCD控制器（ ViewTalk TM系列）
| 型号： | W536020K |
| 厂家： | 
WINBOND |
| 描述： | VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series) |
| 文件： | 总16页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W536020K/030K/060K/090K/120K
VOICE/MELODY/LCD CONTROLLER
(ViewTalk TM Series)
Table of Contents-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 2
FEATURES................................................................................................................................. 3
BLOCK DIAGRAM ...................................................................................................................... 5
PAD DESCRIPTION ................................................................................................................... 6
ELECTRICAL CHARACTERISTICS........................................................................................... 9
5.1 Absolute Maximum Ratings............................................................................................... 9
5.2 DC Characteristics............................................................................................................. 9
5.3 AC Characteristics........................................................................................................... 11
6.
7.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 14
6.1 Sub Clock with RC Mode................................................................................................. 14
6.2 Sub Clock with Crystal Mode........................................................................................... 15
REVISION HISTORY................................................................................................................ 16
Publication Release Date: May 21, 2003
- 1 -
Revision A3
W536020K/030K/060K/090K/120K
1. GENERAL DESCRIPTION
The W536XXXK, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC)
with built-in speech unit, melody unit and 40seg * 8 com LCD driver unit which includes internal
regulator, pump circuit and dedicated one page LCD RAM. The 4-bit uC core contains dual clock
source, 4-bit ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8
interrupt sources and 8-level nesting for subroutine/interrupt applications. Speech unit, integrated as
a single chip with maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable
of expanding to 512 seconds speech addressed by external memory W55XXX with serial bus
interface.
It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides
dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power
dissipation. It is ideal for games, educational toys, remote controllers, watches, clocks and other
application products which incorporate both LCD display and speech.
Body
W536020K W536030K
W536060K
60 sec
W536090K
90 sec
W536120K
120 sec
Voice
20 sec
30 sec
8I/O, 8I, 8O
8I/O, 8I, 8O
4I/O,8I
(RA/RC/RD)
4I/O, 8I
(RA/RC/RD)
8io, 8i
(RA/RB/RC/RD)
I/O pad
(RA/RB/RC/RD/RE/
(RA/RB/RC/RD/
RF)
RE/RF)
WDT disable/Enable
(Mask Option)
Sub-clock
RC/XTAL mode
(Mask Option)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
RD port shared as
serial bus
Y(1)
Y(1)
N
N
N (2)
(Mask Option)
Tri-state serial bus
(Mask Option) (3)
Y
N
Y
N
N
Y
N
Y
Y
Cascaded Voice ROM
Y(1)
through serial bus (2)
Notes:
1. Share 3 pads of RD port (RD1/CLK, RD2/DATA and RD3/ADDR)
2. Dedicate serial bus 3 pads (CLK, DATA and ADDR) to interface with W55XXX. Cascaded Voice ROM can help to expand
voice up to 512 sec by W55XXX chip.
3. Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get
minimum power consumption in general.
- 2 -
W536020K/030K/060K/090K/120K
2. FEATURES
• Operating voltage: 2.4 volt ~ 5.5 volt
• Watch dog disabled/enabled by mask option
• Dual clock operating system
− Main clock with Ring/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
• Memory
− Program ROM (P-ROM): 16K × 20 (ROM Bank0)
− Data RAM (W-RAM): 1K × 4 bit
(RAM Bank 0 is 512 nibbles from 0: 000~0: 1FF and 0: 380~0:3FF are mapped to specia
register.
RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script
kernel)
− LCD RAM (L-RAM): 80× 4 bit (RAM Bank1 from 200~24F)
• Maximum 24 input/output pads
− Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external
memory W55XXX interface @W5360020/30K)
− Ports for output only: 8 pads (RE & RF port; W536090K/120K available only)
− Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536060/090K/
120K only)
• Power-down mode
− Hold mode (except for 32KHz oscillator)
− Stop mode (including 32KHz oscillator and release by RD or RC port)
• Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
− Three external interrupts (Port RC, RD, RA)
• One built-in 14-bit clock frequency divider circuit
• Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from
RC.0
• Built-in 18/14-bit watchdog timer for system reset.
• Powerful instruction sets
• 8-level subroutine (including interrupt) nesting
• LCD driver unit capability
− VLCD higher than (VDD -0.5V)
− Built-in voltage regulator to V2 pad
− 40 seg × 8 com
Publication Release Date: May 21, 2003
- 3 -
Revision A3
W536020K/030K/060K/090K/120K
− 1/8 or 1/4 duty, 1/4 or 1/3 bias, internal pump circuit option by special register
− COM 4~ 7 and SEG16~39 can be shared as general input/output by special register
− Either uC ROM or voice ROM used as LCD picture
• Speech function
− Provided 640K / 1M/ 2M/ 3M/ 4M bits Voice ROM for W536020K/030K/060K/090K/120K
based on 5 bits MDPCM algorithm
− Voice ROM (V-ROM) available for uC data or LCD picture data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory
W55XXX through serial bus.
• Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
• Can mix speech with melody
• Multi-engine controller
• Direct driving speaker/buzzer or DAC output
• Chip On Board available
- 4 -
W536020K/030K/060K/090K/120K
3. BLOCK DIAGRAM
V3,V5,V6
VHI
SEG0~39
COM0~7
DH1,DH2
V2
LCD DRIVER
LCDRAM
VLCD PUMP &
REGULATOR
VDD
80*4 bit
Data RAM
1K*4 bit
TEST
PORT RA
RA0~3
TONE
ACC
ALU
ROM
PORT RB
PORT RC
RB0~3
16K*20Bit
RC0~3
RD0~3
PORT RD
PORT RE
PORT RF
PC
RE0~3
RF0~3
Special Register
IEF
HEF
SPC MLD
MR0
LPX0 LPX1 LPX2
LPX4 LPX5
LPY0
PEF
EVF
HCF
FLAG0
STACK
(8 Levels)
FLAG1 PM0
PSR0
LPX3
LPY1
ADDR
CLK
DATA
Parallel
to Serial
ROSC
SPC_bus
y
MDPCM
Speech
SPC_pla
y
Interrupt ,Hold &
Stop Control
Timer 1
Timer 0
PWM1/DAC
PWM2
MLD_busy
MLD_play
Voice ROM
(640K/1M/3M/
4M)
PWM/
DAC
MIX
VSS
VDDP
Block
Timing
Generator
Watch Dog
Divide
Dual
VSSP
RES
Tone
Melody
XIN XOUT X32I X32O
Publication Release Date: May 21, 2003
Revision A3
- 5 -
W536020K/030K/060K/090K/120K
4. PAD DESCRIPTION
SYMBOL
I/O
FUNCTION
Input pad for main clock oscillator. It can be connected to crystal when
crystal mode is selected (SCR0.2 = 1), otherwise connect a resistor to
V
DD to generate main system clock while Ring mode is selected (SCR0.2
XIN/RXIN
I
= 0 and default). Oscillator can be enabled or stopped by set SCR0.1 to
1 or clear to 0 separately. External capacitor connects to start oscillation
and get more accurate clock when crystal mode
Output pad for oscillator which is connected to another crystal pad when
in crystal mode. External capacitor connects to start oscillation when in
crystal mode.
XOUT
O
I
32.768 KHz crystal input pad or external resistor node 1 by mask
option. External 15~20pF capacitor connects to start oscillation and get
more accurate clock when in crystal mode.
X32I/RSUB1
X32O/RSUB2
32.768 KHz crystal output pad or external resistor node 2 by mask
option. External 15~20pF capacitor connects to start oscillation when in
crystal mode.
O
General Input/Output port specified by PM1 register. If output mode is
selected, PM0 register bit 0 can be used to specify CMOS/NMOS driving
capability option. Initial state is input mode. RA3 may be uses as TONE
if bit 0 of MR0 special register is set to logic 1. An interrupt source.
RA0 ~ RA3/TONE
(9)
I/O
General Input/Output port specified by PM2 register. If output mode is
RB0 ~ RB3
(9)
I/O selected, PM0 register bit 1 can be used to specify CMOS/NMOS driving
capability option. Initial state is input mode (W536060K/090K/120K only.)
4-bit schmitter input with internal pull high option specified by PM3
RC0 ~ RC3
register bit 2. Each pad has an independent interrupt capability specified
I
by PEFL special register. Interrupt and STOP mode wake up source.
RC0 is also the external event counter source of Timer1.
4-bit schmitter input port with internal pull high option specified by PM3
register bit 3. Each pad has an independent interrupt capability specified
by PEFH special register. Interrupt and STOP mode wake up source.
RD1~3 will be shared as the external memory W55XXX interface pads
RD0
RD1/CLK
RD2/DATA
RD3/ADDR
(4)
while RD port shared as serial bus mask option is enabled
@W536020K/030K.
I
For W536020K/030K only, "Tri-state serial bus" mask option can use to
float ADDR/CLK/DATD while "RD port shared as serial bus" mask option
is enabled.
RE0~RE3
(9)
RF0~RF3
(9)
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS
driving capability option. (W536090K/120K only)
O
O
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS
driving capability option. (W536090K/120K only)
- 6 -
W536020K/030K/060K/090K/120K
PAD Description, continued
SYMBOL
I/O
FUNCTION
I
I
System reset pad, active low with internal pull-high resistor.
Test pad. Active high with internal pull low resistor.
RES
TEST
Connect resistor to VDD pad to generate speech or melody playing
clock source.
ROSC
I
While speech or melody is active, PWM1/DAC is speaker direct driving
output or DAC output controlled by voice output file.
While speech or melody is active, PWM2 is another speaker direct
driving output.
External serial memory address write clock for voice extension
(W536120K only).
External serial memory address read clock for voice extension.
(W536120K only).
PWM1/DAC
PWM2
O
O
O
O
ADDR (5)
CLK (5)
External serial memory data in/out for voice extension (W536120K
only).
DATA (5)
I/O
O
Dedicated LCD segment output pads.
SEG0−SEG15
SEG16/PORTN.0
LCD segment output pads, and can be shared as general output by
register LCDM3 bit 1. Default function is segment pad.
O/O
O/I
SEG19/PORTN.3
SEG20/PORTM.0
LCD segment output pads, and can be shared as general input by
register LCDM3 bit 0. Default function is segment pad and PM5.1=0 to
inhibit LCD waveform abnormal.
SEG23/PORTM.3
SEG24/PORTL.0
LCD segment output pads, and can be shared as general output by
register LCDM2 bit 3. Default function is segment pad.
O/O
O/I
SEG27/PORTL.3
SEG28/PORTK.0
LCD segment output pads, and can be shared as general input by
register LCDM2 bit 2. Default function is segment pad and PM5.0=0 to
inhibit LCD waveform abnormal.
SEG31/PORTK.3
LCD segment output pads, and can be shared as general input/output
by register LCDM2 bit 1. PM4 register is used to select input or output
while shared I/O function is active. Default function is segment pad and
PM4.3 = 0 to inhibit LCD waveform abnormal.
SEG32/PORTJ.0
O/IO
SEG35/PORTJ.3
LCD segment output pads, and can be shared as general input/output
by register LCDM2 bit 0. PM4 register is used to select input or output
while shared I/O function is active. Default function is segment pad and
PM4.2 = 0 to inhibit LCD waveform abnormal.
SEG36/PORTI.0
O/IO
SEG39/PORTI.3
Publication Release Date: May 21, 2003
- 7 -
Revision A3
W536020K/030K/060K/090K/120K
PAD Description, continued
SYMBOL
I/O
FUNCTION
LCD common signal output pads either 1/8 duty or 1/4duty. The LCD
frame rate is controlled by LCDM1 register, and default value LCDM1 =
0111b with 64Hz frame rate.
O
COM0−COM3
COM4/PORTO.0
LCD common signal output pads, or shared as general input by register
O/I LCDM3.2 when in 1/4 duty mode. Default function is common function
and PM5.2 = 0 to inhibit LCD waveform abnormal.
COM7/PORTO.3
Connection terminal for voltage double capacitor with 0.1uF. The DH2
DH1, DH2 (6)
O
connects to capacitor positive node and DH1 negative node if polar
capacitor is used.
Connect to V6 (LCD's VLCD) or VDD which has higher voltage, to make
sure there is no any abnormal leakage current appearance.
VHI
I
LCD COM/SEG output driving voltage. Need an external 0.1uF
capacitor when 1/4 bias. (LCDM0.1 = 1)
LCD COM/SEG output driving voltage. Need an external 0.1uF
capacitor to every pad terminal.
V3
O
O
V5 V6 (6)
Voltage regulator output pad. An external capacitor is a must. Output
level can be controlled from 0~Fh by LCDM4 register. If internal pump is
enabled (LCDM3.3 = 0 and default value), LCD operating voltage
(VLCD) will be 3*V2 or 4*V2 depending on 1/3 bias or 1/4 bias. A
limitation should be noted that VLCD must be higher than (VDD -0.5v) to
avoid chip leakage current. While external reference voltage is selected
(LCDM3.3 = 1), V2 pad input voltage can not be over 1.5 Volt to inhibit
chip damage.
V2 (6)
I/O
VSSP (7)
VSS (7)
VDDP (7)
VDD (7)
I
I
I
I
Power ground for PWM or DAC playing output.
Power ground
Power source for PWM or DAC playing output.
Power Source
Notes:
(4)
(5)
(6)
(7)
RD1~3 are shared as CLK/DATA/ADDR to interface with W55XXX @W536020K/030K.
@W536120K only
0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm * 0.5mm.
External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation
properly, please bond all VDD, VDDP, VSS and VSSP pads and connect VSS and VSSP from chip outside PCB circuit.
(8)
(9)
VHI pad is bonded to V6 or VDD.
When working at NMOS open drain mode, external pull high voltage can't bigger than VDD to avoid leakage current.
- 8 -
W536020K/030K/060K/090K/120K
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
PARAMETER
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
RATING
-0.3 to +7.0
-0.3 to +7.0
120
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
5.2 DC Characteristics
(VDD−VSS = 3.0V, no load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD panel on with
dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
Op. Voltage
Op. Current
SYM. CONDITIONS
VDD
MIN.
2.4
-
TYP. MAX.
UNIT
V
µA
5.5
IOP1
Dual clock with crystal
600
600
700
Dual clock with Ring
(No Load, no Voice, no)
Melody)
700
type
Sub-clock only, LCD off
Sub-clock only, LCD on
40
70
50
90
Hold Mode Current
(No Load, LCD OFF)
Hold Mode Current
(No load, LCD ON)
Stop Mode Current
IOP2
IOP3
Sub-clock active only
Sub-clock active only
3
5
µA
35
uA
IOP4
IoH1
LCD auto off
Vout = 2.7V
1
µA
CLK/ADDR Output High
-0.8
mA
Current
CLK/ADDR Output low
Current
IoL1
Vout = 0.4V
0.8
mA
Input Low Voltage
Input High Voltage
VIL
VIH
-
-
VSS
0.7
-
-
0.3
1
VDD
VDD
Port RA, RB, RE, RF Output
VABL
IOL = 2.0 mA
-
-
-
0.4
-
V
V
Low Voltage
Port RA, RB, RE, RF Output
High Voltage
VABH IOH = -2.0 mA
2.4
Publication Release Date: May 21, 2003
Revision A3
- 9 -
W536020K/030K/060K/090K/120K
DC Characteristics, continued
PARAMETER
SYM. CONDITIONS
MIN.
TYP. MAX.
UNIT
Pull-up Resistor
RCD
Port RC, RD
200
300
400
KΩ
Share Output RI, RJ, RL,
RN, RP Sink Current
IOL3
VOL= 0.4V
-300
50
uA
RES Pull-up Resistor
PWM1/2 Source Current (8)
(RLOAD =8Ω between PWM1
And PWM2)
RRES
ISPH
-
100
-20
-70
-110
-135
20
200
KΩ
mA
Volume Option = 00
Volume Option = 01
Volume Option = 10
Volume Option = 11
Volume Option = 00
Volume Option = 01
PWM1/2 Sink Current (8)
(RLOAD = 8Ω between PWM1
And PWM2)
ISPL
mA
70
Volume Option = 10
Volume Option = 11
110
135
-5
DAC output Current
LCD Supply Current
COM/SEG On Resistor
V2 Pad Output Voltage
IDAC VDD = 3V, RL = 100ohm
-4
-
-6
-
mA
µA
Ω
ILCD
RON
VRR
No Load, All Seg. ON
OH = ±50 µA
50
5K
10K
1.45
I
Depended on LCDM4
No Load
0.7
V
V2 Pad Output Deviation (9)
V2 Pad Voltage Step
%
± 5
VD1
VR2
LCDM4 increased 1
50
mV
V6 Pad Output Voltage
(LCD's VLCD depended on
2.85
* V2
3.8
2.9
2.95
* V2
3.9
* V2
1.5
VLCD 1/3 Bias & no load
V
* V2
3.85
* V2
LCDM4 register) (9)
1/4 Bias & no load
* V2
V2 input voltage
VEXT LCDM3.3 = 1
V
Notes:
(8)
(9)
PWM current deviation will be ±20%.
Deviation is governed by LCD dot size. More larger LCD dot will get larger deviation..
- 10 -
W536020K/030K/060K/090K/120K
5.3 AC Characteristics
(VDD−VSS = 3.0V, no load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD on with dot size
0.5mm*0.5mm; unless otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN.
TYP. MAX. UNIT
Crystal type and X32IN
and X32O with 17pF
external cap.
Sub-clock Frequency
FSUB
32768
Hz
Main-clock Frequency
Chip Operation Frequency
FM
Ring type/Crystal type
SCR0.0 = 1, FSYS = FSUB
SCR0.0 = 0; FSYS = FMAIN 400K
400K
-
32768
-
4M
Hz
Hz
FOSC
4M
Instruction Cycle Time
Reset Active Width
Interrupt Active Width
Main clock Ring frequency
(10)
TCYC
TRAW
TIAW
One machine cycle
FOSC = 32.768 KHz
FOSC = 32.768 KHz
RXIN = 680KΩ
-
4/FOSC
-
-
-
-
S
1
1
µS
µS
Hz
-
FRXIN
1M
2M
3M
4M
32
RXIN = 330K Ω
RXIN = 200KΩ
RXIN = 130KΩ
Sub-Clock RC Oscillator
FRSUB
FSTOP
KHz
S
RSUB = 680KΩ
Sub-Clock Oscillation Stable
Time @ Cold Start
0.8
1
RSUB = 680KΩ
f(3V)− f(2.4V)
∆f
f
Frequency Deviation of
10
%
%
main-clock FRXIN ≤ 2MHz
f(3V)
f(3V)− f(2.4V)
∆f
f
Frequency Deviation of
15
20
main-clock FRXIN = 3 MHz
f(3V)
f(3V)− f(2.4V)
∆f
f
Frequency Deviation of
%
MHz
%
main-clock FRXIN = 4 MHz
f(3V)
ROSC Frequency
FROSC
3
ROSC=680KΩ
f(3V)− f(2.4V)
∆f
f
Frequency Deviation of
FROSC = 3MHz
7.5
f(3V)
Frame frequency
FLCD
LCDM1 = 0111 b(default)
64
Hz
Notes:
(10) The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
Publication Release Date: May 21, 2003
Revision A3
- 11 -
W536020K/030K/060K/090K/120K
Iop Vs. Main clock RC mode
1000
800
600
400
200
0
3V
4.5V
Iop (uA)
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44
40
36
32
28
24
20
3V
4.5V
)
hZ
(K
b
u
Fs
560 620 680 750 820
1K
Rsub (Kohm)
- 12 -
W536020K/030K/060K/090K/120K
Main Freq Vs. Rxin
6
5
4
3
2
1
0
2.4V
3v
4.5V
5.5V
Fmain
(MhZ)
130 150 160 200 330 680 2K 3K
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
4.5
4
3.5
3
3V
Fr
eq
(M
4.5V
h
Z)
2.5
2
470
560
680
910
ROSC (Kohm)
Publication Release Date: May 21, 2003
Revision A3
- 13 -
W536020K/030K/060K/090K/120K
6. TYPICAL APPLICATION CIRCUITS
6.1 Sub Clock with RC Mode
1/4 bias, VLCD = 4.5V, VDD = 2.4~3.6V
40SEG*8COM
LCD Panel
VDDP
SPEAKER
Q1
8050
(*3)
VDDP
470
(*2)
R5
SWITCH
PWM1/DAC
VDDP
SPEAKER
___
RES
C4
(*4)
C6
PWM2
CLK/RD1
DATA/RD2
ADDR/RD3
VDDP
W55MXX
VDD W536XXXK
R4
C1
Rosc
DH1
DH2
C13
V6
R1
C2 C3
Battery
XIN
R3
C5
(*4)
C12
V5
C11
V3
C10
V2
X32IN
(*1)
R2
X32IO
C9
V6
VHI
VDD
(*5)
COMPONENT
C1
C2~C4 C5~C6 C7~C8 C9~C13
R1
R2
R3
R4
680KΩ/1MHz
350KΩ/2MHz
215KΩ/3MHz
150KΩ/4MHz
Value
100pF
4.7uF
0.1uF
0.1uF
-
-
0.1~1uF 680KΩ
0.1~1uF 680KΩ
655KΩ
675KΩ
100Ω
V
DD = 3V
750KΩ/1MHz
350KΩ/2MHz
225KΩ/3MHz
160KΩ/4MHz
Value
DD = 4.5V
100pF
4.7uF
100Ω
V
Notes:
1. C9~C13 depends on LCD panel dot size.
2. Option R5 equals to 100Ω if high noise immunity is needed.
3. For DAC option application.
4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best.
Under the mask ROM version, C5 and C6 can be skipped.
5. Sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit.
- 14 -
W536020K/030K/060K/090K/120K
6.2 Sub Clock with Crystal Mode
1/3 bias, VLCD = 3V, VDD = 3.6~5.4V
40SEG*4COM
LCD Panel
VDDP
Q1
SPEAKER
VDDP
R5
8050
(*3)
470
(*2)
SWITCH
C4
___
PWM1/DAC
VDDP
RES
(*4)
PWM2
C6
SPEAKER
VDDP
CLK/RD1
DATA/RD2
ADDR/RD3
W55MXX
VDD W536XXXK
C1
R4
C3
Rosc
R1
C2
Battery
XIN
DH2
R3
DH1
C5
C12
(*4)
V5
X32IN
C11
V3
C7
32K
(*1)
C10
X32IO
V2
C9
C8
V6
VHI
VDD
(*5)
Component
C1
C2~C4
C5~C6
C7~C8
C9~C12
R1
R2
R3
R4
680KΩ/1MHz
350KΩ/2MHz
215KΩ/3MHz
150KΩ/4MHz
750KΩ/1MHz
350KΩ/2MHz
225KΩ/3MHz
160KΩ/4MHz
Value
100pF
4.7uF
4.7uF
0.1uF
15~30PF 0.1~1uF
15~30PF 0.1~1uF
680KΩ
680KΩ
-
100Ω
V
DD = 3V
Value
DD = 4.5V
100pF
0.1uF
-
100Ω
V
Notes:
1. C9~C12 depends on LCD panel dot size.
2. Option R5 equals to 100Ω if high noise immunity is needed.
3. For DAC option application.
4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to 5. pad PWM/PWM2 at its best.
Under the mask ROM version, C5 and C6 can be skipped.
5. Sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit.
Publication Release Date: May 21, 2003
- 15 -
Revision A3
W536020K/030K/060K/090K/120K
7. REVISION HISTORY
VERSION
DATE
WRITER
DESCRIPTION
A1
A2
A3
SEP. 18, 2000
NOV. 24, 2000
May 21, 2003
Jimmy Chen
Jimmy Chen
Jimmy Chen
ꢀ Application circuit modify
ꢀ Application circuit modify
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Information contained in this publication regarding device applications and the like is intended for suggestion
only and may be superseded updates. No representation or warranty is given and no liability is assumed by
Winbond Electronics Corp. with respect to the accuracy or use of such information, or infringement of patents
or other intellectual property.
- 16 -
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