W55212B [WINBOND]

Standard SRAM, 256KX1, 80ns, CMOS, PDIP18;
W55212B
型号: W55212B
厂家: WINBOND    WINBOND
描述:

Standard SRAM, 256KX1, 80ns, CMOS, PDIP18

静态存储器 光电二极管 内存集成电路
文件: 总7页 (文件大小:80K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
W55212B  
SERIAL VOICE SRAM (256K 1 BIT)  
´
GENERAL DESCRIPTION  
The W55212B is a normal speed, low power CMOS static RAM organized as 256K ´ 1 bit that  
operates on a single 5V power supply. Manufactured using Winbond's high performance CMOS  
technology, the W55212B is designed for extensive use in voice recording applications  
FEATURES  
· Single 3.6V to 5.5V power supply  
· Low power consumption  
· Fully static operation  
· Low data retention voltage  
· Easy to cascade  
PIN CONFIGURATION  
NC  
NC  
NC  
NC  
NC  
NC  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
NC  
NC  
NC  
NC  
V
DD  
V
SS  
CLK  
CS  
DATA  
ADDR  
W/R  
11  
10  
EOP  
Publication Release Date: September 1996  
Revision A1  
- 1 -  
W55212B  
PIN DESCRIPTION  
NO.  
6
PIN  
I/O  
DESCRIPTION  
VDD  
PWR Positive power supply  
7
I
CS  
Chip-inhibit when CS = 1; chip-select when CS = 0 or open (with internal  
pull-low resistor)  
8
I
W/R  
EOP  
ADDR  
DATA  
CLK  
Write-in control when W/R = 1, read-out control when W/R = 0  
End signal output  
9
O
I
10  
11  
12  
13  
Clock input for start address  
B
I
Bidirectional data pin  
Clock input for address increment  
VSS  
PWR Ground  
BLOCK DIAGRAM  
EOP  
W/R  
CS  
Control  
Circuits  
SRAM  
256K x 1 Bit  
DATA  
ADDR  
CLK  
Address  
Controller  
FUNCTIONAL DESCRIPTION  
· TRUTH TABLE  
MODE  
DATA PIN  
VDD CURRENT  
CS  
H
W/R  
X
Note selected  
Write  
High Z  
Data in  
Data out  
ISB  
IOP  
IOP  
L
H
L
L
Read  
· When the chip is unselected, the W/R signal will be transmitted to the EOP pin.  
- 2 -  
W55212B  
· Before a read or write operation, the address counter must be reset by sending an ADDR pulse and  
DATA = 0.  
· After power on, the read operation is disabled, and a read operation may be performed only after a  
write operation is completed.  
· In write-in operation, the EOP signal will change from low to high and remain high when the final  
address of the chip is encountered. It will change to low again with the next ADDR pulse.  
· In read-out operation, the EOP pin will generate one pulse signal when the final address of the  
SRAM chip is encountered.  
The timing of the start address loading in write-in/read-out operation is shown below:  
· Load start address for write-in/read-out operation:  
CS  
¡ K  
ADDR  
CLK  
¡ K  
DATA  
EOP  
· Write-in operation:  
CS  
W/R  
ADDR  
¡ K  
CLK  
¡ K  
DATA  
256K  
EOP  
· Read-out operation:  
Publication Release Date: September 1996  
- 3 -  
Revision A1  
W55212B  
CS  
W/R  
ADDR  
¡ K  
¡ K  
CLK  
DATA  
256K  
TEP  
EOP  
· No operation (standby):  
CS  
W/R  
EOP  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Supply Voltage (VDD- VSS)  
Input Voltage  
SYMBOL  
RATING  
-0.3 to +5.5  
UNIT  
-
V
V
VI  
VSS -0.2 to VDD +0.2  
VSS to VDD  
Output Voltage  
VO  
TA  
TS  
V
Operating Temperature  
Storage Temperature  
0 to +70  
°C  
°C  
-55 to +150  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability  
of the device.  
DC CHARACTERISTICS  
- 4 -  
W55212B  
TA = 25° C, VDD = 5.0V, VSS = 0.0V  
PARAMETER  
SYMBOL  
CONDITIONS  
LIMIT  
TYP. MAX.  
UNIT  
MIN.  
3.6  
-
Operating Voltage  
Operating Current  
VDD for Data Retention  
VDD  
IOP  
-
5.0  
5.5  
15  
V
mA  
V
Fc = 1 MHz  
-
-
VDR  
2.4  
5.5  
CS ³ VDD -0.2V  
Data Retention Current  
Standby Current  
IDDDR  
-
-
10  
mA  
VDD ³ 3V, CS ³ 2.8V  
ISB  
VIH  
VIL  
-
-
-
-
2
-
10  
6.0  
mA  
Input Voltage (for ADDR,  
CLK, W/R and CS pins)  
2.8  
-0.5  
V
-
+0.8  
IIH  
VI = 5.0V  
-
-
5
mA  
Input Current (for CS)  
Output Current (for EOP)  
IOH  
IOL  
VO = 4.0V  
VO = 0.8V  
4
6
-
-
mA  
-4  
-8  
AC CHARACTERISTICS  
Ta = 25° C, VDD = 5.0V, VSS = 0.0V  
PARAMETER  
SYM. CONDITIONS MIN. TYP. MAX. UNIT  
Clock Frequency (for CLK and ADDR)  
Data Hold Time  
FC  
TWH  
TRH  
TAH  
TRA  
TWS  
TAS  
TEP  
TH  
-
-
0
-
-
-
-
-
-
-
-
-
1
-
MHz  
nS  
ns  
Write mode  
Data Hold Time  
Read mode  
0
-
Data Hold Time (for ADDR)  
Data Access Time  
-
0
-
nS  
nS  
nS  
nS  
nS  
nS  
Read mode  
-
80  
-
Data Set up Time  
Write mode  
250  
250  
100  
400  
Data Set up Time (for ADDR)  
EOP Pulse Width (for ADDR)  
-
-
Read mode  
-
-
High Level Duration of Clock for CLK and  
ADDR  
-
Low Level Duration of Clock for CLK and  
ADDR  
TL  
-
600  
-
-
nS  
TSUR  
TSUW  
TD  
-
-
-
300  
300  
1
-
-
-
-
-
-
nS  
nS  
mS  
W/R Signal Set up Time for Write Mode  
W/R Signal Set up Time for Write Mode  
Time Width Between ADDR and CLK  
Clock  
TYPICAL APPLICATION CIRCUIT (For reference only)  
Publication Release Date: September 1996  
Revision A1  
- 5 -  
W55212B  
W51205901A/  
W51205903A  
W55212B  
DATA  
DATA  
CLK  
CLK  
ADDR  
ADDR  
W/R  
CS  
W/R  
EOP  
CS  
EOP  
W51205901A/  
W51205903A  
W55212B  
W55212B  
DATA  
W55212B  
DATA  
W55212B  
DATA  
DATA  
DATA  
CLK  
CLK  
CLK  
CLK  
CLK  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
W/R  
CS  
W/R  
CS  
W/R  
W/R  
CS  
W/R  
CS  
EOP  
EOP  
CS  
EOP  
EOP  
EOP  
* W51205901A/W51205903A substrate connected to VSS for C.O.B.  
* W55212B substrate connected to VDD for C.O.B.  
- 6 -  
W55212B  
Winbond Electronics (H.K.) Ltd.  
Winbond Electronics North America Corp.  
Headquarters  
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.  
123 Hoi Bun Rd., Kwun Tong,  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5792697  
Winbond Microelectronics Corp.  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
Winbond Systems Lab.  
2730 Orchard Parkway, San Jose,  
CA 95134, U.S.A.  
TEL: 1-408-9436666  
FAX: 1-408-9436668  
http://www.winbond.com.tw/  
Voice & Fax-on-demand: 886-2-7197006  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-7190505  
FAX: 886-2-7197502  
Note: All data and specifications are subject to change without notice.  
Publication Release Date: September 1996  
Revision A1  
- 7 -  

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