W681513_05 [WINBOND]
5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB APPLICATIONS; 5V单路语音频带编解码器， USB应用
| 型号： | W681513_05 |
| 厂家： | 
WINBOND |
| 描述： | 5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB APPLICATIONS |
| 文件： | 总35页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W681513
5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB
APPLICATIONS
Data Sheet
Publication Release Date: October, 2005
- 1 -
Revision A11
W681513
1. GENERAL DESCRIPTION
The W681513 is a single channel PCM CODEC with pin-selectable μ-Law or A-Law companding
dedicated to the USB accessory market by supporting a derivative 2MHz clock. The device is
compliant with the ITU G.712 specification. It operates from a single +5V power supply and is
available in 20-pin SOP package option. Functions performed include digitization and reconstruction
of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are
compliant with ITU G.712 specification. W681513 performance is specified over the industrial
temperature range of –40°C to +85°C.
The W681513 includes an on-chip precision voltage reference and an additional power amplifier,
capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer
protocol supports both long-frame and short-frame synchronous communications for PCM
applications, and IDL and GCI communications for ISDN applications. W681513 accepts 2MHz
master clock rate, and an on-chip pre-scaler automatically determines the division ratio for the
required internal clock.
Applications
2. FEATURES
•
Soft phones running on a PC (VoInternet):
•
•
Single +5V power supply
o
o
USB Phones
Typical power dissipation of 30 mW,
power-down mode of 0.5 μW
USB to PSTN Gateway
•
•
USB Microphones
•
•
Fully-differential analog circuit design
USB Headset for PC and Game Consoles
On-chip precision reference of 1.575 V for
a 0 dBm TLP at 600 Ω (775mVRMS
)
•
•
•
•
•
Push-pull power amplifiers with external
gain adjustment with 300 Ω load capability
Master clock rate supports 2.000MHz
clock for USB applications
Pin-selectable
companding (compliant with ITU G.711)
μ-Law
and
A-Law
CODEC A/D and D/A filtering compliant
with ITU G.712
Industrial temperature range (–40°C to
+85°C)
•
•
Package: 20-pin SOP (SOG)
Pb-Free / RoHS package option available
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W681513
3. BLOCK DIAGRAM
BCLKR
FSR
PAO+
PAO-
PAI
RO+
AO
PCMR
G.712 CODEC
BCLKT
G.711 /A-Law
μ
AI+
AI-
FST
PCMT
/A-Law
μ
256 kHz
VAG
MCLK
Voltage reference
Pre-Scaler
8 kHz
2000 kHz,
Power Conditioning
Publication Release Date: October, 2005
Revision A11
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W681513
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Transmit Path ................................................................................................................................8
7.2. Receive Path .................................................................................................................................9
7.3. Power Management.....................................................................................................................10
7.3.1. Analog and Digital Supply.....................................................................................................10
7.3.2. Analog Ground Reference Voltage Outpt.............................................................................10
7.4. PCM Interface..............................................................................................................................10
7.4.1. Long Frame Sync..................................................................................................................10
7.4.2. Short Frame Sync .................................................................................................................11
7.4.3. General Circuit Interface (GCI) .............................................................................................11
7.4.4. Interchip Digital Link (IDL).....................................................................................................12
7.4.5. System Timing ......................................................................................................................12
8. TIMING DIAGRAMS.......................................................................................................................... 13
9. ABSOLUTE MAXIMUM RATIINGS................................................................................................... 20
9.1. Absolute Maximum Ratings.........................................................................................................20
9.2. Operating Conditions...................................................................................................................20
10. ELECTRICAL CHARACTERISTICS............................................................................................... 21
10.1. General Parameters ..................................................................................................................21
10.2. Analog Signal Level and Gain Parameters ...............................................................................22
10.3. Analog Distortion and Noise Parameters ..................................................................................23
10.4. Analog Input and Output Amplifier Parameters.........................................................................24
10.5. Digital I/O ...................................................................................................................................26
10.5.1. μ-Law Encode Decode Characteristics...............................................................................26
10.5.2. A-Law Encode Decode Characteristics ..............................................................................27
10.5.3. PCM Codes for Zero and Full Scale ...................................................................................28
10.5.4. PCM Codes for 0dBm0 Output ...........................................................................................28
11. TYPICAL APPLICATION CIRCUITS .............................................................................................. 29
12. PACKAGE SPECIFICATION .......................................................................................................... 32
12.2. 20L SOP (SOG)-300mil.............................................................................................................32
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W681513
13. ORDERING INFORMATION........................................................................................................... 33
14. VERSION HISTORY ....................................................................................................................... 34
Publication Release Date: October, 2005
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Revision A11
W681513
5. PIN CONFIGURATION
VAG
AI+
AI-
RO+
RO+
PAI
PAO-
PAO+
VDD
1
2
20
19
18
17
16
15
14
13
12
11
3
AO
4
SINGLE
CHANNEL
CODEC
/A-Law
5
μ
VSS
6
FST
PCMT
BCLKT
MCLK
FSR
7
8
PCMR
BCLKR
PUI
9
10
SOP
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W681513
6. PIN DESCRIPTION
Pin
Name
Pin Functionality
No.
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
RO+
2
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
PAI
3
4
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
7
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.
FSR
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
9
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD
.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
BCLKT
PCMT
FST
11
12
13
14
15
16
System master clock input supporting 2000 kHz only.
PCM transmit bit clock input pin.
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
This is the supply ground. This pin should be connected to 0V.
VSS
μ/A-Law
Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law
companding is selected when this pin is tied to VSS.
AO
AI-
17
18
19
20
Analog output of the first gain stage in the transmit path.
Inverting input of the first gain stage in the transmit path.
Non-inverting input of the first gain stage in the transmit path.
AI+
VAG
Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin
becomes high impedance when the chip is powered down.
Publication Release Date: October, 2005
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Revision A11
W681513
7. FUNCTIONAL DESCRIPTION
W681513 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a
complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply
with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W681513. The chip consists of a
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample
rate with the external frame sync frequency. The power conditioning block provides the internal
power supply for the digital and the analog section, while the voltage reference block provides a
precision analog ground voltage for the analog signal processing. The main CODEC block diagram
is shown in section 3.
+
-
-
VAG
PAO+
-
PAO
PAI
Receive Path
8
+
-
D/A
+
RO
Converter
fC
= 3400Hz
Smoothing
Filter
Smoothing
/A-
μ
Filter
Control
Transmit Path
AO
AI+
8
A/D
+
Converter
-
f
C
f
= 3400Hz
C
= 200Hz
-
AI
μ
-
/A
HighPass
Filter
Ant
-Aliasing
Ant-Aliasing
Filter
Control
Filter
Figure 7.1 The W681513 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The device has an input operational amplifier whose
output is the input to the encoder section. If the input amplifier is not required for operation it can be
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected
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W681513
as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see
Table 7.1).
AI+
Input Amplifier
Input
VDD
Powered Down
Powered Up
AO
1.2 to VDD-1.2
VSS
AI+, AI-
AI-
Powered Down
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG
.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A-
Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression
format can be selected according to Table 7.2.
Format
μ/A-Law Pin
VSS
VDD
A-Law
μ-Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
sample rate supplied by the external frame sync FST.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO+. The RO+ output can be externally connected to the
PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By
using external resistors (see section 11 for examples), various gain settings of this output amplifier
Publication Release Date: October, 2005
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Revision A11
W681513
can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting
PAI to VDD
.
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681513 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 μF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
2.000 MHz
VSS
8 kHz
VSS
Long or Short Frame Sync
ISDN GCI with active channel B1
ISDN GCI with active channel B2
ISDN IDL with active channel B1
ISDN IDL with active channel B2
VSS
VDD
VDD
VSS
VDD
VDD
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 2.000 MHz clock and connecting the FSR or FST pin to the 8 kHz frame
sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on
the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is
- 10 -
W681513
held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame
Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125
μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will
become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is
being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync
signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The
internal decision logic will determine whether the next frame sync is a long or short frame sync, based
on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for
two frame sync cycles after every power down state. More detailed timing information can be found in
the interface timing section.
7.4.2. Short Frame Sync
The W681513 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681513 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681513 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins: FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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Revision A11
W681513
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 2000 kHz master clock rate only. The system clock is supplied through the
master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is
used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. If the Frame Sync
is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present,
the W681513 will enter the low power standby mode. Another way to power down is to set the PUI pin
to low. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
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W681513
8. TIMING DIAGRAMS
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFSL
FST
TFTRH
TFTRS
TFTFH
TBCKH
TBCKL
BCLKT
PCMT
0
1
2
3
4
5
6
7
8
0
1
TFDTD
TBDTD
THID
THID
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TFS
TFSL
FSR
TFRRH
TFRRS
TFRFH
TBCKH
TBCKL
BCLKR
PCMR
0
1
2
3
4
5
6
7
8
0
1
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
LSB
MSB
TDRH
TDRS
Figure 8.1 Long Frame Sync PCM Timing
Publication Release Date: October, 2005
Revision A11
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W681513
SYMBOL
1/TFS
DESCRIPTION
MIN
---
TYP
MAX
UNIT
kHz
sec
kHz
ns
FST, FSR Frequency
8
---
TFSL
FST / FSR Minimum LOW Width 1
BCLKT, BCLKR Frequency
BCLKT, BCLKR HIGH Pulse Width
BCLKT, BCLKR LOW Pulse Width
TBCK
2000
50
1/TBCK
TBCKH
TBCKL
---
---
---
---
2000
---
50
---
ns
TFTRH
BCLKT 0 Falling Edge to FST Rising 20
Edge Hold Time
---
ns
TFTRS
TFTFH
TFDTD
TBDTD
THID
FST Rising Edge to BCLKT 1 Falling 80
edge Setup Time
---
---
---
---
---
---
---
60
60
60
ns
ns
ns
ns
ns
BCLKT 2 Falling Edge to FST Falling 50
Edge Hold Time
FST Rising Edge to Valid PCMT Delay ---
Time
BCLKT Rising Edge to Valid PCMT ---
Delay Time
Delay Time from the Later of FST 10
Falling Edge, or
BCLKT 8 Falling Edge to PCMT Output
High Impedance
TFRRH
TFRRS
TFRFH
TDRS
BCLKR 0 Falling Edge to FSR Rising 20
Edge Hold Time
---
---
---
---
---
---
---
---
---
---
ns
ns
ns
ns
ns
FSR Rising Edge to BCLKR 1 Falling 80
edge Setup Time
BCLKR 2 Falling Edge to FSR Falling 50
Edge Hold Time
Valid PCMR to BCLKR Falling Edge
Setup Time
0
TDRH
PCMR Hold Time from BCLKR Falling 50
Edge
Table 8.1 Long Frame Sync PCM Timing Parameters
1 TFSL must be at least ≥ TBCK
- 14 -
W681513
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFTFH
TFTFS
FST
TFTRS
TFTRH
TBCKH
TBCKL
BCLKT
PCMT
0
1
-1
0
1
2
3
4
5
6
7
8
TBCK
TBDTD
TBDTD
THID
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
TFS
TFRFH
TFRFS
FSR
TFRRS
TFRRH
TBCKH
TBCKL
BCLKR
PCMR
0
1
-1
0
1
2
3
4
5
6
7
8
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TDRH
TDRS
Figure 8.2 Short Frame Sync PCM Timing
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Revision A11
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W681513
SYMBOL
1/TFS
DESCRIPTION
MIN
---
TYP
8
MAX
---
UNIT
kHz
kHz
ns
FST, FSR Frequency
1/TBCK
TBCKH
BCLKT, BCLKR Frequency
BCLKT, BCLKR HIGH Pulse Width
BCLKT, BCLKR LOW Pulse Width
2000
50
---
---
---
---
2000
---
TBCKL
50
---
ns
TFTRH
BCLKT –1 Falling Edge to FST Rising Edge Hold 20
Time
---
ns
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup 80
Time
---
---
ns
TFTFH
TFTFS
BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50
---
---
---
---
ns
ns
FST Falling Edge to BCLKT 1 Falling Edge Setup 50
Time
TBDTD
THID
BCLKT Rising Edge to Valid PCMT Delay Time
10
---
---
60
60
ns
ns
Delay Time from BCLKT 8 Falling Edge to PCMT 10
Output High Impedance
TFRRH
TFRRS
BCLKR –1 Falling Edge to FSR Rising Edge Hold 20
Time
---
---
---
---
ns
ns
FSR Rising Edge to BCLKR 0 Falling edge Setup 80
Time
TFRFH
TFRFS
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50
---
---
---
---
ns
ns
FSR Falling Edge to BCLKR 1 Falling Edge Setup 50
Time
TDRS
TDRH
Valid PCMR to BCLKR Falling Edge Setup Time
PCMR Hold Time from BCLKR Falling Edge
0
---
---
---
---
ns
ns
50
Table 8.2 Short Frame Sync PCM Timing Parameters
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W681513
TFS
FST
BCLKT
PCMT
TFSFH
TFSRS
TFSRH
-1
TBCKH
TBCKL
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
TBCK
THID
TBDTD
TBDTD
THID
TBDTD
TBDTD
D7
D6 D5
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2
MSB
D1 D0
LSB
MSB
TDRS
TDRH
TDRS
TDRH
D7
D6 D5
PCMR
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2
MSB
D1 D0
MSB
LSB
BCH = 0
BCH = 1
B1 Channel
B2 Channel
Figure 8.3 IDL PCM Timing
SYMBOL DESCRIPTION
MIN
TYP
8
MAX
UNIT
kHz
kHz
ns
1/TFS
1/TBCK
TBCKH
TBCKL
TFSRH
FST Frequency
---
---
BCLKT Frequency
2000
50
---
---
---
---
2000
---
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
50
---
ns
BCLKT –1 Falling Edge to FST Rising Edge 20
Hold Time
---
ns
TFSRS
TFSFH
TBDTD
THID
FST Rising Edge to BCLKT 0 Falling edge 60
Setup Time
---
---
---
---
---
---
60
50
ns
ns
ns
ns
BCLKT 0 Falling Edge to FST Falling Edge 20
Hold Time
BCLKT Rising Edge to Valid PCMT Delay 10
Time
Delay Time from the BCLKT 8 Falling Edge 10
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
TDRS
TDRH
Valid PCMR to BCLKT Falling Edge Setup 20
Time
---
---
---
---
ns
ns
PCMR Hold Time from BCLKT Falling Edge 75
Table 8.3 IDL PCM Timing Parameters
Publication Release Date: October, 2005
Revision A11
- 17 -
W681513
TFS
FST
BCLKT
PCMT
TFSFH
TFSRS
TBCKH
TBCKL
TFSRH
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
THID
TFDTD
D7
TBDTD
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
THID
TBDTD
TBDTD
TBCK
D6 D5
D1 D0
LSB
MSB
LSB
TDRS
TDRH
TDRS
TDRH
D7
D6 D5
PCMR
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
D1 D0
MSB
LSB
LSB
BCH = 0
BCH = 1
B1 Channel
B2 Channel
Figure 8.4 GCI PCM Timing
SYMBOL
1/TFST
1/TBCK
TBCKH
TBCKL
DESCRIPTION
MIN
TYP
MAX UNIT
FST Frequency
---
8
---
kHz
BCLKT Frequency
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
2000 ---
2000 kHz
50
50
20
---
---
---
---
---
---
---
---
---
---
---
---
---
60
60
50
ns
ns
ns
ns
ns
ns
ns
ns
TFSRH
TFSRS
TFSFH
BCLKT 0 Falling Edge to FST Rising Edge Hold Time
FST Rising Edge to BCLKT 1 Falling edge Setup Time 60
BCLKT 1 Falling Edge to FST Falling Edge Hold Time
FST Rising Edge to Valid PCMT Delay Time
BCLKT Rising Edge to Valid PCMT Delay Time
20
---
---
TFDTD
TBDTD
THID
Delay Time from the BCLKT 16 Falling Edge (B1 10
channel) or BCLKT 32 Falling Edge (B2 Channel) to
PCMT Output High Impedance
TDRS
TDRH
Valid PCMR to BCLKT Rising Edge Setup Time
PCMR Hold Time from BCLKT Rising Edge
Table 8.4 GCI PCM Timing Parameters
20
---
---
---
---
ns
ns
60
- 18 -
W681513
SYMBOL
DESCRIPTION
MIN
TYP
2000
MAX
UNIT
1/TMCK
Master Clock Frequency
---
---
kHz
TMCKH
TMCK
/
MCLK Duty Cycle for 256 kHz 45%
Operation
55%
TMCKH
TMCKL
TFTRHM
TFTRSM
Minimum Pulse Width HIGH for 50
MCLK(512 kHz or Higher)
---
---
---
---
---
---
---
---
ns
ns
ns
ns
Minimum Pulse Width LOW for MCLK 50
(512 kHz or Higher)
MCLK falling Edge to FST Rising Edge 50
Hold Time
FST Rising Edge to MCLK Falling edge 50
Setup Time
TRISE
TFALL
Rise Time for All Digital Signals
Fall Time for All Digital Signals
---
---
---
---
50
50
ns
ns
Table 8.5 General PCM Timing Parameters
Publication Release Date: October, 2005
Revision A11
- 19 -
W681513
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS
Condition
Junction temperature
Value
1500C
-650C to +1500C
Storage temperature range
Voltage Applied to any pin
(VSS - 0.3V) to (VDD + 0.3V)
(VSS – 1.0V) to (VDD + 1.0V)
-0.5V to +6V
Voltage applied to any pin (Input current limited to +/-20 mA)
VDD - VSS
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS
Condition
Industrial operating temperature
Supply voltage (VDD
Ground voltage (VSS)
Value
-400C to +850C
)
+4.5V to +5.5V
0V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
- 20 -
W681513
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Symbol Parameters
Conditions
Min (2) Typ (1)
Max (2)
Units
VIL
Input LOW Voltage
0.6
V
V
V
V
VIH
VOL
VOH
Input HIGH Voltage
2.4
PCMT Output LOW Voltage
PCMT Output HIGH Voltage
IOL = 3 mA
0.4
IOL = -3 mA
VDD
–
0.4
VDD Current (Operating) - ADC + DAC
VDD Current (Standby)
6
8
mA
IDD
ISB
No Load
FST & FSR =Vss
PUI=VDD
;
10
100
μA
Ipd
IIL
VDD Current (Power Down)
Input Leakage Current
PUI= Vss
0.1
10
μA
μA
μA
VSS<VIN<VDD
+/-10
+/-10
VSS<PCMT<VDD
High Z State
IOL
PCMT Output Leakage Current
CIN
Digital Input Capacitance
10
15
pF
pF
COUT
PCMT Output Capacitance
PCMT High Z
1. Typical values: TA = 25°C , VDD = 5.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
Publication Release Date: October, 2005
- 21 -
Revision A11
W681513
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
;
MCLK=BCLK= 2MHz; FST=FSR=8 kHz synchronous operation
PARAMETER SYM.
CONDITION
TYP.
TRANSMIT
(A/D)
RECEIVE
(D/A)
UNIT
MIN.
MAX.
MIN.
MAX.
Absolute
Level
LABS
1.096
0.775
1.579
1.573
---
---
---
---
VPK
VRMS
VPK
VPK
0 dBm0 = 0dBm @ 600Ω
Max. Transmit TXMAX
Level
---
---
---
---
---
---
---
---
3.17 dBm0 for μ-Law
3.14 dBm0 for A-Law
Absolute Gain GABS
(0 dBm0 @
1020 Hz;
0 dBm0 @ 1020 Hz;
TA=+25°C
0
-0.25
+0.25 -0.25 +0.25 dB
TA=+25°C)
Absolute Gain GABST
variation with
Temperature
0
-0.03
-0.05
+0.03 -0.03 +0.03 dB
+0.05 -0.05 +0.05
TA=0°C to TA=+70°C
TA=-40°C to TA=+85°C
Frequency
Response,
GRTV
15 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
-40
-30
-26
-0.4
-0.5
-0.5
-0.5
-0.5
0
0
0
0
dB
50 Hz
Relative to
0dBm0 @
1020 Hz
60 Hz
---
200 Hz
-1.0
-0.20
-0.35
-0.8
---
300 to 3000 Hz
3300 Hz
+0.15 -0.20 +0.15
+0.15 -0.35 +0.15
3400 Hz
0
-0.8
---
0
3600 Hz
0
0
4000 Hz
---
-14
-32
+0.3
+0.6
+1.6
---
-14
-30
+0.2
+0.4
+1.6
4600 Hz to 100 kHz
+3 to –40 dBm0
-40 to –50 dBm0
-50 to –55 dBm0
---
---
Gain Variation GLT
vs. Level Tone
-0.3
-0.6
-1.6
-0.2
-0.4
-1.6
dB
(1020 Hz
relative to –10
dBm0)
- 22 -
W681513
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
;
MCLK=BCLK= 2MHz; FST=FSR=8 kHz synchronous operation
PARAMETER
SYM.
CONDITION
TRANSMIT (A/D)
MIN. TYP. MAX.
RECEIVE (D/A)
TYP. MAX.
UNIT
MIN.
34
36
30
25
34
36
30
25
---
Total Distortion vs.
Level Tone (1020 Hz,
μ-Law, C-Message
Weighted)
+3 dBm0
36
36
29
25
36
36
29
25
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
-47
---
---
---
---
---
---
---
---
---
---
---
---
---
---
dBC
DLTμ
0 dBm0 to -30 dBm0
-40 dBm0
---
-45 dBm0
---
Total Distortion vs.
Level Tone (1020 Hz,
A-Law, Psophometric
Weighted)
DLTA
+3 dBm0
---
dBp
dB
0 dBm0 to -30 dBm0
-40 dBm0
---
---
-45 dBm0
---
Spurious Out-Of-Band DSPO
at RO+ (300 Hz to
3400 Hz @ 0dBm0)
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8400 Hz to 100000 Hz
300 to 3000 Hz
-30
-40
-30
-47
---
---
Spurious In-Band (700 DSPI
Hz to 1100 Hz @
0dBm0)
---
dB
dB
Intermodulation
Distortion (300 Hz to
3400 Hz –4 to –21
dBm0
DIM
Two tones
---
---
-41
---
---
-41
Crosstalk (1020 Hz @ DXT
0dBm0)
---
---
---
---
-75
---
---
---
---
-75
dBm0
Absolute Group Delay
1200Hz
360
240
μsec
μsec
τABS
Group Delay
500 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
380
130
130
750
18
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
370
120
120
750
13
τD
Distortion (relative to
group delay @ 1200
Hz)
600 Hz
1000 Hz
2600 Hz
2800 Hz
Idle Channel Noise
NIDL
dBrnc0
dBm0p
μ-Law; C-message
-68
-78
A-Law; Psophometric
Publication Release Date: October, 2005
Revision A11
- 23 -
W681513
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
;
PARAMETER
AI Input Offset Voltage
AI Input Current
SYM.
VOFF,AI
IIN,AI
CONDITION
AI+, AI-
MIN.
---
TYP.
MAX.
±25
UNIT.
---
mV
AI+, AI-
---
±0.1
---
±1.0
---
μA
MΩ
pF
V
AI Input Resistance
AI Input Capacitance
RIN,AI
AI+, AI- to VAG
AI+, AI-
10
CIN,AI
---
---
10
AI Common Mode Input Voltage
Range
VCM,AI
AI+, AI-
1.2
---
VDD-1.2
AI Common Mode Rejection
Ratio
CMRRTI AI+, AI-
---
60
---
dB
AI Amp Gain Bandwidth Product GBWTI
---
---
2150
95
---
---
kHz
dB
AO, RLD≥10kΩ
AO, RLD≥10kΩ
C-Message Weighted
RLD=10kΩ to VAG
RLD=2kΩ to VAG
AO, RO to VAG
AO, RO
AI Amp DC Open Loop Gain
AI Amp Equivalent Input Noise
AO Output Voltage Range
GTI
NTI
VTG
---
-24
---
---
dBrnC
V
0.5
1.0
VDD-0.5
---
V
DD-1.0
Load Resistance
RLDTGRO
CLDTGRO
IOUT1
2
---
---
---
---
1
---
100
---
kΩ
pF
Load Capacitance
AO & RO Output Current
RO+ Output Resistance
RO+ Output Offset Voltage
Analog Ground Voltage
VAG Output Resistance
mA
0.5 ≤AO,RO+≤ VDD-0.5
RO+, 0 to 3400 Hz
RO+ to VAG
±1.0
---
RRO+
---
Ω
VOFF,RO+
VAG
---
---
2.5
2.5
mV
V
±25
Relative to VSS
2.429
---
2.573
12.5
RVAG
Within ±25mV change
Transmit
Ω
Power Supply Rejection Ratio (0 PSRR
to 100 kHz to VDD, C-message)
40
40
---
80
75
---
---
---
dBC
Receive
PAI Input Offset Voltage
PAI Input Current
VOFF,PAI
IIN,PAI
PAI
mV
±20
±1.0
---
PAI
---
10
---
±0.05
---
μA
PAI Input Resistance
RIN,PAI
GBWPI
PAI to VAG
PAO- no load
MΩ
kHz
PAI Amp Gain Bandwidth
Product
1000
---
Output Offset Voltage
Load Resistance
VOFF,PO
RLDPO
PAO+ to PAO-
---
---
---
mV
±50
PAO+, PAO-
differentially
300
---
Ω
Load Capacitance
CLDPO
PAO+, PAO-
differentially
---
---
1000
pF
- 24 -
W681513
PARAMETER
PO Output Current
SYM.
IOUTPO
CONDITION
0.5 ≤AO,RO+≤ VDD-0.5
PAO+ to PAO-
MIN.
±10.0
---
TYP.
---
1
MAX.
---
UNIT.
mA
PO Output Resistance
PO Differential Gain
RPO
---
Ω
-0.2
0
+0.2
dB
GPO
RLD=300Ω, +3dBm0, 1
kHz, PAO+ to PAO-
PO Differential Signal to
Distortion C-Message weighted
45
---
---
60
40
40
---
---
---
dBC
dB
DPO
ZLD=300Ω
ZLD=100nF + 100Ω
ZLD=100nF + 20Ω
0 to 4 kHz
PO Power Supply Rejection
Ratio (0 to 25 kHz to VDD
Differential out)
40
---
55
40
---
---
PSRRP
O
,
4 to 25 kHz
Publication Release Date: October, 2005
Revision A11
- 25 -
W681513
10.5. DIGITAL I/O
10.5.1. μ-Law Encode Decode Characteristics
Normalized
Normalized
Encode
Decision
Levels
Digital Code
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
0
Step
Step
Step
8159
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
8031
:
7903
:
4319
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4191
:
4063
:
2143
2079
:
2015
:
1055
1023
:
991
:
511
495
:
479
:
239
231
:
223
:
103
99
:
95
:
35
33
:
31
:
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
- 26 -
W681513
10.5.2. A-Law Encode Decode Characteristics
Normalized
Digital Code
Normalized
Encode
Decision
Levels
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
1
Step
Step
Step
4096
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
3968
:
:
2048
0
0
0
0
0
0
0
2112
:
2048
:
1088
1056
:
1024
:
544
528
:
512
:
272
264
:
256
:
136
132
:
128
:
68
66
:
64
:
2
0
1
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
Publication Release Date: October, 2005
Revision A11
- 27 -
W681513
10.5.3. PCM Codes for Zero and Full Scale
A-Law
μ-Law
Level
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
(D6,D5,D4)
010
Step bits
(D3,D2,D1,D0)
1010
(D7)
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
+ Full Scale
+ Zero
1
1
0
0
000
111
111
000
0000
1111
1111
0000
1
1
0
0
101
0101
- Zero
101
0101
- Full Scale
010
1010
10.5.4. PCM Codes for 0dBm0 Output
A-Law
Chord bits
(D6,D5,D4)
011
μ-Law
Sample
Sign bit Chord bits
Step bits
Sign bit
Step bits
(D3,D2,D1,D0)
0100
(D7)
0
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
0
1
2
3
4
5
6
7
8
001
000
000
001
001
000
000
001
1110
1011
1011
1110
1110
1011
1011
1110
0
0
010
0001
0
0
010
0001
0
0
011
0100
1
1
011
0100
1
1
010
0001
1
1
010
0001
1
1
011
0100
- 28 -
W681513
11. TYPICAL APPLICATION CIRCUITS
VCC
1K
22uF
1.5K
0.1uF
3.9K
330pF
1.0uF
U1
62K
17
18
19
AO
AI-
AI+
14
12
13
8KHz SYNC INPUT
FST
BCLKT
PCMT
select
3.9K
PCM OUTPUT
MICROPHONE
1.0uF
11
2.000 MHz CLOCK IN
PCM INPUT
MCLK
62K
330pF
20K
20
1
VAG
RO+
8
9
7
PCMR
BCLKR
FSR
1.5K
2
3
4
5
RO+
PAI
3K
16
10
PCM MODE CONTROL
POWER CONTROL
PAO-
u/A
PUI
PAO+
SPEAKER
W681513
0.01uF
Figure 11.1 A USB VoIP Phone application
Publication Release Date: October, 2005
Revision A11
- 29 -
W681513
1K
VCC
22uF
C6 330pF
1.5K
R3 3.9K
1.0uF
R5 62K
AO
AI-
AI+
MICROPHONE
1.0uF R4 3.9K
R6 62K
VAG
1.5K
C7 330pF
0.01uF
R8 3K
R9 select
PAO-
R7 20K
PAI
RO+
SPEAKER
PAO+
Figure 11.2 Equivalent Circuit of Figure 11.1
SUGGESTED COMPONENT VALUES BY APPLICATION
SCHEMATIC
COMPONENT #
TELEPHONE
HANDSET
VoIP PHONE
SET
R3,4
R5,6
C6,7
R9
1K
27K
1K
91K
1200 pF
SELECT
20K
330 pF
SELECT
20K
R7
R8
3K
3K
In the handset application the gain from the handset microphone is set to 27 for the input amplifier.
This is because the acoustical chamber in the telephone type handset lets the electret microphone
provide an output of ~28 mVRMS
.
The chamber typically has a gain of 3 over a bare microphone (or
one placed with only a small opening to the outside world.) Because of the high sensitivity of the
earphone (150 Ώ impedance) in a typical handset, the output gain from the Power Amp is set to ~0.16
for a satisfactory listening level.
In the VoIP telephone, or small wireless phones, the plastic case is typically too small to provide a
reasonable acoustic chamber. Thus the output from the microphone is less than in the previous
example. This results in having to set the input gain of the CODEC to ~75 to 90 and in a comparable
- 30 -
W681513
signal level to the receive telephone handset but, because of the increased gain, the Signal-to-Noise
Ratio (SNR) has decreased and the signal sounds noisier. On the receive side, the gain is set as in
the previous example. When the Power Amp gain is as low as 0.16 a 32 ohm load speaker can be
driven.
Resistor R9 sets the sidetone level (the signal fed back to the earpiece from the microphone so the
telephone sounds “live”) to the level desired by the designer.
Capacitors C6 and C7 are introduced for external compensation to keep the input amplifier stable at
such high gain figures and prevent oscillation. These capacitors are not needed when the gain is
close to unity or less than unity.
Publication Release Date: October, 2005
- 31 -
Revision A11
W681513
12. PACKAGE SPECIFICATION
12.2. 20L SOP (SOG)-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
c
1
2
E
E
L
1
1
O
D
0.2
A
Y
GAUGE
A
b
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
2.35
0.10
0.33
0.23
7.40
12.60
MAX.
2.65
0.30
0.51
0.32
7.60
13.00
MIN.
0.093
0.004
0.013
0.009
0.291
0.496
MAX.
0.104
0.012
0.020
0.013
0.299
0.512
A
A1
b
c
E
D
e
1.27 BSC
0.050 BSC
HE
Y
10.00
-
10.65
0.10
1.27
8º
0.394
-
0.419
0.004
0.050
8º
L
0.40
0º
0.016
0º
0
- 32 -
W681513
13. ORDERING INFORMATION
Winbond Part Number Description
W681513_ _
Package Material:
Product Family
W681513 Product
Blank
=
=
Standard Package
Pb-free Package
G
Package Type:
20-Lead Plastic Small Outline Package (SOG/SOP)
S
=
When ordering W681513 series devices, please refer to the following part numbers.
Part Number
W681513S
W681513SG
Publication Release Date: October, 2005
Revision A11
- 33 -
W681513
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A3
October 1,
2003
First published version
Add Important Notice
A10
A11
April 2005
33
2
October,
2005
Added reference to Pb-free RoHS packaging and to VRMS
Capitalized logic HIGH/LOW
Various
22
Added Reference to VRMS
22, 23
23
Extended Test conditions
Corrected Idle Channel Noise min/max and units.
Improved Application Diagrams
29-31
33
Added G package ordering code
- 34 -
W681513
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
The information contained in this datasheet may be subject to change without
notice. It is the responsibility of the customer to check the Winbond USA website
(www.winbond-usa.com) periodically for the latest version of this document, and
any Errata Sheets that may be generated between datasheet revisions.
Publication Release Date: October, 2005
- 35 -
Revision A11
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