W741C240中文资料_数据手册_规格书

W741C240

4-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W741C240 is a high-performance 4-bit microcontroller (mC) that provides an LCD driver. The

device contains a 4-bit ALU, a 8-bit timers, a divider, a 24 ´ 4 LCD driver, and three 4-bit I/O ports.

There are also three interrupt sources and 8-level subroutine nesting for interrupt applications. The

W741C240 operates on low voltage and very low current and has two power reduction modes, hold

mode and stop mode, which help to minimize power dissipation.

The W741C240 is suitable for caculators, simple watches and clocks, multiple I/O products, keyboard

controllers, speech synthesis LSI controllers, and other products.

FEATURES

· Operating voltage: 2.4V to 3.6V (LCD drive voltage: 3.0V or 4.5V)

· Crystal/RC oscillation circuit selectable by code option for system clock

· Crystal oscillator: 32.768 KHz only

· RC oscillator: 1 MHz (maximum)

- High-frequency (400 KHz to 1 MHz) or low-frequency (below 400 KHz) oscillation option must

be determined by the code option.

- In RC mode, attention must be paid to the high/low frequency oscillation option, because the

LCD driver frequency is related to this option.

· Memory

- 2048 ´ 16 bit program ROM (shared with 2K ´ 4 bit look-up table)

- 64 ´ 4 bit data RAM (shared with 16 working registers)

- 24 ´ 4 LCD data RAM

· 13 input/output pins

- Ports for input only: 1 port/4 pins

- Input/output ports: 2 ports/8 pins

- MFP output pin: 1 pin (MFP)

· Power-down mode

- Hold function: no operation (except for oscillator)

- Stop function: no operation (including oscillator)

· Three types of interrupts

- Two internal interrupts (Divider 0, Timer 1)

- One external interrupts (Port RC)

· LCD driver output

- 24 segment ´ 4 common

- Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

Publication Release Date: May 1999

- 1 -

Revision A1

W741C240

· MFP output pin

- Output is software selectable as modulating or nonmodulating frequency

- Works as frequency output specified by Timer 1

· Built-in 14-bit clock frequency divider circuit

· One built-in 8-bit programmable countdown timers

- Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64)

can be selected (output through MFP pin)

· Built-in 18/14-bit watchdog timer selectable for system reset

· Powerful instruction set: 100 instructions

· 8-level subroutine (include interrupt) nesting

· Up to 4 mS instruction cycle (with 1 MHz operating frequency)

· Packaged in 64-pin QFP

PIN CONFIGURATION

S

E

G

2

S

E

G

2

S

E

G

2

S

E

G

2

S

V

D

3

X

O

U

T

E

G

1

V

D

H

1

D

H

2

D

1

D

2

X

I

N

C

N

C

N

C

N

C

N

C

N

C

N

3

2

1

0

9

41

36

35 34 33

51 50 49 48 47 46 45 44 43 42

40 39 38 37

32

31

30

29

28

27

26

25

24

23

22

21

20

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

52

53

54

55

56

57

58

59

60

61

62

63

64

RES

MFP

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RC0

RC1

SEG8

SEG7

SEG6

RC2

1

2

3

4

5

6

7

8

9

11 12 13 14 15 16 17 18 19

10

R

C

3

N

C

N

C

N

C

N

C

V

S

C

O

C

O

C

O

C

O

S

E

S

E

S

E

S

E

S

E

N

C

N

C

N

C

S

E

G

S

M

3

M M M G G

G

2

G

3

G

4

1

2

0

1

5

- 2 -

W741C240

PIN DESCRIPTION

SYMBOL

XIN

I/O

FUNCTION

I

Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT

O

Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

I/O

I

Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

RA0- RA3

RB0- RB3

RC0- RC3

MFP

Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

4-bit port for input only.

Each pin has an independent interrupt capability.

Output pin only.

O

This pin can output modulating or nonmodulating frequency, or Timer 1

clock output specified by mode register 1 (MR1).

I

System reset pin with pull-high resistor.

RES

O

LCD segment output pins.

SEG0- SEG23

Also can be used as DC output ports specified by code option.

O

LCD common signal output pins.

COM0- COM3

Static

Used

1/2 Duty

Used

1/3 Duty

Used

1/4 Duty

Used

COM0

COM1 Not Used

Used

COM2 Not Used Not Used

Used

COM3 Not Used Not Used Not Used

Used

The LCD alternating frequency can be selected by code option.

DH1, DH2

I

Connection terminals for voltage doubler (halver) capacitor.

Positive (+) supply voltage terminal.

Refer to Functional Description.

VDD1, VDD2,

VDD3

VDD

VSS

I

Positive power supply (+).

Negative power supply (-).

Publication Release Date: May 1999

Revision A1

- 3 -

W741C240

BLOCK DIAGRAM

SEG0 to SEG23

COM0 to COM3

VDD1-3 DH1-2

LCD

DRIVER

RAM

(64*4)

PORT RA

PORT RB

RA0-3

RB0-3

ACC

ALU

ROM

(2048*16)

(look_up table

2K*4)

PORT RC

RC0-3

+1(+2)

Central Control

Unit

PC

HEF PEF

EVF SEF

IEF

HCF

STACK

(8 Levels)

PSR0 PM0

PR

.

PM1

MR1

.

SEL

MUL

MFP

Modulation

Frequency

Pulse

Timer 1

(8 Bit)

VDD

VSS

Divider 0

(14 Bit)

Timing Generator

RES

XOUT XIN

- 4 -

W741C240

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses

of the 2048 ´ 16 on-chip ROM containing the program instruction words. When jump or subroutine

call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to

the instruction will be loaded into the program counter. The format used is shown below.

ITEM

Initial Reset

ADDRESS

000H

INTERRUPT PRIORITY

-

1st

2nd

3rd

-

INT 0 (Divider 0)

INT 2 (Port RC)

INT 7 (Timer 1)

JP Instruction

004H

00CH

020H

XXXH

Subroutine Call

-

Stack Register (STACK)

The stack register is organized as 11 bits ´ 8 levels (first-in, last-out). When either a call subroutine or

an interrupt is executed, the program counter will be pushed onto the stack register automatically. At

the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed

to pop the contents of the stack register into the program counter. When the stack register is pushed

over the eighth level, the contents of the first level will be lost. In other words, the stack register is

always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048

´ 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but

the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up

table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.

There are two registers (TABL and TABH) to be used in look-up table addressing and they are

controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is

executed, the contents of the look-up table location address specified by TABH, TABL and ACC will

be read and transfered to the data RAM. Refer to the instruction table for more details. The

organization of the program memory is shown in Figure 1.

Publication Release Date: May 1999

- 5 -

Revision A1

W741C240

16 bits

000H

TABH

TABL

ACC

- x x x x x x x x x y y

2048

address

Offset

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

600H

7FFH

This area can be used to store both instruction code

and look-up table

3

2

1

0

Each element (4 bits) of the look-up table

2048 x 16-bit

Figure 1. Program Memory Organization

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 64 ´ 4 bits. The data memory can be

addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

Working Register

00H

:

0FH

64

address

3FH

64 x 4-bit

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers

(WR). The other data memory is used as general memory and cannot operate directly with immediate

data. The relationship between data memory locations and the page register (PAGE) in indirect

addressing mode is described in the next section.

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W741C240

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

3

_

2

_

1

0

PAGE

R/W

Note: R/W means read/write available.

Bit 3 and Bit2 are reserved.

Bit 1, Bit 0 are indirect addressing mode preselect bits:

00 = Page 0 (00H- 0FH)

10 = Page 2 (20H- 2FH)

01 = Page 1 (10H- 1FH)

11 = Page 3 (30H- 3FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data

between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following

functions:

· Logic operations: ANL, XRL, ORL

· Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC

· Shift operations: SHRC, RRC, SHLC, RLC

· Binary additions/subtractions: ADC, SBC, ADD, SUB, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is

stored in the internal registers. CF can be read out by executing MOVA R, CF.

Clock Generator

The W741C240 provides a crystal or RC oscillation circuit selected by option codes to generate the

system clock through external connections. If a crystal oscillator is used, a crystal must be connected

to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a

crystal oscillator is used, only low-frequency clock (32 KHz) can be selected for the system clock by

means of option codes. If the RC oscillator is used, a resistor in the range of 20 KW to 1.6 MW must

be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32

KHz to 1 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to

4 mS with a 1 MHz system clock.

XIN

or

Resistor

Crystal

32 KHz

XOUT

Figure 3. Oscillator Configuration

Publication Release Date: May 1999

Revision A1

- 7 -

W741C240

Divider 0

Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as

shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC).

When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt

enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag

has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be

reset by executing the CLR DIVR0 instruction.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set

to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is

FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing

the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the

instruction CLR WDT. In normal operation, the application program must reset WDT before it

overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.

The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT

clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT

function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

Divider0

HEF.0

Fosc

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

EVF.0

S

R

. . .

Q14

R

Q1 Q2

Q9 Q10 Q11 Q12 Q13

IEF.0

Q

R

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

WDT

PMF.3

Fosc/16384

Fosc/1024

Overflow signal

Qw1 Qw2 Qw3 Qw4

System Reset

R

Enable

1. Reset

2. CLR WDT

/Disable

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

Timer/Counter

Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 5. Timer 1 can

be used as a counter to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can

be one of two sources: FOSC/64, or FOSC. The source can be selected by setting bit 0 of mode

register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. When the MOV TM1L, R or MOV

TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the

TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1),

- 8 -

W741C240

the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to

down count, and the event flag 7 is reset (EVF.7 = 0). When the timer decrements to FFH, it will

generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will

continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7

= 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1).

The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of

MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then:

Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ¸ (preset value + 1) ¸ 2 (Hz)

Preset value: Decimal number of Timer 1 preset value, and

FOSC: Clock oscillation frequency

MOV TM1L, R

MOV TM1H, R

Underflow

signal

S

R

MR1.3 = 1

Q

EVF.7

4

Auto-reload buffer

8 bits

8-bit Binary

4

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

Enable

Fosc/64

Fosc

F_T

Down Counter

(Timer 1)

2

circuit

MFP

output pin

Disable

MR1.0

Reset

Set MR1.3 to 1

MR1.2

MFP signal

1. MR1.3 = 0

Figure 5. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will

output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between

the tone frequency and the preset value of TM1 is shown in the table below.

Publication Release Date: May 1999

- 9 -

Revision A1

W741C240

3

4

5

Tone

TM1 preset value

& MFP frequency

Tone

TM1 preset value

& MFP frequency

Tone

TM1 preset value

& MFP frequency

frequency

C

C^#

D

130.81

138.59

146.83

155.56

164.81

174.61

185.00

196.00

207.65

220.00

233.08

246.94

7CH

75H

6FH

68H

62H

5DH

58H

53H

4EH

49H

45H

41H

131.07

138.84

146.28

156.03

165.49

174.30

184.09

195.04

207.39

221.40

234.05

248.24

261.63

277.18

293.66

311.13

329.63

349.23

369.99

392.00

415.30

440.00

466.16

493.88

3EH

3AH

37H

34H

31H

2EH

2BH

29H

26H

24H

22H

20H

260.06

277.69

292.57

309.13

327.68

372.36

390.09

420.10

443.81

442.81

468.11

496.48

523.25

554.37

587.33

622.25

659.26

698.46

739.99

783.99

830.61

880.00

932.23

987.77

1EH 528.51

1CH 564.96

1BH 585.14

T

D^#

19H

18H

16H

15H

14H

13H

12H

11H

10H

630.15

655.36

712.34

744.72

780.19

819.20

862.84

910.22

963.76

E

O

F

F ^#

N

E

G

G^#

A

A ^#

B

Note: Central tone is A4 (440 Hz).

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control

the operation of Timer 1. The bit descriptions are as follows:

3

2

1

0

MR1

W

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.

Bit 1

Reserved

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.

Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

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W741C240

Interrupts

The W741C240 provides two internal interrupt sources (Divider 0, Timer 1) and one external interrupt

sources (port RC). Vector addresses for each of the interrupts are located in the range of program

memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the

interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been

set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited

until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by

executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be

released momentarily and the interrupt subroutine will be executed. After the RTN instruction is

executed in an interrupt subroutine, the mC will enter hold mode again. The operation flow chart is

shown in Figure 7. The control diagram is shown below.

Initial Reset

EN INT

Enable

MOV IEF,#I

Divider 0

overflow signal

EVF.0

S

Q

IEF.0

IEF.2

R

Port RC

signal change

Interrupt

Process

Circuit

EVF.2

EVF.7

Interrupt

004H

Vector

00CH

020H

Generator

Timer 1

underflow signal

S

Q

IEF.7

R

Initial Reset

CLR EVF,#I instruction

Disable

DIS INT instruction

Figure 6. Interrupt Event Control Diagram

Stop Mode Operation

In stop mode, all operations of the mC cease (including the operation of the oscillator). The mC enters

stop mode when the STOP instruction is executed and exits stop mode when an external trigger is

activated (by a falling signal on the RC port). When the designated signal is accepted, the mC

awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It

will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the

NOP instruction should follow the STOP command.

Publication Release Date: May 1999

- 11 -

Revision A1

W741C240

Hold Mode Operation

In hold mode, all operations of the mC cease, except for the operation of the oscillator, timer, and

LCD driver. The mC enters hold mode when the HOLD instruction is executed. The hold mode can be

released in one of three ways: by the action of Timer 1, Divider 0, or the RC port. Before the device

enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release

conditions. For more details, refer to the instruction-set table and the following flow chart.

Divider 0, Timer 1,

Signal Change on

Port RC

In

HOLD

Mode?

Yes

No

Interrupt

Enable?

Interrupt

Enable?

Yes

No

IEF

Flag Set?

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Reset EVF.n Flag

Execute

Interrupt Service Routine

HEF

Flag Set?

No

Yes

(Note)

Disable interrupt

PC <- (PC+1)

Disable interrupt

HOLD

Note: The bit of EVF corresponding to the interrupt request signal will be reset.

Figure 7. Hold Mode and Interrupt Operation Flow Chart

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W741C240

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The

HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I

instruction. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

w

HEF

Note: W means write only.

HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released.

HEF.1 Reserved

HEF.2 = 1 Signal change at port RC causes hold mode to be released.

HEF.3, 4 Reserved

HEF.5, 6 Reserved

HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used

to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these

interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are

unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or

EN INT is executed again. Besides, these interrupts can be disabled by executing DIS INT instruction.

The bit descriptions are as follows:

7

6

5

4

3

2

1

0

w

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from Divider 0.

IEF.1 Reserved

IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.

IEF.3, 4 Reserved

IEF.5, 6 Reserved

IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

Publication Release Date: May 1999

Revision A1

- 13 -

W741C240

Port Enable Flag (PEF)

The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be

used to release the hold mode or perform an interrupt function, the content of the PEF must be set

first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

3

2

1

0

PEF

w

Note: W means write only.

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.

PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.

PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.

PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).

Before port RC may be used to make the device exit the stop mode, the content of the SEF must be

set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

3

2

1

0

SEF

w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.

SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.

SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.

SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It

indicates by which interrupt source the hold mode has been released, and it is loaded by hardware.

The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the

HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be

reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF

has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as

follows:

7

6

5

4

3

2

1

0

w

HCF

w

Note: R means read only.

- 14 -

W741C240

HCF.0 = 1 Hold mode was released by overflow from Divider 0.

HCF.1 Reservsd

HCF.2 = 1 Hold mode was released by a signal change on port RC.

HCF.3, 4 Reserved.

HCF.5 = 1 Hold mode was released by underflow from Timer 1.

HCF.6, 7 Reserved.

Event Flag (EVF)

The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset

by the CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

w

EVF

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred.

EVF.1 Reserved

EVF.2 = 1 Signal change on port RC occurred.

EVF.3, 4 Reserved

EVF.5, 6 Reserved

EVF.7 = 1 Underflow from Timer 1 occurred.

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled

by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

3

2

1

0

PMF

W

Note: W means write only.

Bit 0, Bit1, Bit2

Reserved

Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.

= 1 The fundamental frequency of the watchdog timer is FOSC/16384.

Publication Release Date: May 1999

Revision A1

- 15 -

W741C240

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used

to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction.

The bit descriptions are as follows:

3

2

1

0

PM0

w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type.

Bit 0 = 1 RA port is NMOS open drain output type.

Bit 1 = 0 RB port is CMOS output type.

Bit 1 = 1 RB port is NMOS open drain output type.

Bit 2 = 0 RC port pull-high resistor is disabled.

Bit 2 = 1 RC port pull-high resistor is enabled.

Bit 3

Reserved

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used

to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit

descriptions are as follows:

3

2

1

0

PM1

w

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin.

Bit 1 = 0 RA.1 works as output pin.

Bit 2 = 0 RA.2 works as output pin.

Bit 3 = 0 RA.3 works as output pin.

Bit 0 = 1 RA.0 works as input pin.

Bit 1 = 1 RA.1 works as input pin.

Bit 2 = 1 RA.2 works as input pin.

Bit 3 = 1 RA.3 works as input pin.

After initial reset, port RA is in input mode (PM1 = 1111B).

- 16 -

W741C240

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used

to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit

descriptions are as follows:

3

2

1

0

PM2

w

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin.

Bit 1 = 0 RB.1 works as output pin.

Bit 2 = 0 RB.2 works as output pin.

Bit 3 = 0 RB.3 works as output pin.

Bit 0 = 1 RB.0 works as input pin.

Bit 1 = 1 RB.1 works as input pin.

Bit 2 = 1 RB.2 works as input pin.

Bit 3 = 1 RB.3 works as input pin.

After initial reset, port RB is in input mode (PM2 = 1111B).

Reset Function

The W741C240 is reset either by a power-on reset or by using the external RES pin. The initial state

of the W741C240 after the reset function is executed is described below.

Program Counter (PC)

TM1

000H

Reset

MR1, PM0, PAGE, PMF registers

PM1, PM2 registers

Reset

Set (1111B)

Reset

PSR0 register

IEF, HEF, HCF, PEF, EVF, SEF flags

Timer 1 input clock

Reset

FOSC

MFP output

Low

Input/output ports RA,RB

RA & RB ports output type

RC ports pull-high resistors

Input clock of the watchdog timer

LCD display

Input mode

CMOS type

Disabled

FOSC/1024

OFF

Segment output mode

LCD drive output

Publication Release Date: May 1999

Revision A1

- 17 -

W741C240

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. After initial reset,

input/output ports RA and RB are both in input mode. When RA and RB are used as output ports,

CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or

RB can be specified as input or output mode independently by the PM1 and PM2 registers. The

MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV

RB, R operate the output functions. For more details, refer to the instruction table and Figure 8.

Input/Output Pin of the RA(RB)

Vdd

PM0.0 (or PM0.1)

Output

Buffer

I/O PIN

RA.n(RB.n)

Enable

DATA

BUS

PM1.n

(or PM2.n)

MOV RA, R

(or MOV RB, R)

Instruction

Enable

MOVA R, RA

(or MOVA R, RB)

instruction

Figure 8. Architecture of Input/Output Pins

Input Ports RC

Port RC consists of pins RC.0 to RC.3. Each pin of port RC can be connected to a pull-up resistor,

which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to

the RC port are set, a signal change on the specified pins of port RC will execute the hold mode

release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any

signal changes on the pins that make up the port. PSR0 can be read out and cleared by the MOV R,

PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified

by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 9 and the

instruction table for more details. The RD port is used as input port only, it has no hold mode release,

wake-up stop mode or interrupt functions.

- 18 -

W741C240

DATA BUS

PEF.0

PM0.2

PSR0.0

D

Q

Signal

change

detector

ck

R

RC.0

RC.1

HEF.2

EVF.2

PEF.1

PEF.2

PEF.3

D

ck

Q

HCF.2

PSR0.1

PSR0.2

PSR0.3

D

ck

Q

Signal

change

detector

R

IEF.2

INT 2

PM0.2

D

ck

Signal

change

detector

CLR EVF, #I

Reset

RC.2

RC.3

D

ck

Signal

change

detector

Reset

MOV PEF, #I

CLR PSR0

SEF.0

SEF.1

SEF.2

SEF.3

Falling

edge

detector

Falling

edge

detector

Wake up from STOP mode

Falling

edge

detector

Falling

edge

detector

Figure 9. Architecture of Input Ports RC

Port Status Register 0 (PSR0)

Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or

cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

3

2

1

0

PSR0

R

Note: R means read only.

Bit 0 = 1 Signal change on RC.0.

Bit 1 = 1 Signal change on RC.1.

Bit 2 = 1 Signal change on RC.2.

Bit 3 = 1 Signal change on RC.3.

Publication Release Date: May 1999

Revision A1

- 19 -

W741C240

MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is

determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of

MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal

from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz,

2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to

specify the modulation output combination. The data specified by the 8-bit operand and the MFP

output pin are shown as below:

(FOSC = 32.768 KHz)

R7 R6

R5

0

1

0

1

0

1

0

1

R4

0

1

0

1

0

1

0

1

0

R3

0

1

0

1

0

1

0

1

0

R2

0

1

0

1

0

1

0

1

0

R1

0

1

0

1

0

1

0

1

0

R0

0

1

0

1

0

1

0

1

0

FUNCTION

Low level

128 Hz

64 Hz

0 0

8 Hz

4 Hz

2 Hz

1 Hz

High level

128 Hz

64 Hz

0 1

1 0

1 1

8 Hz

4 Hz

2 Hz

1 Hz

2048 Hz

2048 Hz * 128 Hz

2048 Hz * 64 Hz

2048 Hz * 8 Hz

2048 Hz * 4 Hz

2048 Hz * 2 Hz

2048 Hz * 1 Hz

4096 Hz

4096 Hz * 128 Hz

4096 Hz * 64 Hz

4096 Hz * 8 Hz

4096 Hz * 4 Hz

4096 Hz * 2 Hz

4096 Hz * 1 Hz

- 20 -

W741C240

LCD Controller/Driver

The W741C240 can directly drive an LCD with 24 segment output pins and 4 common output pins for

a total of 24 ´ 4 dots. Option codes can be used to select one of five options for the LCD driving

mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure

12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. The

structure of the LCD alternating frequency (FLCD) is shown in the figure below.

Divider 0

Fosc

Timing

Generator

Q1 Q2 Q3 Q4 Q5 Q6

Q14

...

Fosc/32

High frequency clock

Fw

Low frequency clock

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

Fw/64

Fw/128

Fw/256

Fw/512

Selector

F_LCD

Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram

Data Bus

Option Codes

LCD Frequency

Selection

LCD Data RAM

(24 x 4 bits)

LCD Drive

Mode

Selection

Fw

Clock

Generator

LCD Mode

Controller

LCD Duty & Bias

F_LCD

LCD

DH1

DH2

Waveform

Segment

Driver/Controller

LCD Voltage

Controller

Common

Driver

V_DD

VSS

V_{DD1 to 3}

SEG0 to 23

COM0 to 3

Figure 12. LCD Driver/Controller Circuit Diagram

Publication Release Date: May 1999

Revision A1

- 21 -

W741C240

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY

Fw/512 (64 Hz)

STATIC

64

1/2 DUTY

32

1/3 DUTY

1/4 DUTY

21

43

16

32

Fw/256 (128 Hz)

Fw/128 (256 Hz)

Fw/64 (512 Hz)

128

64

256

128

85

64

512

256

171

128

Corresponding to the 24 LCD drive output pins, there are 24 LCD data RAM segments (LCDR00 to

LCDR17). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR,

ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the

segment output pins automatically without program control. When the bit value of the LCD data RAM

is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," the LCD is turned off.

The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 23 pins by

a direct memory access. The relationship between the LCD data RAM and segment/common pins is

shown below.

COM3

bit 3

0/1

COM2

bit 2

0/1

COM1

bit 1

0/1

COM0

bit 0

0/1

LCD data RAM

LCDR00

Output pin

SEG0

LCDR01

SEG1

0/1

.

LCDR16

LCDR17

SEG22

SEG23

0/1

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction

turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state

ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON

must be executed. The relationship between the LCD drive mode and the maximum number of

drivable LCD segments is shown below.

LCD DRIVE MODE

MAX. NUMBER OF

DRIVABLE LCD SEGMENTS

CONNECTION AT

POWER INPUT

Static

24 (COM1)

Connect VDD3, VDD2 to VDD1

1/2 bias 1/2 duty

1/2 bias 1/3 duty

1/3 bias 1/3 duty

1/3 bias 1/4 duty

Connect VDD3 to VDD2

48 (COM1- COM2)

72 (COM1- COM3)

96 (COM1- COM4)

Connect VDD3 to VDD2

-

The output waveforms for the five LCD driving modes are shown below.

- 22 -

W741C240

Static Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

VDD2

VDD1

VSS

Unlit LCD driver

outputs

Lit LCD driver

outputs

VDD2

VDD1

VSS

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

COM1

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0,

COM1 sides

being unlit

VDD2

VDD1

VSS

LCD driver

outputs for

only seg. on

COM0 side

being lit

VDD2

VDD1

VSS

LCD driver

outputs for

only seg. on

COM1 side

being lit

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0,

COM1 sides

being lit

VDD2

VDD1

VSS

Publication Release Date: May 1999

Revision A1

- 23 -

W741C240

1/2 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

VDD2

VDD1

VSS

COM1

COM2

VDD2

VDD1

VSS

VDD2

VDD1

VSS

LCD driver

outputs for all

seg. on COM0,1,2

sides being unlit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0

side being lit

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM1

side being lit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0,1

sides being lit

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM2

side being lit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0,2

sides being lit

- 24 -

W741C240

1/3 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

VDD3

VDD2

VDD1

VSS

COM0

COM1

VDD3

VDD2

VDD1

VSS

VDD3

VDD2

VDD1

VSS

COM2

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for all

seg. on COM0,1,2

sides being unlit

LCD driver

VDD3

VDD2

VDD1

VSS

outputs for only

seg. on COM0

side being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM1

side being lit

LCD driver

outputs for seg.

on COM0,2

VDD3

VDD2

VDD1

VSS

sides being lit

LCD driver

outputs for seg.

on COM1,2

VDD3

VDD2

VDD1

VSS

sides being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for seg.

on COM0,1,2

sides being lit

Publication Release Date: May 1999

Revision A1

- 25 -

W741C240

1/3 Bias 1/4 Duty Lighting System (Example)

Normal Operating Mode

VDD3

VDD2

VDD1

VSS

COM0

VDD3

VDD2

VDD1

VSS

COM1

COM2

VDD3

VDD2

VDD1

VSS

VDD3

VDD2

VDD1

VSS

COM3

LCD driver

outputs for

only seg. on

COM0 side

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

only seg. on

COM1 side

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0,

COM1 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM1,

COM2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

- 26 -

W741C240

1/3 Bias 1/4 Duty Normal Lighting System, continued

LCD driver

outputs for

seg. on COM1

COM2 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0

COM2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0

COM1,2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

The power connections for each LCD driving mode, which are determined by a mask option, are

shown below.

Static LCD Configuration

1/2 Bias LCD Configuration

DH1

0.1uF

DH2

DH1, DH2 floating

DH2

VSS

VDD

C

H

I

P

H

I

P

VDD

0.1uF

VDD1

VDD2

VDD3

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD3 = VDD

VDD1 = VDD2 = VDD3 = VDD

Publication Release Date: May 1999

Revision A1

- 27 -

W741C240

LCD Configuration, continued

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

C

H

I

VDD

0.1uF

P

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD, VDD3 = 3/2 VDD

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

VDD

C

H

I

P

VDD

0.1uF

VDD1

VDD2

VDD3

VDD1 = 1/3 VDD, VDD2 = 2/3 VDD, VDD3 = VDD

- 28 -

W741C240

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage to Ground Potential

Applied Input/Output Voltage

Power Dissipation

RATING

-0.3 to +7.0

120

UNIT

V

mW

°C

Ambient Operating Temperature

Storage Temperature

0 to +70

-55 to +150

°C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC CHARACTERISTICS

(VDD- VSS = 3.0V, FOSC. = 32.768 KHz, TA = 25° C; unless otherwise specified)

PARAMETER

Op. Voltage

SYM.

VDD

IOP1

IOP2

IHM1

CONDITIONS

-

MIN.

TYP.

MAX.

3.6

15

UNIT

V

2.4

-

8

Op. Current (Crystal type)

Op. Current (RC type)

No load (Ext-V)

-

mA

35

4

60

Hold Current (Crystal type)

Hold mode

6

No load (Ext-V)

Hold Current (RC type)

Stop Current (Crystal type)

Stop Current (RC type)

IHM2

ISM1

ISM2

Hold mode

No load (Ext-V)

-

16

0.1

40

2

mA

Stop mode

No load (Ext-V)

Stop mode

2

No load (Ext-V)

Input Low Voltage

VIL

VIH

-

VSS

-

0.3 VDD

V

Input High Voltage

0.7 VDD

VDD

MFP Output Low Voltage

MFP Output High Voltage

Port RA, RB Output Low Voltage

Port RA, RB Output high Voltage

LCD Supply Current

VML

VMH

IOL = 3.5 mA

IOH = -3.5 mA

-

2.4

-

0.4

V

-

0.4

-

V

VABL IOL = 2.0 mA

VABH IOH = -2.0 mA

V

2.4

-

V

ILCD

IOL

All Seg. On

6

mA

VOL = 0.4V

4

-

SEG0- SEG23 Sink Current

VLCD = 0.0V

(work as LCD output pins)

IOH

VOH = 2.4V

VLCD = 3.0V

15

-

SEG0- SEG23 Drive Current

mA

(work as LCD output pins)

Publication Release Date: May 1999

Revision A1

- 29 -

W741C240

DC Characteristics, continued

PARAMETER

SYM.

RCD

CONDITIONS

MIN.

100

20

TYP.

350

MAX.

1000

500

UNIT

KW

Input Port Pull-up Resistor

Port RC, RD

-

RRES

100

KW

RES Pull-up Resistor

AC CHARACTERISTICS

(VDD- VSS = 3.0V, TA = 25° C; unless otherwise specified)

PARAMETER

Op. Frequency

SYM.

CONDITIONS

MIN.

TYP.

-

MAX. UNIT

FOSC RC type

Crystal type (Option

-

1000

32.768

-

KHz

%

low-speed type)

Frequency Deviation by

Voltage Drop for RC

Oscillator

-

10

f(3V)- f(2.4V)

Df

f(3V)

f

Instruction Cycle Time

Reset Active Width

TI

One machine cycle

-

4/FOSC

-

mS

TRAW FOSC = 32.768 KHz

1

mS

- 30 -

W741C240

PAD ASSIGNMENT & POSITIONS

m

2140 m

51 50 49 48 47 46 45 44 43 42

39

37

38

41

40

36

1

35

34

33

2

3

4

Y

32

31

30

2110 mm

5

6

X

(0,0)

7

8

29

28

27

26

9

10

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Note: The chip substrate must be connected to system ground (VSS).

PAD NO. PAD NAME

X

Y

PAD NO. PAD NAME

X

Y

1

2

VSS

-915.00

603.23

466.18

327.00

187.83

48.65

11

12

13

14

15

16

17

18

19

20

SEG5

SEG6

-905.00

-775.00

-645.00

-515.00

-385.00

-258.00

-131.00

-4.00

-900.00

COM3

COM2

COM1

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

3

SEG7

4

SEG8

5

SEG9

6

-86.23

-216.23

-346.23

-476.23

-606.23

SEG10

SEG11

SEG12

SEG13

SEG14

7

8

9

123.00

250.00

10

Publication Release Date: May 1999

Revision A1

- 31 -

W741C240

Pad positions, continued

PAD NO. PAD NAME

X

Y

PAD NO. PAD NAME

X

Y

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

VDD3

377.00

507.00

637.00

767.00

897.00

907.00

897.00

767.00

-900.00

-644.45

-514.45

-384.45

-254.45

-124.45

5.55

41

42

43

44

45

46

47

48

49

50

51

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RC0

RC1

RC2

RC3

377.00

250.00

123.00

-4.00

879.10

-131.00

-258.00

-385.00

-515.00

-645.00

-775.00

-905.00

VDD2

VDD1

135.55

265.55

395.55

525.55

655.55

879.10

DH2

DH1

VDD

XOUT

XIN

RES

MFP

RA0

39

40

637.00

507.00

879.10

- 32 -

W741C240

TYPICAL APPLICATION CIRCUIT

Vcc

V_DD

COM0

RA0

RA3

LCD

Output Signal

PANEL

COM3

SEG0

(1/3 Bias

1/4 Duty)

RB0

RB1

RB2

RB3

SEG23

DH1

RC0

RC1

RC2

RC3

DH2

V_DD1

V_DD2

V_DD3

Connect to capacitor and VDD

to generate LCD voltage

RES

Vcc

XOUT

XIN

or

MFP

V_SS

Publication Release Date: May 1999

Revision A1

- 33 -

W741C240

INSTRUCTION SET TABLE

Symbol Description

ACC:

ACC.n:

WR:

PAGE:

MR1:

PM0:

PM1:

PM2:

PSR0:

R:

Accumulator

Accumulator bit n

Working Register

Page Register

Mode Register 1

Port Mode 0

Port Mode 1

Port Mode 2

Port Status Register 0

Memory (RAM) of address R

LCD data RAM of address LDR

Memory bit n of address R

Constant parameter

Branch or jump address

LCDR:

R.n:

I:

L:

CF:

ZF:

Carry Flag

Zero Flag

PC:

Program Counter

TM1:

Timer 1

IEF.n:

HCF.n:

HEF.n:

SEF.n:

PEF.n:

EVFn:

BF:

Interrupt Enable Flag n

HOLD mode release Condition Flag n

HOLD mode release Enable Flag n

STOP mode wake-up Enable Flag n

Port Enable Flag n

Event Flag n

Backup Flag

! =:

&:

Not equal

AND

^:

OR

- 34 -

W741C240

Symbol Description, continued

EX:

Exclusive OR

Transfer direction, result

¬ :

[PAGE*10H+()]: Contents of address PAGE(bit2, bit1, bit0)*10H+()

[P()]: Contents of port P()

INSTRUCTION SET TABLE 1

MNEMONIC

FLAG

CYCLE

FUNCTION

AFFECTED

Arithmetic

ADD

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R

ZF, CF

1

ACC¬ (R) + (ACC)

ADD

ACC¬ (WR) + I

ADDR

ADC

ACC, R¬ (R) + (ACC)

ACC, WR¬ (WR) + I

ACC¬ (R) + (ACC) + (CF)

ACC¬ (WR) + I + (CF)

ACC, R¬ (R) + (ACC) + (CF)

ACC, WR¬ (WR) + I + (CF)

ACC¬ (R) - (ACC)

ADC

ADCR

SUB

ACC¬ (WR) - I

SUBR

SBC

ACC, R¬ (R) - (ACC)

ACC, WR¬ (WR) - I

ACC¬ (R) - (ACC) - (CF)

ACC¬ (WR) - I - (CF)

ACC, R¬ (R) - (ACC) - (CF)

ACC, WR¬ (WR) - I - (CF)

ACC, R¬ (R) + 1

SBC

SBCR

INC

DEC

R

ACC, R¬ (R) - 1

Publication Release Date: May 1999

Revision A1

- 35 -

W741C240

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

CYCLE

AFFECTED

Logic Operations

ANL

ANLR

ORL

ORLR

XRL

XRLR

Branch

JMP

JB0

R, ACC

WR, #I

R, ACC

WR, R #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

ZF

1

ACC¬ (R) & (ACC)

ACC¬ (WR) & I

ACC, R¬ (R) & (ACC)

ACC, WR¬ (WR) & I

ACC¬ (R) Ù (ACC)

ACC¬ (WR) Ù I

ACC, R¬ (R) Ù (ACC)

ACC, WR¬ (WR) Ù I

ACC¬ (R) EX (ACC)

ACC¬ (WR) EX I

ACC, R¬ (R) EX (ACC)

ACC, WR¬ (WR) EX I

L

1

PC10- PC0¬ L10- L0

PC10- PC0¬ L10- L0; if ACC.0 = "1"

PC10- PC0¬ L10- L0; if ACC.1 = "1"

PC10- PC0¬ L10- L0; if ACC.2 = "1"

PC10- PC0¬ L10- L0; if ACC.3 = "1"

PC10- PC0¬ L10- L0; if ACC = 0

PC10- PC0¬ L10- L0; if ACC ! = 0

PC10- PC0¬ L10- L0; if CF = "1"

PC10- PC0¬ L10- L0; if CF ! = "1"

JB1

JB2

JB3

JZ

JNZ

JC

JNC

- 36 -

W741C240

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

CYCLE

AFFECTED

Data Move

MOV

MOVA

MOV

MOVC

WR, R

R, WR

WR, R

R, WR

R, ACC

ACC, R

R, #I

1

2

1

2

WR¬ (R)

R¬ (WR)

ZF

ACC, WR¬ (R)

ACC, R¬ (WR)

R¬ (ACC)

ACC¬ (R)

R¬ I

ZF

WR, @R

@R, WR

TABH, R

TABL, R

R

WR¬ [PR (bit2, bit1, bit0) ´ 10H + (R)]

[PR (bit2, bit1, bit0) ´ 10H +(R)]¬ WR

TAB High addresss ¬ R

TAB Low addresss ¬ R

R¬ [ TAB ´ 10H + (ACC)]

Input & Output

MOVA

MOV

R, RA

ZF

1

ACC, R¬ [RA]

ACC, R¬ [RB]

ACC, R¬ [RC]

[RA]¬ (R)

R, RB

R, RC

RA, R

RB, R

MFP, #I

MOV

[RB]¬ (R)

MOV

[MFP]¬ I

Flag & Register

MOVA

MOV

MOVA

MOV

R, PAGE

ZF

1

ACC, R¬ PAGE (Page Register)

PAGE¬ (R)

PAGE, R

PAGE, #I

MR0, #I

MR1, #I

R, CF

PAGE¬ I

MR0¬ I

MR1¬ I

ZF

CF

ACC.0, R.0¬ CF

CF¬ (R.0)

CF, R

Publication Release Date: May 1999

Revision A1

- 37 -

W741C240

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

ACC, R¬ HCF0- HCF3

FLAG

AFFECTED

CYCLE

MOVA

CLR

R, HCFL

R, HCFH

PMF, #I

PM0, #I

PM1, #I

PM2, #I

EVF, #I

PEF, #I

IEF, #I

ZF

1

ACC, R¬ HCF4- HCF7

Clear Parameter Flag if In = 1

Set Parameter Flag if In = 1

Port Mode 0¬ I

SET

MOV

CLR

Port Mode 1¬ I

Port Mode 2¬ I

Clear Event Flag if In = 1

Set/Reset Port Enable Flag

Set/Reset Interrupt Enable Flag

Set/Reset HOLD mode release Enable Flag

MOV

HEF, #I

SEF, #I

Set/Reset STOP mode wake-up Enable Flag

for RC port

MOVA

CLR

SET

CLR

R, PSR0

PSR0

CF

ZF

1

ACC, R¬ Port Status Register 0

Clear Port Status Register 0

Set Carry Flag

CF

Clear Carry Flag

DIVR0

WDT

Clear last 4 bits of Divider 0

Clear Watchdog Timer

Shift & Rotate

SHRC

RRC

R

ZF, CF

1

ACC.n, R.n¬ (R.n+1);

ACC.3, R.3¬ 0; CF¬ R.0

ACC.n, R.n¬ (R.n+1);

ACC.3, R.3¬ CF; CF¬ R.0

ACC.n, R.n¬ (R.n-1);

SHLC

RLC

ACC.0, R.0¬ 0; CF¬ R.3

ACC.n, R.n¬ (R.n-1);

ACC.0, R.0¬ CF; CF¬ R.3

- 38 -

W741C240

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

LCD

MOV

LCDR, #I

1

LCDR¬ I

MOV

WR, LCDR

LCDR, WR

LCDR, ACC

WR¬ (LCDR)

LCDR¬ (WR)

LCDR¬ (ACC)

LCD ON

MOV

LCDON

LCDOFF

Timer

MOV

LCD OFF

TM1H, R

TM1L, R

1

Timer 1 High register ¬ R

Timer 1 Low register ¬ R

MOV

Subroutine

CALL

L

1

STACK ¬ (PC)+1;

PC10- PC0 ¬ L10- L0

RTN

Other

HOLD

STOP

NOP

EN

(PC)¬ STACK

Enter Hold mode

1

Enter Stop mode

No Operation

INT

Enable Interrupt Function

Disable Interrupt Function

DIS

Publication Release Date: May 1999

Revision A1

- 39 -

W741C240

NOTES:

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

FAX: 886-3-5792766

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

- 40 -

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.84	具有ADC：	NO
地址总线宽度：		位大小：	4
最大时钟频率：	1 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：
JESD-30 代码：	R-PQFP-G64	I/O 线路数量：	13
端子数量：	64	最高工作温度：	70 °C
最低工作温度：		PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
认证状态：	Not Qualified	ROM可编程性：	MROM
最大供电电压：	3.6 V	最小供电电压：	2.4 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子位置：	QUAD
uPs/uCs/外围集成电路类型：	MICROCONTROLLER	Base Number Matches：	1

型号	制造商	描述	价格	文档
W741C250	ETC	4-Bit Microcontroller	获取价格
W741C260	WINBOND	4-BIT MICROCONTROLLER	获取价格
W741E200	ETC	4-Bit Microcontroller	获取价格
W741E201	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格
W741E202	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格
W741E203	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格
W741E204	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格
W741E204S	WINBOND	暂无描述	获取价格
W741E205	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格
W741E20X	WINBOND	4-BIT FLASH MICROCONTROLLER	获取价格

W741C240

W741C240 概述

W741C240 规格参数

W741C240 数据手册

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